Special Functions Framework Output Module Used for L1_Qualifier - L3_Trans_Num Multiplexer and for "Special Functions" --------------------------------------------- Original: 21-APR-1998 Latest: 31-JAN-2002 The current idea is that a single AONM/FOM circuit board will be used to implement both the Multiplexer for the L1_Qualifiers - L3_Transfer_Number and the "special functions" that need to be derived from the Specific Triggers Fired Bus. It is not pictured, however, that all of these requirements will be met by a single FPGA design. One FPGA design will be required for the Multiplexer for the L1 Qualifiers - L3 Transfer Number and at least one FPGA design will be required for the "special functions." The Multiplexer for the L1_Qualifiers - L3_Transfer_Number FOM These FOM FPGA's preform the normal FOM function and in addition contain: a 16 bit L3_Transfer_Number counter, a multiplexer to select 4 bits of the L3_Trans_Num, a multiplexer to select sending out either the normal L1_Qualifiers or the L3_Trans_Num, and a multiplexer to select either all 4 normal FOM L1_Qualifiers or 3 normal FOM L1_Qualifiers and 1 Hardware Source L1_qualifier. A block diagram of this functions is shown. Hardware +---------+ +---------+ HSRO Source L1_Qual | 1 Wide | | HSRO & |----> ----------------------/---------| 2 Input | --->| Monitor | 1 | MUX |--- | | Readout |----> ---| VME CTRL| | | +---------+ VME +----------+ 1 | +---------+ | 1 | Spec | | | | \----------------\ Trg's | Normal | | | | ---\-----| FOM |---\---/--------\-------\----/--\ | 128 | Function | 4 3 4 \ | Fired | | | +---------+ | +----------+ ----| 4 Wide | | P1_TS #1 | 2 Input |--/-> Inc. +----------+ +----------+ ----| MUX | 4 L3# Gate | | | 4 Wide | | | RT CTRL | MSA ---------| L3_Trans | | 4 Input | / +---------+ Out | Number |---/-----| MUX |--------/--/ | Tick | 16 bit | 16 | VME CTRL | 4 | Select ---------> Counter | +----------+ | Clock +----------+ | P1_TS #2 Send L2 Decision >------/ In addition to this Multiplexer for the L1_Qualifiers - L3_Transfer_Number on this same FOM card we need to generate an electrical copy of the L3_Transfer_Number that is available on an MSA_Outputs all of the time. Because the FOM card has only 4 MSA_Output lines per FPGA site, we need to generate this 16 bit L3_Trans_Num 4 bits at a time and have a mux to select which 4 bits are sent out MSA_Output lines. We also would need to provide HSRO for this L3_Transfer_Number. Well this function can be meant by using the same FPGA design as is used for the L1_Qualifier - L3_Trans_Num Multiplexer and just leaving the multiplexer always selecting the L3_Trans_Num. Setup this way the active part of this FPGA design looks like: P1 Inc. +----------+ +----------+ L3# Gate | | | 4 Wide | MSA_Output ---------| L3_Trans | | 4 Input | 4 | Number |---/-----| MUX |-----/-----------------\------> Tick | 16 bit | 16 | VME CTRL | 4 \ ---------> Counter | +----------+ | +---------+ Clock +----------+ | | Monitor | |---| Readout |-----> | +---------+ VME 4 | | +---------+ | | HSRO | |---| Readout |-----> +---------+ HSRO The programming interface for this FPGA will include (in addition to the usual AONM/FOM programming interface) a 16 bit regsiter to control the multiplexers for the Hardware Source L1 Qualifier selection and for the L3 Transfer Number bit selection. This register will be located at VME register address 48 with the following bit allocation: Bit Access Contents --- ------ -------- 0 R/W Select Hardware Source L1 Qualifier 2:1 R/W Select L3 Transfer Number Bits (3:0, 7:4, 11:8, or 15:12) 4:3 R/W Select MSA Ouptuts (0: always send L1 Qualifiers 1: always send L3 Xfer Number) 2: Timing Signal selects L1 Qualifiers or L3 Xfer Number) The "Special Functions" part of this FOM currently includes the following special functions: 1. Skip Next Beam Crossing signal Will need at least 2 copies of this signal: one copy for a Global Disable to the TDM cards and another copy to go to the 8x 159 Per Bunch Scalers as a "possibly correlated" gate signal. Most likely will want a spare copy or two of this signal. It is a general purpose "strobe" that is asserted near the end of every tick that contains a L1 trigger. It (verified by the clock edge at the beginning of the next tick) could be used for example: to clock the L1 Spec Trig's Fired mask into the TRM's that feed the L2 Framework or to Increment a scaler that needs to get ready ahead of time for the next L1 Trigger. So we want to make perhaps 4 of these. 2. Generic L1 Spec Trig Fired Strobe The only way to have a full tick length L1 Trig Fired strobe is to have it asserted for the tick following the tick that contained the L1 Trigger. Such a Strobe would be useful for somethings, e.g. incrementing a scaler after a L1 Trig to get ready for the next L1 Trigger. We should make ?? copies of this L1 Spec Trig Fired Strobe. 3. Skip Next N Ticks Programmable N We want perhaps 4 of these. It is asserted on the tick after the tick that contained the L1 Trig and it remains asserted for N ticks where N is programmable by TCC. These signals feed back to And-Or Input Terms. Note that all of these Special Functions are the normal FOM function followed by something like a latch or counter that enabled a signal for N ticks. The following diagram reminds us of what Run II FW timing looks like. Recall that the TRM's and the TDM's basically clock a latch to begin each tick while the AONM's and FOM's are not latched. Tick with Tick Clock |<---->|<---->|<---->|<---->|<---->|<---->|<---->|<---->| Typ FOM Output ------- G.S. L1 Acpt ------------ ----------------------------------- | | | | | | | | | SF FOM Output ------- Skip Next ------------ ----------------------------------- | | | | | | | | | SF FOM Output ------- L1 Fired Strb --------------- ----------------------------------- | | | | | | | | | SF FOM Output ---------------------------- Skip Next "N" --------------- -------------- First recall the mapping of FPGA site to MSA_Outputs on the FOM card: FPGA Site Number Generates these MSA_Outputs --------- -------------------------------- 0 (VME Interface FPGA) 1 MSA_Output(3:0) 2 MSA_Output(7:4) 3 MSA_Output(11:8) 4 MSA_Output(15:12) 5 MSA_Output(19:16) 6 MSA_Output(23:20) 7 MSA_Output(27:24) 8 MSA_Output(31:28) 9 MSA_Output(35:32) 10 MSA_Output(39:36) 11 MSA_Output(43:40) 12 MSA_Output(47:44) 13 MSA_Output(51:48) 14 MSA_Output(55:52) 15 MSA_Output(59:56) 16 MSA_Output(63:60) 17 (Board Support Functions BSF FPGA) Now add to this table what the various MSA-Outputs will be used for and where these signals will go: FPGA Front Site Generates these Paddle MSA_Output Signals Numb MSA_Outputs Conn. Function and Destination ---- ----------------- ------ ---------------------------------- 1 MSA_Output(3:0) \ J 15:0 are the Multiplexed output 2 MSA_Output(7:4) | 15 of the L1 Qualifier Set 0 3 MSA_Output(11:8) | :0 and L3 Transfer Number. This 4 MSA_Output(15:12) / goes to the SCL Hub End. 5 MSA_Output(19:16) \ J 31:16 are the Multiplexed output 6 MSA_Output(23:20) | 31 of the L1 Qualifier Set 1 7 MSA_Output(27:24) | :16 and L3 Transfer Number. This 8 MSA_Output(31:28) / goes to the SCL Hub-End. 9 MSA_Output(35:32) \ J 35:32 4 copies of Skip Next 10 MSA_Output(39:36) | 47 39:36 4 copies of L1 Trig Strobe 11 MSA_Output(43:40) | :32 43:40 4 Skip next N Programmable 12 MSA_Output(47:44) / 47:44 4 Diagnostic Scaler Control 13 MSA_Output(51:48) \ J 63:48 outputs are NOT used 14 MSA_Output(55:52) | 63 All 4 of these FPGA sites (13,14,15, 15 MSA_Output(59:56) | :48 16) are used for Miguel FPGA's to 16 MSA_Output(63:60) / readout the Spec Trig's Fired Mask. P5 Global I/O Signals The Hardware Source L1 Qualifiers are received on this FOM card via the P5 Global I/O connector. P5 Signal Signal - Function - Source --------- ---------------------------------------------------------- P5(7:0) These pins are used to receive a Mark_&_Force_Pass signal from each of the 8 TDM cards. These 8 Signals are "ORed" before they become the Harware_Source_L1_Qualifier signal that goes to FPGA sites #1 and # 5. In these FPGA's this "ORed" signal can be selected as L1_Qualifier #3. These FPGA site's make L1_Qualifiers 3:0 P5-8 This pin is used to receive the Hardware_Source_L1_Qualifier that goes to FPGA sites #2 and #6 where it can be selected as L1_Qualifier #7. These FPGA sites make L1_Qualifiers 7:4. P5-9 This pin is used to receive the Hardware_Source_L1_Qualifier that goes to FPGA sites #3 and #7 where it can be selected as L1_Qualifier #11. These FPGA sites make L1_Qualifiers 11:8. P5-10 This pin is used to receive the Hardware_Source_L1_Qualifier that goes to FPGA sites #4 and #8 where it can be selected as L1_Qualifier #15. These FPGA sites make L1_Qualifiers 15:12. P5(16:11) NOT Used