Original:	27-OCT-1998
						Revision:	27-OCT-1998



When implemented in a 4013L (e.g. for the AONM), the standard BSF FPGA
design does not meet the timing constraints.  Specifically, both the
DAV* Generator and the Timing Signal Selection components are unable
to meet the 50 MHz period constraint.  The following "fixes" have been tested:

	1) increase the constraint from 18.8 ns to 27.0 ns
	   the design still fails to meet the constraint

	2) remove the mux and hardwire the P1 TS to the HQ TS
	   this helps, but the design still doesn't meet the 27.0 ns constraint

	3) in addition to #2, remove some of the test fixtures
	   in particular, the DAV* generator will always generate 1 DAV*
	   (remove the forced low and 2 DAV* modes)
	   again the design fails to meet the 27.0 ns constraint
	   however, the number of paths failing is small and all of them
	   are on P1 TS to HQ TS which are not used in the AONM
	   (i.e. HQ TS 2 and 3)

	4) run a multipass place and route on the design from #3
	   this is still in progress but seems to promise at least
	   some improvement

In practice, the timing estimates provided by the software are always
very pessimistic so some timing tests with the hardware were
performed.  

There were two concerns: that the Tick Clock would slip 1 phase later
relative to the accelerator clock and that the DAV* generator would
slip sufficiently to provide either 0 or 2 DAV*.  Because the AONM
only uses the Tick Clock for readout, the first case is not a problem.
If in fact the Tick Clock slips 1 phase later, the only result is an
increase in the set up time before the data to be read out is
captured.  

The second case is more of an issue but was relatively easy to rule
out.  The position of the DAV* was checked by manually running the
AONM through a cycle of HSRO and capturing the timing signals on the
logic analyzer.  Both the data and the DAV* change slightly later
relative to the 50 MHz clock than in the TRM.  This is not surprising
since the 4013L is slower than the 4028XL, and the shift is not large
enough to be worrying.  To gain more of a feel for the performance
over a number of cycles, the standard HSRO test using an AONM in place
of the usual TRM was run.  Over several thousand loops, no errors were
found.  

For both of these tests, the standard BSF design with full
functionality was used.  Although this will probably not be used as
the production version of the BSF in the AONM, the fact that it does
work provides additional confidence that the reduced version (see #3
above) will be more than adequate despite failing to meet the timing
constraints.