BSF FPGA Programming ------------------------ Orig: 15-FEB-2000 Rev: 11-SEPT-2001 Basic default settings: Reg Data Comment --- ---- ------- 0 0x0000 No interrupts allowed by BSF 1 0x0000 LED is OFF 2 0x0000 Do not enable Timing Signal based Scaler Reset for any BSF Scalers 3 0x0000 Do not hold any BSF Scalers in Reset 4 0x0010 all P5_IO signals DISABLED P5_IO(15:0) are INPUTS to the BSF (and the card) P5_IO(16) is an OUTPUT from the BSF (and the card) 5 0x0000 BG_IO(15:0) are INPUTS to the BSF 6 0x0000 BG_IO(16) is an INPUT to the BSF 8 ****** Follow the pattern described in the BSF FPGA documentation: write 0x0242, write 0x0243, wait 5 ms, write 0x0247 16 0x2440 Timing Signal Map: P1(1) -> HQ(0) (Tick Clock) LOW -> HQ(1) LOW -> HQ(2) P1(15) -> HQ(3) (Scaler Reset) P1(10) -> Capture Monitor Data 32 0x0008 HSRO Header Word 0 LSByte TCC written event to event fixed data. The low byte of this register appears in the low byte of Header Word 0. 34 0x0000 HSRO Header Word 1 TCC written event to event fixed data. 35 0x0000 HSRO Trailer Word 0 TCC written event to event fixed data. 36 0x0000 Tick History Shift Register Control Register is set for zero latency (i.e. capture current tick data) These basic settings are modified for particular card types. Note that no distinction is made between cards which read out via HSRO vs. cards which do not read out via HSRO. ALL information presented below should be verified with what TRICS is actually currently setting up in the hardware at Initialize time. (1) AOIT TRM's Reg Data Comment --- ---- ------- 16 0x2121 Timing Signal Map P1(2) -> HQ(0) (TRM Clock) P1(11) -> HQ(1) (Maginot Line) P1(6) -> HQ(2) (Gap Marker) P1(15) -> HQ(3) (Scaler Reset) P1(10) -> Capture Monitor Data 32 0x00?? Header Word 0 LSByte 36 0x0001 BXHSR Depth same as TRM MSA FPGA (2) L1 Busy TRM's, Ind Disbl TRM's, Glob Dsbl TRM's (As setup by TRICS September 2001) Reg Data Comment --- ---- ------- 16 0x2120 Timing Signal Map P1(1) -> HQ(0) (Tick Clock) P1(11) -> HQ(1) (Maginot Line) P1(6) -> HQ(2) (Gap Marker) P1(15) -> HQ(3) (Scaler Reset) P1(10) -> Capture Monitor Data 32 0x00?? Header Word 0 LSByte 36 0x0002 BXHSR Depth same as TRM MSA FPGA (3) L1 AONM's and FOM's in L1 (but not FOM++ or L2 AONM's/FOM) Reg Data Comment --- ---- ------- 32 0x00?? Header Word 0 LSByte 36 ****** BXHSR Depth same as MSA FPGA BXHSR Depth on same cards (different 1st half FW vs. 2nd half FW) (4) FOM++ Reg Data Comment --- ---- ------- 16 0x2330 Timing Signal Map P1(1) -> HQ(0) (Tick Clock) P1(12) -> HQ(1) (Increment L3 Xfr Number) P1(14) -> HQ(2) (Send L2 Decision to SCL) P1(15) -> HQ(3) (Scaler Reset) P1(10) -> Capture Monitor Data 32 0x00?? Header Word 0 LSByte 36 0x0000 BXHSR Depth same as FOM++ MSA FPGA (5) TDM Reg Data Comment --- ---- ------- 4 0x1010 P5_IO(16) is enabled as an output P5_IO(15:0) are disabled and set as inputs 32 0x00?? Header Word 0 LSByte 36 0x0000 BXHSR Depth same as TDM MSA FPGA (6) L1 ST Fired to L2 TRM's Reg Data Comment --- ---- ------- 4 0x1110 P5_IO(16) is enabled as an output P5_IO(3:0) are enabled as inputs P5_IO(15:4) are disabled and set as inputs 16 0xa220 Timing Signal Map P1(1) -> HQ(0) (Tick Clock) P1(11) -> HQ(1) (L2 Maginot Line) P1(13) -> HQ(2) (Transfer STF Mask to L2 FW) P1(15) -> HQ(3) (Scaler Reset) P5(0) -> Capture Monitor Data (7) L2 Answer TRM's, L2 Auxi TRM's Reg Data Comment --- ---- ------- 4 0x1110 P5_IO(16) is enabled as an output P5_IO(16:0) are disabled and set as inputs P5_IO(16:4) are disabled and set as inputs 16 0x2220 Timing Signal Map P1(1) -> HQ(0) (Tick Clock) P1(11) -> HQ(1) (L2 Maginot Line) P1(13) -> HQ(2) (Transfer STF Mask to L2 FW) P1(15) -> HQ(3) (Scaler Reset) P1(10) -> Capture Monitor Data (8) TTS Reg Data Comment --- ---- ------- 16 0x2300 Timing Signal Map P1(1) -> HQ(0) (Tick Clock) P1(3) -> HQ(1) (Beginning of Turn) P1(14) -> HQ(2) (Send L2 Decision to SCL) P1(15) -> HQ(3) (Scaler Reset) P1(10) -> Capture Monitor Data 32 0x00?? Header Word 0 LSByte 36 0x0004 BXHSR Depth same as TTS MSA FPGA (9) PBS Reg Data Comment --- ---- ------- 16 0x2400 Timing Signal Map P1(1) -> HQ(0) (Tick Clock) P1(3) -> HQ(1) (Beginning of Turn) LOW -> HQ(2) P1(15) -> HQ(3) (Scaler Reset) P1(10) -> Capture Monitor Data (10) FM D_Latches in M122 Bottom Reg Data Comment --- ---- ------- 16 0x2430 Timing Signal Map P1(1) -> HQ(0) (Tick Clock) P1(12) -> HQ(1) (L3 Control Data Latch Enable) LOW -> HQ(2) P1(15) -> HQ(3) (Scaler Reset) P1(10) -> Capture Monitor Data (11) FM D_Latch in M123 Bottom Reg Data Comment --- ---- ------- 4 0x1110 P5_IO(16) is enabled as an output P5_IO(3:0) are enabled as inputs P5_IO(15:4) are disabled and set as inputs 16 0xa430 Timing Signal Map P1(1) -> HQ(0) (Tick Clock) P1(12) -> HQ(1) (L3 Control Data Latch Enable) LOW -> HQ(2) P1(15) -> HQ(3) (Scaler Reset) P5(0) -> Capture Monitor Data (12) L2 BAD no change from default (13) GS no change from default (14) L2 AONM's and L2 FOM's Reg Data Comment --- ---- ------- 16 0x2420 Timing Signal Map: P1(1) -> HQ(0) (Tick Clock) P1(11) -> HQ(1) (L2 Maginot Line) LOW -> HQ(2) P1(15) -> HQ(3) (Scaler Reset) P1(10) -> Capture Monitor Data