***************************** * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * * and * * * * Level 2 Trigger Framework * * * * Board Support Function * * * * FPGA Description * * * ***************************** Original: 7-MAY-1998 Latest: 18-NOV-1998 Introduction ------------ This document concentrates on the architecture and implementation of the Board Support Function (BSF) FPGA. Some version of the BSF FPGA will be used on all cards in the L1 Framework. The basic design of the BSF will be the same on all cards, but the BSF for some cards (e.g. the Trigger Decision Module) will in addition perform some special functions. The BSF FPGA has the following input and output connections: 1. On-Card Bus (EXCEPT for the High-Quality Timing Signals) 2. P1 Timing Signals 3. Board Global I/O Signals 4. P5 Global I/O Signals 5. High-Quality Timing Signals Like the Main Signal Array FPGAs, the BSF FPGA is accessible and configurable via VME, has a Chip_Status signal which it sends to the VME Interface FPGA, and appears on the JTAG scan chain. The BSF FPGA processes the 16 Timing Signals into the 16 High-Quality Timing Signals and the Capture HSRO Data and Capture Monitor Data signals. In addition, it performs the board-level management of the High-Speed Readout (HSRO) protocol. The BSF also does the processing associated with the 17 Board Global I/O Signals and the 17 P5 Global I/O Signals. On certain cards the BSF will perform more specialized functions as well. Operation--General Comments --------------------------- The BSF FPGA is composed of the following elements: 1. On-Card Bus Interface 2. Timing Signal Processing 3. High-Speed Readout Management, consisting of A. Command Receiver B. HSRO State Engine C. Readout Block 4. Board Global I/O Processing 5. P5 I/O Processing 6. Specialized Function Processing Each element is described below. 1. On-Card Bus Interface This is the standard On-Card Bus Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. The only caveat is that the High-Quality Timing Signal input pins are not driven since the High-Quality Timing Signals are produced by the BSF FPGA itself. 2. Timing Signal Processing On the P1 Backplane, 16 differential ECL timing signals (designated P1_TS(15:0)) are bussed to all slots. On each instance of THE Card, these signals are converted to single-ended TTL and routed to the BSF FPGA (additionally, the TTL version of P1_TS(0) is also routed to the VME Interface FPGA). The BSF FPGA processes these signals to produce 16 High Quality Timing Signals (designated HQ_TS(15:0)). These High Quality Timing Signals are divided into 4 groups of 4 signals each (e.g. HQ_TS(3:0), HQ_TS(7:4)). Each group of 4 High Quality Timing Signals is bussed to the 4 FPGAs in a single column of the Main Signal Processing Array (e.g. FPGAs #1-#4). The processing which takes place between the P1 Timing Signals and the High Quality Timing Signals is programmable via TCC, and is limited to: - selecting 1 of 4 P1 Timing Signals to drive each High Quality Timing Signal - forcing each HQ Timing Signal high or low via TCC Note that there are 4 separate sets of 4 HQ Timing Signals. The structure of the BSF requires that the 4 sets of HQ Timing Signals are identical, that is: - HQ_TS(0,4,8,12) are the same - HQ(TS(1,5,9,13) are the same, etc. Specifically, HQ_TS copy one of P1_TS (or are forced H/L) ----- ----- 0, 4, 8, 12 1, 2, 9, 10 1, 5, 9, 13 3, 4, 11, 12 2, 6, 10, 14 5, 6, 13, 14 3, 7, 11, 15 7, 0, 15, 8 The logic used to process the P1 Timing Signal fits into a single CLB. Additionally, the processing of P1_TS into HQ_TS is pipelined into two stages (using the 53 MHz Accelerator_Clock to run the pipeline), and the HQ_TS are latched in the IOB. This minimizes skew between the HQ Timing Signals distributed on the card, at the expense of introducing a fixed 36.6 ns delay between the P1 Timing Signals on the backplane and the HQ Timing Signals on the card. This fixed delay must be compensated for when programming the Carmen Master Clock. Note that the Carmen Master Clock allows the 53 MHz Accelerator Clock to be shifted with respect to the other clock signals. We will take advantage of this feature to compensate for skew between the P1 Timing Signals introduced in the cabling from Carmen, the TOM, and THE Card. 3. High-Speed Readout Management Many instances of THE Card use an optical readout path, designated High-Speed Readout. This involves 3 optical fibers: 2 incoming (for receiving command signals from the rest of the DAQ system) and 1 outgoing (for providing data to the rest of the DAQ system). A total of 4 TTL signals (Command Data, Command Data Valid, Command Clock, and Command Clock Valid) are routed from the incoming/low-speed optical fiber interface to the BSF FPGA. The High-Speed Readout Management receives these commands and performs the board-level management of the High-Speed Readout protocol. A larger number of TTL signals are routed from the BSF FPGA to the outgoing/high-speed optical fiber interface. These signals are: - Frame Clock - Flag - ED - DAV* - CAV* - LoopEn - FlagSel - M20Sel - Div(1:0) - Rst* - FF - Data(19:16) - Converter_Latch and their use is described in THE_CARD_HIGH_SPEED_READOUT.TXT. The High-Speed Readout Management includes A. Command Receiver B. HSRO State Engine C. Readout Block, consisting of 1. Data Source 2. High-Speed Readout (HSRO) Interface 3.A Command Receiver The Command Receiver receives the 4 TTL signals from the low-speed optical interface and parallelizes the bit stream. It then passes the commands to the HSRO State Engine. 3.B HSRO State Engine. Once an L1 accept has been generated, the L1 Framework generates a Capture High-Speed Readout signal which is passed along the backplane as a P1 Timing Signal. The HSRO State Engine receives the Capture High-Speed Readout signal via the P1 Timing Signal Processing. At some point the HSRO State Engine receives a Transport Data signal from the Command Receiver. If the Transport Data signal arrives before the Capture High-Speed Readout signal, it is delayed by the appropriate amount to allow the data to be captured. The Transport Data signal then initiates a daisy chain style readout of all 16 MSA FPGAs. The BSF FPGA manages the high-speed readout and can also provide its own data for readout before or after (or both) the 16 MSA FPGAs. The following signals are used to support this readout: - HSRO_Daisy_Chain_Enable_Out*: the BSF drives this signal low to indicate to the first chip in the daisy chain that it should now begin providing readout data on the HSRO_Data(15:0) pins and also driving the HSRO_Data_Valid* signal. This signal is daisy-chained through all FPGAs in the High Speed Readout chain - HSRO_Daisy_Chain_Enable_In*: the last chip in the HSRO chain drives this signal to the BSF FPGA to indicate that it has finished providing readout data. This is the end of the token daisy chain. - HSRO_Data_Valid*: FPGAs in the HSRO chain drive this signal low to indicate that they are currently providing valid data on the HSRO_Data(15:0) lines. The BSF FPGA synchronizes this signal with the 53 MHz master clock and drives it to the outgoing fiber optical cable interface as the DAV* signal. This signal is configured as an open-drain pull-chain type output on the MSA FPGAs, and is configured with a pull-up resistor on the BSF FPGA input. - HSRO_Data(19:16): MSA FPGAs drive HSRO_Data(15:0) as described above. The BSF FPGA drives HSRO_Data(15:0) in the same fashion, but additionally can provide 4 more data/flag/status/etc. bits to the rest of the DAQ system via the HSRO_Data(19:16) signals. Note that these signals do not pass through the BSF FPGA. In addition to overseeing the daisy chain readout, the HSRO State Engine monitors the signals to check for example that the Transport Data signal arrives after the Capture HSRO Data signal and that the next Capture HSRO Data signal is not received until the current readout cycle is completed. 3.C Readout Block The Readout Block has the following components: i. Data Source ii. HSRO Interface One Readout Block is required for each block of data to be read out. Thus, if the BSF FPGA is to provide data both before and after the MSA FPGA data, the BSF FPGA will need two Readout Blocks. 3.C.i Data Source The Data Source is similar to that found in the MSA FPGAs. The information to be read out is passed to a High-Speed Data Holding Register. This register is clocked by the BX Clock. The clock enable is controlled by the Capture High-Speed Readout signal. Note that the Capture High-Speed Data signal only enables the transfer of the data; the actual transfer occurs with the rising edge of the BX Clock. 3.C.ii HSRO Interface This is the standard High-Speed Readout Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. 5. P5 I/O Processing The P5 connector on THE Card carries 17 differential ECL "global I/O" signals, designated P5_IO(16:0). These signals pass through ECL/TTL transceivers and are routed to the BSF FPGA. These signals are arranged in 5 groups: 4 groups of 4 signals each (P5_IO(3:0), P5_IO(7:4), P5_IO(11:8), and P5_IO(15:12)), and a 5th "group" consisting only of P5_IO(16). This 5th "group" could be used either as a clock/strobe signal or a 17th data signal. The BSF FPGA selects the direction and controls the output enable separately for each group of these signals, via VME-accessible registers. Note that, although these signals are called "I/O" type signals, on-the-fly switching of signal direction is not supported, as the termination/pull-down resistors must be changed when switching between ECL input and ECL output functionality. 6. Specialized Function Processing For test purposes, the BSF also has facilities to o force DAV* low o provide consecutive DAV* signals and then stop o provide HSRO data from a register o provide HSRO data from a 16 bit counter Programming Interface --------------------- The Board Support Function FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W P5 Global I/O Dir/OE Control 8 R/W G-Link Control % 16 R/W Timing Signal Selection Control * 24 R Header: High-Speed Readout State * 25 R/W Header: High-Speed Readout Terminal Count * 26 R Header: High-Speed Readout Current Count * 27 R Trailer: High-Speed Readout State * 28 R/W Trailer: High-Speed Readout Terminal Count * 29 R Trailer: High-Speed Readout Current Count 32 R/W DAV* Selection 33 R/W DAV* Counter Control 34 R/W HSRO Data Selection 35 R/W HSRO Data Register 36 R/W DCE* Control % Not implemented in AONM BSF * Not presently implemented in any BSF The bit allocation in each of these registers is given below. Chip Control Status Register LSW: Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 3:15 --- unallocated The Chip Status Register MSW is currently unused. P5 Global I/O Direction and Enable Control: Bit Access Contents --- ------ -------- 0 R/W P5_IO(3:0) Direction Control ('1': these are OUTPUT signals, i.e. convertor runs TTL -> ECL '0': these are INPUT signals, i.e. convertor runs ECL -> TTL) 1 R/W P5_IO(7:4) Direction Control 2 R/W P5_IO(11:8) Direction Control 3 R/W P5_IO(15:12) Direction Control 4 R/W P5_IO(16) Direction Control 7:5 R/W Unused 8 R/W P5_IO(3:0) Output Enable ('1': Output (as specified by Direction) enabled '0': Both outputs disabled (TTL tri-stated, ECL INV and NINV both cut-off)) 9 R/W P5_IO(7:4) Output Enable 10 R/W P5_IO(11:8) Output Enable 11 R/W P5_IO(15:12) Output Enable 12 R/W P5_IO(16) Output Enable 15:13 R/W Unused G-Link Control Bit Access Contents --- ------ -------- 0 R/W RST* 1 R/W FF 2 R/W ED 3 R/W Flag 5:4 R/W Div(1:0) 6 R/W M20Sel 7 R/W FlagSel 8 R/W LoopEn 9 R/W CAV* 15:10 R/W Unused Timing Signal Selection Control Bit Access Contents --- ------ -------- 1:0 R/W HQ Set 0 P1 TS Selection ('0 0': select P1_TS 1 '0 1': select P1_TS 2 '1 0': select P1_TS 9 '1 1': select P1_TS 10 2 R/W HQ Set 0 Force Bit ('0': use the selected input timing signal '1': force the HQ Timing Signal high or low based on the the state of bit 1 above: bit 1 '0': force output LOW bit 1 '1': force output HIGH) 3 R/W Unallocated 5:4 R/W HQ Set 1 P1 TS Selection 6 R/W HQ Set 1 P1 Force Bit 7 R/W Unallocated 9:8 R/W HQ Set 2 P1 TS Selection 10 R/W HQ Set 2 P1 Force Bit 11 R/W Unallocated 13:12 R/W HQ Set 3 P1 TS Selection 14 R/W HQ Set 3 P1 Force Bit 15 R/W Unallocated DAV* Mode Selection Bit Access Contents --- ------ -------- 8:0 R/W DAV* counter terminal count () 9 R/W unallocated 10 R/W 1/2 DAV* mode select '0': 1 DAV* '1': 2 DAV* 11 R/W unallocated 12 R/W DAV* trigger '0': HSRO_Data_Valid* input '1': Internal (see bit 15) 13 R/W DAV* force low '1': DAV* output forced low 14 R/W DAV* counter mode '0': use DAV* counter '1': repeat DAV* endlessly 15 R/W DAV* Internal trigger '0': start DAV* counter via TCC write (see below) '1': start DAV* counter via Trans_HSD P1_TS DAV* Counter Control Bit Access Contents --- ------ -------- 0 R/W Start the DAV* counter must write 0 and then 1 15:1 R/W not allocated HSRO Data Selection Bit Access Contents --- ------ -------- 1:0 R/W Select the HSRO data output 00: real data 01: register data 10: counter data 2 R/W Enable the counter 3 R/W Enable the HSRO_Data output 15:4 R/W not allocated DCE* Control Bit Access Contents --- ------ -------- 0 R/W DCE* Disable 0: DCE* launched following Transport_HSRO P1_TS 1: DCE* forced HIGH (inactive) 15:1 R/W not allocated