Foundation Module Board Description --------------------------------------- Original Rev. 3-APR-1997 Most Recent Rev. 24-FEB-1999 This file is the description of the actual Foundation Module circuit board as it was designed and built in 1996. This is not a description of the Potalamaic Ideal THE_Card. The Potalamaic Ideal THE_Card is described in another file. Twenty of the Rev. A.2 Foundation Modules (FM) were designed and built in 1996. These cards have a 99.9% standard THE_Card perimeter layout but have only 4 FPGA's in their Main Signal Processing FPGA Array. Reasons for Designing and Building the FM Card: - verify mechanical design of THE Card and interaction with the backplane, connectors, etc. - verify design of the VME Slave Interface FPGA - provide a target card for system software development/testing - verify/test electrical layout and termination of THE Card - verify understanding of FPGA configuration methods (serial EPROM, parallel download from TCC) - test FPGA designs for THE Card - push Mentor Graphics PCB design software through all of its various stages - test Mentor Graphics auto-router capability - we can use this card as a digital I/O or whatnot card during Run II - provide the seed design from which all the derivative THE_Cards will come. Description of the FM Card: The FM Card includes all the following standard THE_Card components: (1) P1-P3 and P4-P5 connectors with all the standard routing and connections (2) VME Slave Interface (3) Timing Signal Receivers and Timing Signal distribution (4) P2/P3 MSA_In receivers, P4 MSA_Out drivers/pulldowns, and P5 Global I/O transceivers with terminator/pulldowns. (5) 4 Main Signal Processing Array FPGA's (6) examples of different routing and series terminating ideas for traces feeding MSA_In signals to the Main Signal Processing Array (7) High Speed Readout: Finisar output and Command Receiver (8) Board Support Functions FPGA (10) On Card Bus FM's Main Signal Processing Array: ---------------------------------- Chip Numbers Recall that the FPGA's in the Main Signal Processing Array are given "Chip Numbers". As viewed in the Mentor Standard orientation the Main Array FPGA's are assigned Chip Number in the following way: T.S. VME MSA_IN 0:63 MSA_IN 64:127 +-----------------+ +-----------------+ +-----------------+ +--| P1 |---| P2 |---| P3 |--+ | +-----------------+ +-----------------+ +-----------------+ | | +-----+ | | | # 0 | +-----+ +-----+ +-----+ +-----+ | | +-----+ | # 1 | | | | | | # 4 | | | VME +-----+ +-----+ +-----+ +-----+ | | | | +-----+ +-----+ +-----+ +-----+ +-----+ | | | # 17| | | | | | | | | | | +-----+ +-----+ +-----+ +-----+ +-----+ | | Brd Support Main Signal Processing Array | | Functions +-----+ +-----+ +-----+ +-----+ | | | | | | | | | | | | +-----+ +-----+ +-----+ +-----+ | | | | +-----+ +-----+ +-----+ +-----+ | | | # 13| | | | | | # 16| | | +-----+ +-----+ +-----+ +-----+ | | +----------+ +-----------------+ | +------------------| P5 |---------| P4 |---------+ +----------+ +-----------------+ MSA_OUT 0:63 Front of the FM Board The FM board has only Main Signal Processing Array Chip Numbers: 1, 4, 13 and 16. High Speed Read Out Order On the FM board the High Speed Readout order through the four chips in the Main Signal Processing Array is: first Chip #1, Chip #4, Chip #16, Chip #13 last. Note that the new current official THE_Card definition of the High Speed Readout order for the Main Signal Processing Array chips is straight Chip Number order, i.e. first Chip #1, ..., Chip #16 last. MSA_In MSA_Out Signals The mapping of MSA_IN and MSA_OUT signals to the four chips in the FM's Main Signal Processing Array is: Chip Reference Number Designator MSA_IN MSA_OUT ------ ---------- ------------------------ ---------------- 1 U52 MSA_IN 0:127 MSA_OUT 56:59 4 U53 MSA_IN 0:63 MSA_OUT 0:31 13 U54 MSA_IN 64:127 MSA_OUT 32:55 16 U55 MSA_IN 64:71 MSA_OUT 60:63 14 loads on MSA_IN_80 MSA_IN 88,89 MSA_IN 96:100 MSA_IN 104:107 14 loads on MSA_IN_108 14 loads on MSA_IN_109 14 loads on MSA_IN_110 14 loads on MSA_IN_111 Timing Signals The FM board receives the 16 P1 Backplane Timing Signals. All 16 of these backplane timing signals are delivered to the Board Support Functions FPGA. In addition Backplane Timing Signal #0 is delivered to the VME Interface FPGA and to the Finisar High Speed Readout module. The Board Support Functions FPGA can process the Backplane Timing Signals and then they are delivered to the Main Signal Processing Array FPGA's. Each horizontal row (Mentor orientation) of Main Signal Processing Array FPGA's is serviced by 4 High Quality Timing Signal lines that originate in the Board Support Functions FPGA. These lines are series terminated at the Board Support Functions FPGA. There are 4 sets of these 4 High Quality Timing Lines, one set for each row of Main Signal Processing Array FPGA's. Concern about Broken Traces and Resistor Arrays If THE-Card is miss-handled (handled roughly) there are 4 traces and 2 resistor arrays that are susceptible to breaking. The following specifics are true for both the Foundation Module and the other THE-Card derivatives. The 4 traces are located on the "solder side" of the board near the P4 MSA_Output connector. These traces pass under the heads of the screws that hold the P4 connector to the board. These traces are protected from the screw heads by fiber washers. If these fiber washers are not installed and these screws are tightened then any of these 4 traces could be broken. These 4 traces carry the Complement Side of the MSA_Output signals for: MSA_Output(35), MSA_Output(42), MSA_Output(58), MSA_Output(61), There are two resistor arrays in the lower right hand corner (Mentor orientation) of THE-Card that could be broken if THE-Card is excessively flexed by the front panel. These resistor networks are located very close to brackets that hold the front panel and the insertion extraction handles to the circuit board. The signals handled by these two resistor networks are the complement and direct side of the following MSA_Output signals: MSA_Out(58), MSA_Out(59), MSA_Out(60), MSA_Out(61), MSA_Out(62), MSA_Out(63), ECO History ----------- Foundation Modules used for Big Ben or P1-P5 copier functions must have the following ECO ("TS(0) BSF Bypass") 1. Cut top layer trace: U47 pin 12 to adjoining via (this is a very short trace) 2. Add 39-ohm series termination SMT resistor to U63 pin 11 (solder directly to IC lead) 3. Add WHITE wire: from above resistor to U47 pin 12 4. Add BLACK wire: GND via near U63 pin 11 to GND lead on C41 (GND lead is lead nearest U47--ignore silkscreen on card!) (this wire should be twisted with the above WHITE wire) Additionally, FM's used for Big Ben functions must have the following ECO's ("Local TS(0) Generation") 1. Remove R137. 2. Reinstall R137 in "tombstone" mode only on pad NEAREST FRONT of card. 3. Loosen P1 end of rear support bar. 4. Install crystal oscillator socket on an approximately 2" x 2" piece of perfboard (hot glue in place): +------------------------+ | | pins: 1: NC | 7 1 * | 7: GND | +------+ | 8: Out | | | | 14: VCC | | | | | +------+ | | 8 14 | | | +------------------------+ (front of card) 5. Install 0.1 uF capacitor between pins 7 and 14 on this perfboard (on solder side) 6. Install *short* heavy power wiring leads from pins 7 and 14 of this socket (on solder side of perfboard) to convenient GND and VCC pickup points (e.g. caps near U40) 7. Install *short* wire-wrap signal lead from pin 8 of this socket (on solder side of perfboard) to the "upended" terminal of R137. 8. Wedge perfboard between rear stiffener bar and P1 and retighten stiffener.