Description of the Foundation Module When Used as a 64 Bit D-Latch ---------------------------------------- Original Rev. 23-SEP-1999 Most Recent Rev. 24-FEB-2000 The goal is to use the FM card as a 64 bit wide D-Latch. That is 64 MSA_Input signals would be latched by latches in Main Array FPGA's and the output from these latches is the 64 bit wide MSA_Output from this FM card. To get access to 64 MSA signals (input and output) on an FM card requires using all 4 Main Array FPGA's on that card. Details about which FPGA would handle which MSA signals is presented below. The location of the MSA Signal Latches is at the input cell of the individual MSA Signals coming onto the FPGA. Latching at the input cell instead of the output cell will hold the skew on the various MSA Signal paths to a minimum. In our L2 FW application it is the skew of the signals coming into the latches that will be important. We have very little concern about the skew in the data coming out of the latches. The clock signal to cause the MSA Signal Latches to update is the normal combination of the FW Tick Clock and a clock enable signal. As usual, both of these are P1 TS which the Board Support FPGA routes to HQ TS, in this case HQ TS(0) and (1) respectively. The other main feature of this design is to be able to capture, for Monitor Readout the data that has been latched by the MSA Signal Latches. This allows us to see, via Monitor Readout, what MSA data has been captured in the MSA Signal Latches. The Capture Monitor Data clock, i.e. to update the Monitor Data Latches, arrives on P5 IO(0) and is routed to HQ TS(2) by the Board Support FPGA. This is necessary because the FM does not have a dedicated Capture Monitor wire from the Board Support as do the other cards. Block Diagram of the 64 Bit FM Latch Card ----------------------------------------- MSA Signal Latch at the Input Cell Output Cell +-----+ | | |\ MSA_Input >-------|D Q|-------------------------------| >----> MSA_Output | | | |/ | Clk | | +-----+ | | | Monitor Data | | Latch | | +-----+ P1 FW +-----+ | | | | |\ Tick >----| | | ----|D Q|------| >------> VME Readout Clk | |--- | | |/ of Monitor | AND | | Clk | | Data Clk >----| | +-----+ | Enable +-----+ | VME Read Capture | Monitor >-------- Data Use of MSA Signal ----------------- How to best setup the MSA_Inputs and MSA_Outputs on an FM card if you want to pass 64 signals into it and out of it. Consideration is given to the cable layout at the input and to not using MSA_In nets that have heavy loads on the FM board. For background information read the FM_Board_Description.txt document. With the following layout no heavily loaded MSA_In nets on the FM board are used. General Layout -------------- Best MSA_Inputs Number of FPGA to Ingested MSA_Outputs Signals Processe Site by this Site Driven by this Site by this Site ---- ---------------- ------------------- ---------------- 1 67:64 59:56 4 4 31:0 31:0 32 13 127:112 & 103:96 55:32 24 16 71:68 63:60 4 Input Cable vs MSA_In Layout ---------------------------- ----------------------------------------------|| Cable Arrives with Signals 15:0 || Plugs Into MSA_In 15:0 -.--------------------------------------------.| ----------------------------------------------|| Cable Arrives with Signals 31:16 || Plugs Into MSA_In 31:16 -.--------------------------------------------.| ----------------------------------------------|| Cable Arrives with Signals 47:32 || Plugs Into MSA_In 127:112 -.--------------------------------------------.| Signals 63:56 || /------|| Plugs Into MSA_In 71:64 / -----.| Connector Labeled 79:64 -------------------------------------/ / Cable Arrives with Signals 63:48 < -.-----------------------------------\ \ || \ -----|| Plugs Into MSA_In 103:96 \------.| Connector Labeled 111:96 Signals 55:48 The ".'s" try to imply the pin #1 end of a connector and the LSB in a bus of signals. Layout of the FM-Latch ---------------------- Input Serviced FPGA Serviced Output Signal by MSA_In Site by MSA_Out Signal +---------------------------------+ | FM-Latch Card | | --------------- | +-+ +-+ Input | | MSA_In ---> MSA_Out | | Output Signals | | 15:0 4 15:0 | | Signals 15:0 +-+ +-+ 15:0 | | +-+ +-+ Input | | MSA_In ---> MSA_Out | | Output Signals | | 31:16 4 31:16 | | Signals 31:16 +-+ +-+ 31:16 | | +-+ +-+ Input | | MSA_In ---> MSA_Out | | Output Signals | | 127:112 13 47:32 | | Signals 47:32 +-+ +-+ 47:32 | | | | Input +-+ | Signals | | MSA_In | 55:48 +-+ 103:96 ---> +-+ | 13 MSA_Out | | Output Input +-+ 63:48 | | Signals Signals | | MSA_In ---> +-+ 63:48 63:56 +-+ 71:64 16,1 | | | +---------------------------------+ Mapping of MSA_In to MSA_Out at the 4 FPGA Sites ------------------------------------------------ FPGA Site MSA_Inputs Maps to MSA_Outputs ---- -------------------------------------------- 1 MSA_In 67:64 maps to MSA_Out 59:56 4 MSA_In 31:0 maps to MSA_Out 31:0 13 MSA_In 127:112 maps to MSA_Out 47:32 MSA_In 103:96 maps to MSA_Out 55:48 16 MSA_In 71:68 maps to MSA_Out 63:60 Programming Interface --------------------- The FM Latch FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Enable Timing Signal Reset 3 R/W Force Scaler Reset 9:8 R Monitor Data The bit allocation in each of these registers is: Chip Control Status Register LSW (Register Address 0) Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 15:3 --- not allocated The Chip Status Register MSW and Scaler Reset Registers are currently unused. Monitor Data The contents of these registers is site dependent. FPGA Register Bit MSA Input MSA Output Comments ---- -------- --- --------- ---------- -------- 1 8 3:0 67:64 59:56 15:4 forced low 9 doesn't exist 4 8 15:0 15:0 15:0 9 31:16 31:16 31:16 13 8 15:0 127:112 47:32 9 7:0 103:96 55:48 15:8 forced low 16 8 3:0 71:68 63:60 15:4 forced low 9 doesn't exist