***************************** * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * * FM Electrical Tester * * * * FPGA Description * * * ***************************** Original: 28-AUG-1996 Latest: 21-OCT-1996 Introduction ------------ This file describes the Foundation Module "Electrical Tester" FPGA. It is used to test the following aspects of the Foundation Module: - downloading FPGA configuration via VME - VME access of registers within an FPGA - VME access of RAM within an FPGA - interrupt propagation from FPGA to VME interface to VME to TCC - input/output/timing signal quality and resistor values - ... Note that, although the original concept for the "electrical tester" FPGA involved only using this design in one of the 4 "corners" of the Foundation Module (and have similarly "specialized" FPGA's in the other 3 corners), for the initial tests of the Foundation Module it makes more sense to make a general "electrical tester" FPGA which can be used in all 4 corners of the FM. Implementation -------------- The FMET has the following features: 1. On-Card Bus/JTAG/High-Quality Timing Signal Interface This is a "component" from the MSU FPGA Common Block Library, which will receive its first functional testing in the FMET. Once the operation of this component is verified, it can be simply re-used for all other FPGA designs (except the VME Interface FPGA, which by necessity has a somewhat different version of this component) 2. Chip-Level Condition/Status Register This is a 32-bit register, spread across 2 Register Addresses, used to control and monitor the operation of the FPGA (e.g. it contains interrupt-enable and interrupt-request bits). This component is specific to this FPGA (not part of the Common Block Library), but similar functionality will be required on other FPGA's. 3. Scratch Registers There are multiple 16-bit "scratch" registers in this FPGA. These scratch registers use CLB's configured as D flip-flops as memory elements, and are distributed in address space in such a way as to stress the register-address decoding logic, allowing us to verify that the decoding logic does not produce glitches which cause unintended register writes. Recall that the decoders and flip-flop memory elements are relatively inefficient in their CLB usage, so we can only afford to have around 25 of these registers (using around 200 CLB's). 4. Scratch RAM This FPGA also has some "scratch" RAM. This RAM uses CLB's configured as RAM as memory elements. Again this memory is distributed in address space in such a way as to stress the register-address decoding logic. The register address decoding logic for RAM-style memory is different from that for register-style memory so it is important to carefully test both types. Also recall that the decoders and RAM memory elements are relatively efficient in their CLB usage, so we can have many more RAM-style memory locations (compared to register-style). 5. 128 input pins This FPGA is configured with 128 "Main Signal" inputs. They are assigned as in the And-Or Network Module FPGA. Note that FPGA's with fewer than 128 Main Signal inputs simply use a subset of the 128 Main Signal input pins assigned on the AONM FPGA. Also note that the Global I/O pins (on FPGA 13) are also assigned to a subset of these 128 pins, so the FMET FPGA can "automatically" receive input on the Global I/O pins when installed at Chip Address 13. These 128 input signals are latched on the rising edge of the lowest High-Quality Timing Signal servicing its column (e.g. HQ_TS(0)), using D-latches (by changing FPGA configuration we could also use transparent latches or no latches, which do we think is better?), and their states are readable via VME. 6. 4 output pins This FPGA is configured with 4 "Main Signal" outputs, again as on the And-Or Network Module FPGA. This FPGA can drive all 4 outputs from Chip Address 1 and 16, but has access to NONE of the outputs from Chip Address 4 and 13, due to the routing on the Foundation Module. These 4 output signals are controlled by a read/write register, which is accessible via VME. Other features which could be placed in this FPGA are: 1. High-Speed Readout Interface This would be extremely useful as a testbed for the High-Speed Readout Interface. Making a functional HSRO Interface requires both circuitry in this FPGA and circuitry in the Board Support Functions FPGA. The implementational details of this circuitry have not yet been finalized, but we should all review how this interface is intended to work, how it talks to the rest of the optical readout system, and what VME-based testing and control features we want/need for long-term support. 2. ... Programming Interface --------------------- The FMET has the following VME-visible registers: VME Byte Address Offset (in HEX, Reg from card base Register Addr Access address) Contents ---- ------ -------------- -------- 0 R/W $000 Chip Control Status Register (LSW) 1 R/W $002 Chip Control Status Register (MSW) 8 R $010 Main Signal Input 15:0 Readback 9 R $012 Main Signal Input 31:16 Readback 10 R $014 Main Signal Input 47:32 Readback 11 R $016 Main Signal Input 63:48 Readback 12 R $018 Main Signal Input 79:64 Readback 13 R $01a Main Signal Input 95:80 Readback 14 R $01c Main Signal Input 111:96 Readback 15 R $01e Main Signal Input 127:112 Readback 16 R/W $020 Main Signal Output 3:0 32-47 R/W $040 - $05f RAM Bank 1 48-63 R/W $060 - $07f RAM Bank 2 128-129 R/W $100 - $101 Scratch Registers 144-145 R/W $120 - $121 Scratch Registers 160-161 R/W $140 - $141 Scratch Registers 176-177 R/W $160 - $161 Scratch Registers 192-193 R/W $180 - $181 Scratch Registers 208-209 R/W $1a0 - $1a1 Scratch Registers 224-225 R/W $1c0 - $1c1 Scratch Registers 240-241 R/W $1e0 - $1e1 Scratch Registers 256 R/W $200 Scratch Register 272 R/W $220 Scratch Register 288 R/W $240 Scratch Register 304 R/W $260 Scratch Register 320 R/W $280 Scratch Register 336 R/W $2a0 Scratch Register 352 R/W $2c0 Scratch Register 368 R/W $2e0 Scratch Register 384 R/W $300 Scratch Register 416 R/W $340 Scratch Register 432-447 R/W $360 - $37f RAM Bank 3 448 R/W $380 Scratch Register 464-479 R/W $3a0 - $3bf RAM Bank 4 480 R/W $3c0 Scratch Register The bit allocation in most registers is straightforward. Within a single Main Signal Input or Output register, the least significant bit (e.g. Main Signal Input Bit 0 appears at D0 in register (8? 15?)). The bit allocation in the Chip Status Register is as follows: Chip Control Status Register LSW (Register Address 0) Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 3:15 unallocated The Chip Status Register MSW is currently unused. Implementation Notes -------------------- Recall that "normally" all registers (and RAM blocks) are connected internally to a single Read_Data bus via tri-state drivers. The Read_Data bus is made of horizontal long lines. In an XC4013 device, only 24 tri-state drivers (1/column) can be connected to a horizontal long line, imposing a limit on this type of connection of 24 16-bit registers, 24 16x16 RAM blocks, or any combination thereof. The FMET FPGA has 39 registers and 4 16x16 RAM blocks. To accomodate this large number of registers, the Read_Data bus is bifurcated: all elements with Register Address <=255 are on one half, with Register Addresses 256 to 511 on the other half. The 2 Read_Data busses are connected via a 16-bit wide, 2:1 mux. Note that the Read_Data bus for the lower half of the address space is still overloaded. This is solved by using a 16-bit wide, 8:1 mux to perform the Main Signal Input readback. Note that this 16-bit wide, 8:1 mux is quite wasteful of CLB resources, and this problem could be handled with another subdivision of the Read_Data bus, but this FPGA is a "testbed" of various ideas, and I considered it worthwhile to test this idea.