Card and FPGA Function by Address --------------------------------- Original: 10-MAY-1999 Revised: 7-SEP-2000 This file defines the layout of the Level 1 Trigger Framework, indicating which card (and FPGA on the card) handles each function. Rack M122 Top Crate: Luminosity Per-Bunch Scalers ------------------------------------------------- Vertical Master: 0 Vertical Slave: 0 Slot Card ---- ---- 1 TOM 2 PBS: Per-Bunch "Spare Item 4" Ticks 159:81 3 PBS: Per-Bunch "Spare Item 4" Ticks 80:1 4 PBS: Per-Bunch "Spare Item 3" Ticks 159:81 5 PBS: Per-Bunch "Spare Item 3" Ticks 80:1 6 PBS: Per-Bunch "Spare Item 2" Ticks 159:81 7 PBS: Per-Bunch "Spare Item 2" Ticks 80:1 8 PBS: Per-Bunch "Spare Item 1" Ticks 159:81 9 PBS: Per-Bunch "Spare Item 1" Ticks 80:1 10 PBS: Per-Bunch "Spare Item 0" Ticks 159:81 11 PBS: Per-Bunch "Spare Item 0" Ticks 80:1 12 PBS: Per-Bunch "Luminosity Item 4" Ticks 159:81 13 PBS: Per-Bunch "Luminosity Item 4" Ticks 80:1 14 PBS: Per-Bunch "Luminosity Item 3" Ticks 159:81 15 PBS: Per-Bunch "Luminosity Item 3" Ticks 80:1 16 PBS: Per-Bunch "Luminosity Item 2" Ticks 159:81 17 PBS: Per-Bunch "Luminosity Item 2" Ticks 80:1 18 PBS: Per-Bunch "Luminosity Item 1" Ticks 159:81 19 PBS: Per-Bunch "Luminosity Item 1" Ticks 80:1 20 PBS: Per-Bunch "Luminosity Item 0" Ticks 159:81 21 PBS: Per-Bunch "Luminosity Item 0" Ticks 80:1 For all of the above THE Cards, the FPGA usage is shown below: FPGA Design Note ---- ------ ---- 1 PBS Ticks 80*n + 5 : 80*n + 1 (n = 1:0) 2 PBS Ticks 80*n + 10 : 80*n + 6 3 PBS Ticks 80*n + 15 : 80*n + 11 4 PBS Ticks 80*n + 20 : 80*n + 16 5 PBS Ticks 80*n + 25 : 80*n + 21 6 PBS Ticks 80*n + 30 : 80*n + 26 7 PBS Ticks 80*n + 35 : 80*n + 31 8 PBS Ticks 80*n + 40 : 80*n + 36 9 PBS Ticks 80*n + 45 : 80*n + 41 10 PBS Ticks 80*n + 50 : 80*n + 46 11 PBS Ticks 80*n + 55 : 80*n + 51 12 PBS Ticks 80*n + 60 : 80*n + 56 13 PBS Ticks 80*n + 65 : 80*n + 61 14 PBS Ticks 80*n + 70 : 80*n + 66 15 PBS Ticks 80*n + 75 : 80*n + 71 16 PBS Ticks 80*n + 80 : 80*n + 76 * 17 BSF * Tick 160 does not exist, instead it is replaced with a checksum, which should equal the sum across all bunches. Rack M122 Middle Crate: Exposure Group Per-Bunch Scalers -------------------------------------------------------- Vertical Master: 0 Vertical Slave: 1 Slot Card ---- ---- 1 TOM 2 (open) 3 (open) 4 (open) 5 (open) 6 PBS: Per-Bunch "Exposure Group 7" Ticks 159:81 7 PBS: Per-Bunch "Exposure Group 7" Ticks 80:1 8 PBS: Per-Bunch "Exposure Group 6" Ticks 159:81 9 PBS: Per-Bunch "Exposure Group 6" Ticks 80:1 10 PBS: Per-Bunch "Exposure Group 5" Ticks 159:81 11 PBS: Per-Bunch "Exposure Group 5" Ticks 80:1 12 PBS: Per-Bunch "Exposure Group 4" Ticks 159:81 13 PBS: Per-Bunch "Exposure Group 4" Ticks 80:1 14 PBS: Per-Bunch "Exposure Group 3" Ticks 159:81 15 PBS: Per-Bunch "Exposure Group 3" Ticks 80:1 16 PBS: Per-Bunch "Exposure Group 2" Ticks 159:81 17 PBS: Per-Bunch "Exposure Group 2" Ticks 80:1 18 PBS: Per-Bunch "Exposure Group 1" Ticks 159:81 19 PBS: Per-Bunch "Exposure Group 1" Ticks 80:1 20 PBS: Per-Bunch "Exposure Group 0" Ticks 159:81 21 PBS: Per-Bunch "Exposure Group 0" Ticks 80:1 For all of the above THE Cards, the FPGA usage is as shown for Rack M122 Upper Crate. Rack M122 Bottom Crate: L2 Framework ------------------------------------ Vertical Master: 0 Vertical Slave: 2 Slot Card ---- ---- 1 TOM 2 TRM: Auxi L1 Data to L2 Framework 3 TRM: L2 Answers from L2 Global SpTrg 127:64 4 TRM: L2 Answers from L2 Global SpTrig 63:0 5 Pass-Through for L2 Answers from L2 Global 6 AONM: L2 Spec Trig Accept SpTrig 127:64 7 AONM: L2 Spec Trig Reject SpTrig 127:64 8 Pass-Through for L2 Spec Trig Accept/Reject 9 AONM: L2 Spec Trig Accept SpTrg 63:0 10 AONM: L2 Spec Trig Reject SpTrg 63:0 11 Pass-Through for L2 Spec Trig Accept/Reject 12 FOM: L2 Geo Sect Reject GeoSec 127:64 13 FOM: L2 Geo Sect Reject GeoSec 63:0 14 FM: D-Latch Data to L3 15 FM: D-Latch Data to L3 16 FOM: L2 Geo Sect Accept GeoSec 127:64 17 FOM: L2 Geo Sect Accept GeoSec 63:0 18 L2BAD: L2 Busy Answer Delay GeoSec 127:64 19 L2BAD: L2 Busy Answer Delay GeoSec 63:0 20 FM: L2 Framework Helper 21 FM: L1 Framework Helper, SCL Helper For the L2 Answer TRM's, the FPGA usage is as shown below: FPGA Design Note ---- ------ ---- 1 L2_TRM ST 64*n + 3 : 64*n + 0 (n = 1:0) 5 L2_TRM ST 64*n + 7 : 64*n + 4 9 L2_TRM ST 64*n + 11 : 64*n + 8 13 L2_TRM ST 64*n + 15 : 64*n + 12 2 L2_TRM ST 64*n + 19 : 64*n + 16 6 L2_TRM ST 64*n + 23 : 64*n + 20 10 L2_TRM ST 64*n + 27 : 64*n + 24 14 L2_TRM ST 64*n + 31 : 64*n + 28 3 L2_TRM ST 64*n + 35 : 64*n + 32 7 L2_TRM ST 64*n + 39 : 64*n + 36 11 L2_TRM ST 64*n + 43 : 64*n + 40 15 L2_TRM ST 64*n + 47 : 64*n + 44 4 L2_TRM ST 64*n + 51 : 64*n + 48 8 L2_TRM ST 64*n + 55 : 64*n + 52 12 L2_TRM ST 64*n + 59 : 64*n + 56 16 L2_TRM ST 64*n + 63 : 64*n + 60 17 BSF For the Auxiliary Data TRM, the FPGA usage is as shown below: FPGA Design Note ---- ------ ---- 1 L2_TRM L1 Capture Monitor Data (Channel 0) 5 L2_TRM unallocated 9 L2_TRM unallocated 9 L2_TRM unallocated 13 L2_TRM unallocated 2 L2_TRM unallocated 6 L2_TRM unallocated 10 L2_TRM unallocated 14 L2_TRM unallocated 3 L2_TRM unallocated 7 L2_TRM unallocated 11 L2_TRM unallocated 15 L2_TRM unallocated 4 L2_TRM unallocated 8 L2_TRM unallocated 12 L2_TRM unallocated 16 L2_TRM unallocated 17 BSF For the above FOM cards, the FPGA usage is as shown below: FPGA Design Note ---- ------ ---- 1 L2_FOML Geo Sect 64*n + 3 : 64*n + 0 (n = 1:0) 2 L2_FOML Geo Sect 64*n + 7 : 64*n + 4 3 L2_FOML Geo Sect 64*n + 11 : 64*n + 8 4 L2_FOML Geo Sect 64*n + 15 : 64*n + 12 5 L2_FOML Geo Sect 64*n + 19 : 64*n + 16 6 L2_FOML Geo Sect 64*n + 23 : 64*n + 20 7 L2_FOML Geo Sect 64*n + 27 : 64*n + 24 8 L2_FOML Geo Sect 64*n + 31 : 64*n + 28 9 L2_FOML Geo Sect 64*n + 35 : 64*n + 32 10 L2_FOML Geo Sect 64*n + 39 : 64*n + 36 11 L2_FOML Geo Sect 64*n + 43 : 64*n + 40 12 L2_FOML Geo Sect 64*n + 47 : 64*n + 44 13 L2_FOML Geo Sect 64*n + 51 : 64*n + 48 14 L2_FOML Geo Sect 64*n + 55 : 64*n + 52 15 L2_FOML Geo Sect 64*n + 59 : 64*n + 56 16 L2_FOML Geo Sect 64*n + 63 : 64*n + 60 17 BSF For the above AONM cards, the FPGA usage is as shown below: FPGA Design Note ---- ------ ---- 1 L2_AONM Spec Trg 64*n + 3 : 64*n + 0 (n = 1:0) 2 L2_AONM Spec Trg 64*n + 7 : 64*n + 4 3 L2_AONM Spec Trg 64*n + 11 : 64*n + 8 4 L2_AONM Spec Trg 64*n + 15 : 64*n + 12 5 L2_AONM Spec Trg 64*n + 19 : 64*n + 16 6 L2_AONM Spec Trg 64*n + 23 : 64*n + 20 7 L2_AONM Spec Trg 64*n + 27 : 64*n + 24 8 L2_AONM Spec Trg 64*n + 31 : 64*n + 28 9 L2_AONM Spec Trg 64*n + 35 : 64*n + 32 10 L2_AONM Spec Trg 64*n + 39 : 64*n + 36 11 L2_AONM Spec Trg 64*n + 43 : 64*n + 40 12 L2_AONM Spec Trg 64*n + 47 : 64*n + 44 13 L2_AONM Spec Trg 64*n + 51 : 64*n + 48 14 L2_AONM Spec Trg 64*n + 55 : 64*n + 52 15 L2_AONM Spec Trg 64*n + 59 : 64*n + 56 16 L2_AONM Spec Trg 64*n + 63 : 64*n + 60 17 BSF For the above L2BAD cards, the FPGA usage is as shown below: FPGA Design Note ---- ------ ---- 1 L2BAD Geo Sect 64*n + 3 : 64*n + 0 (n = 1:0) 2 L2BAD Geo Sect 64*n + 7 : 64*n + 4 3 L2BAD Geo Sect 64*n + 11 : 64*n + 8 4 L2BAD Geo Sect 64*n + 15 : 64*n + 12 5 L2BAD Geo Sect 64*n + 19 : 64*n + 16 6 L2BAD Geo Sect 64*n + 23 : 64*n + 20 7 L2BAD Geo Sect 64*n + 27 : 64*n + 24 8 L2BAD Geo Sect 64*n + 31 : 64*n + 28 9 L2BAD Geo Sect 64*n + 35 : 64*n + 32 10 L2BAD Geo Sect 64*n + 39 : 64*n + 36 11 L2BAD Geo Sect 64*n + 43 : 64*n + 40 12 L2BAD Geo Sect 64*n + 47 : 64*n + 44 13 L2BAD Geo Sect 64*n + 51 : 64*n + 48 14 L2BAD Geo Sect 64*n + 55 : 64*n + 52 15 L2BAD Geo Sect 64*n + 59 : 64*n + 56 16 L2BAD Geo Sect 64*n + 63 : 64*n + 60 17 BSF Note: on both cards, FPGA #1 additionally provides the "L2 BAD" output to the L2 Helper, on MSA_Out(0) For the Framework Helper card, the FPGA usage is as shown below FPGA Design Note ---- ------ ---- 1 (unused) 4 Helper (L1 FW) 13 SCL_Helper 16 (unused) 17 (unused) For the FM D_Latch card, the FPGA usage is as follows FPGA Design Note ---- ------ ---- 1 FM_Latch_4B1 Spec Trig 64*n + 59 : 64*n + 56 (n = 1:0) 4 FM_Latch_32B Spec Trig 64*n + 31 : 64*n + 0 13 FM_Latch_24B Spec Trig 64*n + 55 : 64*n + 32 16 FM_Latch_4B16 Spec Trig 64*n + 63 : 64*n + 60 17 BSF Rack M123 Top Crate: L1 And-Or and Exposure Group Input ------------------------------------------------------- Vertical Master: 1 Vertical Slave: 0 Slot Card ---- ---- 1 TOM 2 TRM: And-Or Input Terms AOIT 255:192 3 TRM: And-Or Input Terms AOIT 191:128 4 Pass-Through for And-Or Input Terms 191:128 5 AONM: Exposure Group 7:0 AOIT 255:128 6 AONM: Specific Trigger 127:64 AOIT 255:128 7 AONM: Specific Trigger 63:0 AOIT 255:128 8 Pass-Through for Upper Physics And-Or Fired 9 TRM: And-Or Input Terms AOIT 127:64 10 TRM: And-Or Input Terms AOIT 63:0 11 Pass-Through for And-Or Input Terms 191:128 12 AONM: Exposure Group 7:0 AOIT 127:0 13 AONM: Specific Trigger 127:64 AOIT 127:0 14 AONM: Specific Trigger 63:0 AOIT 127:0 15 Pass-Through for Lower Physics And-Or Fired 16 TRM: Geo Sect L1 Busy GeoSec 127:64 17 TRM: Geo Sect L1 Busy GeoSec 63:0 18 Pass-Through for Geo Sect L1 Busy 19 FOM: Exposure Group 7:0 L1 Disables 20 TRM: Global Disables 21 (open) For the TRM cards used above to receive And-Or Input Terms (slots 2, 3, 9, 10) the FPGA usage is as shown below: FPGA Design Note ---- ------ ---- 1 L1_TRM AOIT 64*n + 3 : 64*n + 0 (n = 3:0) 5 L1_TRM AOIT 64*n + 7 : 64*n + 4 9 L1_TRM AOIT 64*n + 11 : 64*n + 8 13 L1_TRM AOIT 64*n + 15 : 64*n + 12 2 L1_TRM AOIT 64*n + 19 : 64*n + 16 6 L1_TRM AOIT 64*n + 23 : 64*n + 20 10 L1_TRM AOIT 64*n + 27 : 64*n + 24 14 L1_TRM AOIT 64*n + 31 : 64*n + 28 3 L1_TRM AOIT 64*n + 35 : 64*n + 32 7 L1_TRM AOIT 64*n + 39 : 64*n + 36 11 L1_TRM AOIT 64*n + 43 : 64*n + 40 15 L1_TRM AOIT 64*n + 47 : 64*n + 44 4 L1_TRM AOIT 64*n + 51 : 64*n + 48 8 L1_TRM AOIT 64*n + 55 : 64*n + 52 12 L1_TRM AOIT 64*n + 59 : 64*n + 56 16 L1_TRM AOIT 64*n + 63 : 64*n + 60 17 BSF For the TRM cards used above to receive Geo Sect L1 Busy (slots 16, 17), the FPGA usage is as shown below: FPGA Design Note ---- ------ ---- 1 L1_TRM GeoSect 64*n + 3 : 64*n + 0 (n = 1:0) 5 L1_TRM GeoSect 64*n + 7 : 64*n + 4 9 L1_TRM GeoSect 64*n + 11 : 64*n + 8 13 L1_TRM GeoSect 64*n + 15 : 64*n + 12 2 L1_TRM GeoSect 64*n + 19 : 64*n + 16 6 L1_TRM GeoSect 64*n + 23 : 64*n + 20 10 L1_TRM GeoSect 64*n + 27 : 64*n + 24 14 L1_TRM GeoSect 64*n + 31 : 64*n + 28 3 L1_TRM GeoSect 64*n + 35 : 64*n + 32 7 L1_TRM GeoSect 64*n + 39 : 64*n + 36 11 L1_TRM GeoSect 64*n + 43 : 64*n + 40 15 L1_TRM GeoSect 64*n + 47 : 64*n + 44 4 L1_TRM GeoSect 64*n + 51 : 64*n + 48 8 L1_TRM GeoSect 64*n + 55 : 64*n + 52 12 L1_TRM GeoSect 64*n + 59 : 64*n + 56 16 L1_TRM GeoSect 64*n + 63 : 64*n + 60 17 BSF For the TRM card used above to receive Global Disables (slot 20), the FPGA usage is as shown below: FPGA Design Note ---- ------ ---- 1 L1_TRM Decorrelated Glb Dsbl 3:0 to TDM 5 L1_TRM Correlated Glb Dsbl 2:0 to TDM * 9 SHED Luminosity Index High-Speed Readout 13 (unused) 2 L1_TRM Decorrelated Glb Dsbl 3:0 to PBS 6 L1_TRM Decorrelated Glb Dsbl 2:0 to PBS * 10 (unused) 14 (unused) 3 (unused) 7 (unused) 11 (unused) 15 (unused) 4 (unused) 8 (unused) 12 (unused) 16 (unused) 17 BSF * Recall that Correlated Global Disable 3 is actually "Skip Next Tick" which is sourced by the FOM++, see below. The Correlated Global Disable 3 output from this FPGA is NOT USED. For the AONM cards used above to produce Physics Partial (Upper or Lower) And-Or Fired (slots 6, 7, 13, 14), the FPGA usage is as shown below: FPGA Design Note ---- ------ ---- 1 L1_AONM Spec Trg 64*n + 3 : 64*n + 0 (n = 1:0) 2 L1_AONM Spec Trg 64*n + 7 : 64*n + 4 3 L1_AONM Spec Trg 64*n + 11 : 64*n + 8 4 L1_AONM Spec Trg 64*n + 15 : 64*n + 12 5 L1_AONM Spec Trg 64*n + 19 : 64*n + 16 6 L1_AONM Spec Trg 64*n + 23 : 64*n + 20 7 L1_AONM Spec Trg 64*n + 27 : 64*n + 24 8 L1_AONM Spec Trg 64*n + 31 : 64*n + 28 9 L1_AONM Spec Trg 64*n + 35 : 64*n + 32 10 L1_AONM Spec Trg 64*n + 39 : 64*n + 36 11 L1_AONM Spec Trg 64*n + 43 : 64*n + 40 12 L1_AONM Spec Trg 64*n + 47 : 64*n + 44 13 L1_AONM Spec Trg 64*n + 51 : 64*n + 48 14 L1_AONM Spec Trg 64*n + 55 : 64*n + 52 15 L1_AONM Spec Trg 64*n + 59 : 64*n + 56 16 L1_AONM Spec Trg 64*n + 63 : 64*n + 60 17 BSF For the AONM cards used above to produce Exposure Group Partial (Upper or Lower) Enable (slots 5, 12), the FPGA usage is as shown below: FPGA Design Note ---- ------ ---- 1 L1_AONM EGPE 3:0 to TDM 2 L1_AONM EGPE 7:4 to TDM 3 (unused) 4 (unused) 5 L1_AONM EGPE 3:0 to PBS 6 L1_AONM EGPE 7:4 to PBS 7 (unused) 8 (unused) 9 (unused) 10 (unused) 11 (unused) 12 (unused) 13 Miguel AOIT 31:0 / 159:128 14 Miguel AOIT 63:32 / 191:160 15 Miguel AOIT 95:64 / 223:192 16 Miguel AOIT 127:96 / 255:224 17 BSF For the FOM card used to produce Exposure Group L1 Busy Disable (slot 19), the FPGA usage is as shown below: FPGA Design Note ---- ------ ---- 1 FOML Exp Group 3:0 L1 Busy to TDM 2 FOML Exp Group 7:4 L1 Busy to TDM 3 (unused) 4 (unused) 5 FOML Exp Group 3:0 L1 Busy to PBS 6 FOML Exp Group 7:4 L1 Busy to PBS 7 (unused) 8 (unused) 9 (unused) 10 (unused) 11 (unused) 12 (unused) 13 Miguel L1FEBZ 31:0 14 Miguel L1FEBZ 63:32 15 Miguel L1FEBZ 95:64 16 Miguel L1FEBZ 127:96 17 BSF Rack M123 Middle Crate: L1 Spec Trig Fired, Geo Sect L1 Accept -------------------------------------------------------------- Vertical Master: 1 Vertical Slave: 1 Slot Card ---- ---- 1 TOM 2 (open) 3 Pass-Through for Exp Grp Prt Enb, EG FEBz, Global Disable 4 TDM: L1 Specific Trigger Fired SpTrg 127:112 5 TDM: L1 Specific Trigger Fired SpTrg 111:96 6 TDM: L1 Specific Trigger Fired SpTrg 95:80 7 TDM: L1 Specific Trigger Fired SpTrg 79:64 8 TDM: L1 Specific Trigger Fired SpTrg 63:48 9 TDM: L1 Specific Trigger Fired SpTrg 47:32 10 TDM: L1 Specific Trigger Fired SpTrg 31:16 11 TDM: L1 Specific Trigger Fired SpTrg 15:0 12 Pass-Through for L1 Specific Trigger Fired 13 (open) 14 FOM: L1 Accept GeoSec 127:64 15 FOM: L1 Accept GeoSec 63:0 16 FOM++ 17 TRM: L1 ST Fired Mask FIFO to L2 FW SpTrg 127:64 18 TRM: L1 ST Fired Mask FIFO to L2 FW SpTrg 63:0 19 Pass-Through for L1 ST Fired Mask to L2 FW 20 Pass-Through for FOM++ outputs 21 Pass-Through for Geographic Section L1 Accepts For the TDM cards above, the FPGA usage is as follows: FPGA Design Note ---- ------ ---- 1 TDM ST 16*n + 0 (n = 7:0) 5 TDM ST 16*n + 1 (n = 7:0) 9 TDM ST 16*n + 2 (n = 7:0) 13 TDM ST 16*n + 3 (n = 7:0) 2 TDM ST 16*n + 4 (n = 7:0) 6 TDM ST 16*n + 5 (n = 7:0) 10 TDM ST 16*n + 6 (n = 7:0) 14 TDM ST 16*n + 7 (n = 7:0) 3 TDM ST 16*n + 8 (n = 7:0) 7 TDM ST 16*n + 9 (n = 7:0) 11 TDM ST 16*n + 10 (n = 7:0) 15 TDM ST 16*n + 11 (n = 7:0) 4 TDM ST 16*n + 12 (n = 7:0) 8 TDM ST 16*n + 13 (n = 7:0) 12 TDM ST 16*n + 14 (n = 7:0) 16 TDM ST 16*n + 15 (n = 7:0) 17 BSF For the FOM cards used above to produce L1 Accept (slots 14, 15), the FPGA usage is as in the L2 Framework (M122 Bottom). For the FOM++, the FPGA usage is as follows: FPGA Design Note ---- ------ ---- 1 FOMPPL L1 Qualifier Set 0 / L3 Xfr Number bits 3:0 2 FOMPPL L1 Qualifier Set 0 / L3 Xfr Number bits 7:4 3 FOMPPL L1 Qualifier Set 0 / L3 Xfr Number bits 11:8 4 FOMPPL L1 Qualifier Set 0 / L3 Xfr Number bits 15:12 5 FOMPPL L1 Qualifier Set 1 / L3 Xfr Number bits 3:0 6 FOMPPL L1 Qualifier Set 1 / L3 Xfr Number bits 7:4 7 FOMPPL L1 Qualifier Set 1 / L3 Xfr Number bits 11:8 8 FOMPPL L1 Qualifier Set 1 / L3 Xfr Number bits 15:12 9 FOMPPL Skip Next Tick (4 copies) (Ch. 0 -> CGSTD(3) to TDM's) (Ch. 1 -> CGSTD(3) to Exp Grp PBS's) (Ch. 2, 3 unused) 10 FOMPPL L1 Trigger Strobe (4 copies) (Ch. 0 -> SCL Hub End) (Ch. 1 -> L1 ST Fired Mask to L2 FIFO TRM's) (Ch. 2, 3 unused) 11 FOMPPL Skip Next "N" Ticks (4 different "N" values) (all channels go to an AOIT TRM) 12 FOMPPL Diagnostic Scaler Control (4 different outputs) (all channels go to ????) 13 Miguel ST Fired 31:0 14 Miguel ST Fired 63:32 15 Miguel ST Fired 95:64 16 Miguel ST Fired 127:96 17 BSF For the TRM cards used above to FIFO the L1 Specific Trigger Fired Mask to L2, the FPGA usage is as follows: FPGA Design Note ---- ------ ---- 1 L2_TRM Sp Trig 64*n + 3 : 64*n + 0 (n = 1:0) 5 L2_TRM Sp Trig 64*n + 7 : 64*n + 4 9 L2_TRM Sp Trig 64*n + 11 : 64*n + 8 13 L2_TRM Sp Trig 64*n + 15 : 64*n + 12 2 L2_TRM Sp Trig 64*n + 19 : 64*n + 16 6 L2_TRM Sp Trig 64*n + 23 : 64*n + 20 10 L2_TRM Sp Trig 64*n + 27 : 64*n + 24 14 L2_TRM Sp Trig 64*n + 31 : 64*n + 28 3 L2_TRM Sp Trig 64*n + 35 : 64*n + 32 7 L2_TRM Sp Trig 64*n + 39 : 64*n + 36 11 L2_TRM Sp Trig 64*n + 43 : 64*n + 40 15 L2_TRM Sp Trig 64*n + 47 : 64*n + 44 4 L2_TRM Sp Trig 64*n + 51 : 64*n + 48 8 L2_TRM Sp Trig 64*n + 55 : 64*n + 52 12 L2_TRM Sp Trig 64*n + 59 : 64*n + 56 16 L2_TRM Sp Trig 64*n + 63 : 64*n + 60 17 BSF Rack M123 Bottom Crate: Individual Disables, Gated Scalers ----------------------------------------------------------- Vertical Master: 1 Vertical Slave: 2 Slot Card ---- ---- 1 TOM 2 TRM for Individual Disable 1 SpTrg 127:64 3 TRM for Individual Disable 1 SpTrg 63:0 4 Pass-Through for Individual Disable 1 5 TRM for Individual Disable 0 SpTrg 127:64 6 TRM for Individual Disable 0 SpTrg 63:0 7 Pass-Through for Individual Disable 0 8 9 10 11 12 13 14 15 16 17 18 SM for Sequential L1 Accept # 19 SM for long version of L3 Transfer Number 20 FM D-Latch for data to L3 via control path 21 TTS for Tick and Turn Number For the TRM cards used above to receive Individual Disables (slots 2, 3, 5, 6), the FPGA usage is as shown below: FPGA Design Note ---- ------ ---- 1 L1_TRM ID m, Sp Trig 64*n + 3 : 64*n + 0 (n = 1:0) 5 L1_TRM ID m, Sp Trig 64*n + 7 : 64*n + 4 (m = 1:0) 9 L1_TRM ID m, Sp Trig 64*n + 11 : 64*n + 8 13 L1_TRM ID m, Sp Trig 64*n + 15 : 64*n + 12 2 L1_TRM ID m, Sp Trig 64*n + 19 : 64*n + 16 6 L1_TRM ID m, Sp Trig 64*n + 23 : 64*n + 20 10 L1_TRM ID m, Sp Trig 64*n + 27 : 64*n + 24 14 L1_TRM ID m, Sp Trig 64*n + 31 : 64*n + 28 3 L1_TRM ID m, Sp Trig 64*n + 35 : 64*n + 32 7 L1_TRM ID m, Sp Trig 64*n + 39 : 64*n + 36 11 L1_TRM ID m, Sp Trig 64*n + 43 : 64*n + 40 15 L1_TRM ID m, Sp Trig 64*n + 47 : 64*n + 44 4 L1_TRM ID m, Sp Trig 64*n + 51 : 64*n + 48 8 L1_TRM ID m, Sp Trig 64*n + 55 : 64*n + 52 12 L1_TRM ID m, Sp Trig 64*n + 59 : 64*n + 56 16 L1_TRM ID m, Sp Trig 64*n + 63 : 64*n + 60 17 BSF For the GS cards used above for general scaling, (slots 18, 19), the FPGA usage is as shown below: FPGA Design Note ---- ------ ---- 1 GS Items 96*n + 5 : 80*n + 0 (n = 3:0) 5 GS Items 96*n + 11 : 80*n + 6 9 GS Items 96*n + 17 : 80*n + 12 13 GS Items 96*n + 23 : 80*n + 18 2 GS Items 96*n + 29 : 80*n + 24 6 GS Items 96*n + 35 : 80*n + 30 10 GS Items 96*n + 41 : 80*n + 36 14 GS Items 96*n + 47 : 80*n + 42 3 GS Items 96*n + 53 : 80*n + 48 7 GS Items 96*n + 59 : 80*n + 54 11 GS Items 96*n + 65 : 80*n + 60 15 GS Items 96*n + 71 : 80*n + 66 4 GS Items 96*n + 77 : 80*n + 72 8 GS Items 96*n + 83 : 80*n + 78 12 GS Items 96*n + 89 : 80*n + 84 16 GS Items 96*n + 95 : 80*n + 90 17 BSF NOTE: Functions are yet to be assigned to channels here. For the TTS card used above to scale Tick and Turn type quantities (Slot 21), the FPGA usage is as shown below: FPGA Design Note ---- ------ ---- 1 TTS 2 TTS 3 TTS 4 TTS 5 TTS 6 TTS 7 TTS 8 TTS 9 TTS 10 TTS 11 TTS 12 TTS 13 TTS 14 TTS Never Reset Current BX Number 15 TTS Current BX Number (aka FE TZ BX Number) 16 TTS L1 Accept BX Number (aka FW TZ BX Number) 17 BSF For the FM D_Latch card, the FPGA usage is as follows FPGA Design Note ---- ------ ---- 1 FM_Latch_4B1 4 FM_Latch_32B 13 FM_Latch_24B L3 Transfer Number bits 15:0 16 FM_Latch_4B16 17 BSF