FPGA Companies and Products ----------------------------- Initial Version: 20-MAR-1995 Latest Version: 25-APR-1995 The purpose of this file is to collect together in one place what we have learned about the various FPGA products form the various manufactures. The first part of this file is about the Integrated Circuit products that the various companies produce. The IC products reviewed here are those that have potential use in the Run II Trigger Frameworks. Besides the current IC offerings we hope to understand the directions that the various companies are taking with their future products, e.g. 3 Volt logic, higher density, higher I/O count. The second section in this file is about the various software products that are available for FPGA design. These software products come from both the FPGA IC houses themselves and from independent FPGA software companies. The third section of this file compares AT&T to Xilinx. The fourth section of this file tries to describe some criteria that we should be using to make our FPGA selection. We should think about the silicon itself, how we can use the silicon, the software, and "expertise" issues. The fifth section of this file is a (currently unorganized) menu of questions that we need to have answered about all of the serious contenders. We need to talk to an application engineer type person who works for the FPGA vendor, not a sales person or anyone from a distributor. The sixth section of this file describes individual pieces of software which we can/should/need to purchase. The point of this file is to organize our understanding of the FPGA world so that we make a good selection of Si and software for our Run II work. FPGA Integrated Circuits ------------------------ ACTEL Date of information 1994 ----- ACTEL makes the ACT1, ACT2, and ACT3 series FPGA's. All are based on anitfuse technology. This implies they are not reprogrammable. The newest biggest parts are from the ACT3 series. The A14100A has 10,000 Gate Array Equivalent Gates, 250 TTL equivalent packages, 228 user I/O's. ALTERA Date of information May 1994 ------ The FLEX 8000 and the FLEX 10000 are the products from ALTERA that are of interest to us. All of the older ALTERA products are both too small and have the wrong architecture. The FLEX parts are SRAM based. The architecture is based on Logic Array Blocks (LABs) and routing interconnects. Each LAB contains 8 Logic Elements (LEs). Each LE has 4 data inputs, some clear-preset inputs, some clock inputs, a flip-flop, a carry chain, and an output selector. ALTERA does routing via continuous Rows and Columns that transverse the entire device. The 24 inputs to a LAB come from signals carried in a Row trace and each output from a LAB can drive up to two traces in a Column and/or one trace in a Row (this is with some restrictions due to Row - Column interconnects. There are some additional global signal distribution paths of clock signals and such and some local interconnects between LABs for Carry Chain and Cascade. The FLEX 8000 I/O is done from the ends of the Rows and Columns. JTAG scan path is available through the I/O cells. The biggest part from the FLEX 8000 series (EPF81500) has 16,000 usable gates, 1,500 flipflops, 162 LABs (I think), and 204 I/O's (I think), 304 pins. Does FLEX 10000 really exits and if so what is it? Does Altera make any 3 Volt parts? ATMEL Date of information May 1992 ----- ATMEL makes fancy EPLD's. The fanciest is about 60 I/O's with 128 flip-flops. all of this is "sum of terms" type PLD architecture. UV Erasable. ATMEL makes real gate arrays. The biggest is order of 100k gates and about 320 I/O's. All of their gate arrays can operate at 3.3 Volts. AT&T Date of information April 1995 ---- The following information is from the sketchy product brief that AT&T sent. We should be receiving a real data book from AT&T soon. The devices of interest from AT&T are called ORCA. They have part numbers like ATT2C40. AT&T also makes something called the ATT3000 series, which is a pin for pin substitute for Xilinx XC3000 series parts. The ORCA chips are reprogrammable SRAM-based parts. The architecture is composed of programmable logic cells (PLC's), programmable I/O cells (PIC's), and routing resources all arranged in an array structure. The current biggest part is ATT2C40 which is claimed to be 40K gates, 900 PLC's arranged in a 30x30 matrix, and up to 480 user I/O's (but currently only a 208 pin package is available). The PLC's are arranged in 4 identical quadrants. A PLC consists of a programmable function unit (PFU) and programmable routing resources. A PFU has a lookup section and a latch section. There are 19 inputs to and 6 outputs from a PFU. The lookup section has 4 16x1 LUT's with fast carry logic. A lookup section can act as a RAM (two 16x2 or one 16x4), adder, or combinatorial lookup of any 4, 5, or 6 input logic functions. The latch section has 4 latches. The latch and lookup can be used separately. An AT&T ORCA PFU is very similar to a Xilinx XC4000 CLB. One ORCA PFU looks like two XC4000 CLB's. ORCA PFU's can't provide the outputs from all 4 lookup tables and all 4 flip flops to the on-chip routing resources simultaneously. XC4000 CLB's do have enough outputs to provide 2 lookup table outputs and 2 flip flop outputs simultaneously. The routing resources are also similar to Xilinx. They use metal lines which are connected to PLC's and to each other via pass transistors. They seem to have more classes of routing resources than Xilinx, though. They concentrate on 4-bit (and some 5-bit) busses. For both horizontal and vertical lines, they have: - single-length (x1) busses are broken by pass transistors between every PLC. There are 2 horizontal and 2 vertical x1 busses (total of 16 signals) per PLC. - quad-length (x4) busses are broken by pass transistors between every fourth PLC. But it is not the case that all 4 bits of the bus are broken at the same location. Instead, the bus "flips" and one bit is broken by a pass transistor between each pair of PLC's: x4[3]-----. .-----2-----. .-----1-----. .-----0-----. .-----3-- X X X X x4[2]-----' \ .---1-----' \ .---0-----' \ .---3-----' \ .---2-- X X X X x4[1]-------' \ .-0-------' \ .-3-------' \ .-2-------' \ .-1-- X X X X x4[0]--PT-----' `-3--PT-----' `-2--PT-----' `-1--PT-----' `-0-- PLC0 PLC1 PLC2 PLC3 There are 2 horizontal and 2 vertical x4 busses (total of 16 signals) per PLC. - half-length (xH) busses are only broken by pass transistors in the middle of the array of PLC's. There is 1 horizontal and 1 vertical xH bus (total of 8 signals) per PLC. - full-length (xL) busses are not broken by pass transistors. There is 1 horizontal and 1 vertical xL bus (total of 8 signals) per PLC. The xL busses "flip" like the x4 busses (why?). - 2 horizontal and 2 vertical clock lines are provided per PLC. - interquad routing runs through the middle of the chip both horizontally and vertically. There are 20 horizontal and 20 vertical interquad signals. - for the the 2C40 only, there is the concept of subquad (4x4 array of PLC's). There is a class of inter-subquad routing to connect adjacent subquads both horizontally and vertically. Unlike Xilinx, the "routing resources per PLC" is constant (except for the interquad routing, which is not a function of the array size. That is, there are always 16 "single-length" lines per PLC. In Xilinx, the "wires to gates" ratio increases as the array size goes up, but it is not clear from their data book what the ratio is for any given array size. The PIC's are located around the perimeter of the chip and support JTAG boundary scan. No latching of inputs or outputs is available in a PIC. No hints about 3V. For software, AT&T uses NeoCAD's FPGA Foundry. AT&T has the source code to this software and will take over development/maintenance for the AT&T devices now that NeoCAD has been purchased by Xilinx. A concern is whether AT&T is really committed to supporting ORCA. It is not the majority of their business so they could lose it without a lot of damage to their company. Do they have the manpower and interest to really take over the software development? Motorola Date of information September 1994 -------- Mot offers the MPA1000 series of FPGA's. As far as we know Mot is new to the FPGA field and it is not clear if they are committed to it (although they have been in the gate array business for a long time). MPA1000 series uses SRAM structures to store the configuration and has programmable 3V/5V I/O although I believe that the internal logic runs from +5V. Note that Motorola used NeoCAD FPGA Foundry for their design software. We have not yet heard what Mot's plans are now that NeoCAD has been purchased by Xilinx. MPA1000 Layout +------+ 2x2 5x5 +------+ | Cell | -------> TILE -------> | | 5x5 2x2 Device | aka | | Zone | -------> Quadrant -------> Chip | Core | 10x10 | | 4x4 Package | Cell | ---------------------> | | 3x3 +------+ +------+ 2x2 So the biggest guy, the MPA1100, has 10000 Core Cells. Motorola calls this 22000 FPGA equivalent Gates. The MPA1100 also has 200 signal I/O connections. The Core Cell has a NAND primary function. A group of 2x2 Core Cells is called a Tile. In a Tile, one Core Cells has DFF?=/Latch as a seconday function, another has Wired-OR for a secondary function and two have NOR as secondary functions. Routing TEXAS Date of information April 1992 ----- Texas makes two series: TPC10 and TPC12. The largest is the TCP1280 which has "8000 Gate Array Equivalent Gates, 267 TTL Equivalent Packages, 1232 Logic Modules, 998 Flip-Flops, 750000 Antifuses, upto 140 user I/O, and a 160 to 176 pin package. AntiFuse --> one time programmable What does Texas currently offer? Until we learned about C40 I used to think that lots of Texas stuff was a some what strange. From C40 layout its clear that some Texas people can think clearly about what features it takes to get a job done. Maybe some of these people worked on newer Texas FPGA's. Texas has sold (spring 1995) their FPGA business to Actel. They had originally licensed the antifuse technology from Actel. XILINX Date of information June 1994 / April 1995 ------ The Xilinx parts that are of interest to use are the XC4000 series parts. All of the older FPGA parts (XC3000, XC2000) are too small. Xilinx also makes EPLD's (XC7000) which are not of interest. Xilinx also plans to release (or already has released by now) a new family, XC5000, which is based on XC4000 but with reduced functionality and reduced I/O count, i.e. XC5000 is not of interest to us. Note also that the XC4000 parts exist in XC4000, XC4000A, XC4000H lines. The A suffix indicates reduced I/O capacity, the H suffix indicates high I/O capacity. The XC4000 series is SRAM-based with "unlimited" programming cycles. The XC3000 parts are available in 3V (suffix L). The XC4000 parts are not yet available in 3V but Xilinx says that they recognize the demand for 3V XC4000 parts. The largest currently announced XC4000 part is the XC4025 which has 1024 CLB's arranged 32x32. But it is not shipping in quantity yet (7-APR-1995). This is claimed to be a 25000 gate product. Xilinx claims that they will release a part with 50000 gates (which would be something like 44x44 and presumably called XC4050) sometime during 1995. The architecture is based on Configurable Logic Blocks (CLB's), Input Output Blocks (IOB's), wide decoders located along the perimeter of the device, and routing interconnects. The CLB's are arranged in a square matrix with routing channels running horizontally and vertically between the CLB's. Each CLB has 13 inputs and 4 outputs. A CLB consists of 2 independent 4-input 1-output function generators, a 3-input 1-output function generator, 2 D flip-flops, and high-speed carry logic. A CLB can implement 2 arbitrary functions of 4 variables, or 1 arbitrary function of 5 variables, or some functions of up to 9 variables, or a 2-bit adder, or a 32-bit (32x1 or 16x2) RAM. The flip-flops can be used independently from the function generators. Each IOB contains an input latch and output latch, with independent clocks. The IOB's support JTAG boundary scan. Four wide "wired-AND" decoders (the width varies with the device size) are located along each edge of the chip (total of 16 decoders). These decoders may be "split" to give a total of up to 32 (narrower) decoders. There are 4 types of routing resources: single-length lines, double-length lines, longlines, and global distribution nets. All routing resources are metal with programmable switching points. The quantity of each resource is a function of device size. The features of each resource are: - single and double-length lines offer the most flexible routing but incur delay when passing through a switch element. Single-length lines hit a switch element between every CLB, double-length lines hit a switch element between alternating CLB's. There are both horizontal and vertical runs of each type. - longlines run horizontally or vertically across the entire chip. Some horizontal longlines can be driven by 3-state drivers to provide wire-and or bidirectional bus functionality. - global nets provide low-skew distribution of clock or other high- fanout control signals. There are 8 global nets (4 primary and 4 somewhat slower and more skewed secondary). Xilinx design software is called XACT and can interface directly to Mentor Graphics design entry (Design Architect) and simulation (QuickSim II) tools. For schematic-based design, XACT includes macro libraries. XACT also claims to allow various "text-based" entry methods such as state machine entry, Boolean equations, and high-level design languages, but it is not 100% clear whether 3rd party tools are required to really use any or all of these other methods. Design implementation is via the PPR (partition, place, and route) program, which can work automatically or with designer-specified "hints." I do not fully understand the XACT environment, the relationship to Mentor, the full details of which simulation levels are performed via Mentor and which (if any) simulation is performed in XACT, and what "back-annotation" information XACT can provide to guide the Mentor simulator QuickSim II. Xilinx also bought NeoCAD Inc., the formerly independent FPGA design software vendor. Both Xilinx and NeoCAD say (via telephone conversations) that Xilinx XACT and NeoCAD FPGA Foundry will both be shipping for the next year or so (i.e. current releases and immediately upcoming releases are not affected), but they are trying to produce a new "merged" software. The new software will look more like NeoCAD than XACT (according to both companies). The new software will be a free upgrade to NeoCAD users but will cost money for the XACT users (this is according to Xilinx). Both companies suggest that for our situation (want to start learning now for designs in 1996) we should buy NeoCAD FPGA Foundry which currently supports up to XC4013 (but will support XC4025 when the part is available), and upgrade to the new stuff when it is available, i.e. skip XACT altogether. Comparison between AT&T/Xilinx ------------------------------ OK, so ORCA looks like XC4000. The differences are at the detail level (not the fundamental level), but cannot be proven to be unimportant. Perhaps the most interesting thing to note is that ORCA is shipping 40K gate density while Xilinx is only shipping 13K gate density parts (sampling 25K gate parts). I believe that 1 ORCA gate = 1 XC4000 gate, so AT&T is shipping parts that are 3x fancier than Xilinx (but they cost $800 each right now). What can we learn from this? Possibilities: - Xilinx can't design the big parts. This seems very unlikely. - Xilinx can't manufacture the big parts. This is almost impossible to believe. - Xilinx can't sell the big parts. This would be surprising but it seems to be the reasonable conclusion. Are we in a non-existent market segment? Indications from Xilinx technical people are that the decision to release XC4025 is related to "business factors," but that they expect to fully release this part and continue to increase gate density. What about speed? Combinatorial delays within a CLB/PFU are pretty similar (order of 4 ns). Input delays for an IOB/PIC are about 3 ns each, and output delays for each are of the order of 6 ns. But the comparisons for routing delays are harder to make. We can note that both chips have similar methods (metal lines, pass transistors, similar routing architectures). But the only data book comparison that can be made is for the "global/clock" nets. For the biggest ORCA, 5.8 ns is quoted as delay. For the 13K gate Xilinx guy, this is quoted as 7.5 ns. So the 13K gate Xilinx part has 30% more clock delay than the 40K gate ORCA part. It is clear that this delay only increases as the array gets bigger. How do the other routing resources compare? What about commitment to market? Clearly Xilinx has the advantage here. They can't give up FPGA's. It's all they sell (OK, they have some plain gate arrays, too, but they are based on the FPGA's), and they sell more of them than anyone. AT&T could bail out tomorrow. What about software tools? AT&T was purely NeoCAD, now they have to support themselves for future releases. FPGA Design Software -------------------- No matter which FPGA vendor we pick, we need to have some software which converts an FPGA "design" (which may be entered via the program itself or may be imported from e.g. Mentor Graphics, and may be schematics or some text-based specification e.g. VHDL/state machine description/Boolean equations) into an FPGA configuration. Typically some simulation facilities (either internal or in conjunction with some other design software like Mentor Graphics) are provided. This software may be thought of like "PALASM" in the sense that it converts a design to a device configuration but should be a lot more powerful. All vendors (except Motorola and AT&T) sell their own flavor of FPGA design software. The vendor-specific design software only supports the devices of a particular vendor. Buying vendor-specific software then locks us into the devices of that vendor. In the final state, we will almost certainly want to be locked into one vendor, allowing us to leverage our experience across all designs. But how early do we really want to make that commitment? Choosing early gives us maximum time to learn the software and architecture, but choosing late lets us explore the phase space more fully. The FPGA design software is actually made up of 2 parts: synthesis and place/route. Synthesis software takes synthesizable VHDL as input and produces some kind of netlist (EDIF, XNF) as output. The netlist does not include FPGA placement/routing information and may not even be fully decomposed into FPGA-specific elements. Examples of this software are AutoLogic (from Mentor, we have this software) and Synopsys FPGA Compiler (which we don't have but appears to be popular). AutoLogic can accept VHDL, Mentor Graphics schematic, or any combination of the two as input. It can also accept various "equation" style inputs such as PLA or KISS. It requires libraries for the target FPGA, but the libraries are free from Mentor (and will be included on the May 1995 CDROM). Note that there are both Xilinx libraries and NeoCAD libraries. Both Mentor and NeoCAD recommend using the Xilinx libraries rather than the NeoCAD libraries. It produces EDDM (MG internal data format) or EDIF output. The Xilinx-to-Mentor interface software includes an EDDM-to-XNF translator so we can produce XNF output as well. This output would go to the place and route software (i.e. NeoCAD). Synopsys is another synthesis vendor. It is not vendor specific but requires libraries from the target vendor (i.e. we buy the libraries from Xilinx). Synopsys can use VHDL as input. It produces EDIF and XNF output. Synopsys appears to be popular and is probably pretty good, but it is probably not that much better than AutoLogic. So let's plan to use AutoLogic until we prove that AutoLogic is not going to work. NeoCAD sells FPGA place and route software. They used to be non-vendor- specific but have been purchased by Xilinx. Both NeoCAD and the old Xilinx XACT software are still available, but within 9 months to 1 year they will be merged into one tool. NeoCAD receives the output from the synthesis software (i.e. a netlist in EDIF, XNF, or some other format) and produces a placed and routed FPGA design. NeoCAD requires libraries which they sell. NeoCAD cannot use EDDM (the MG internal data format) but we can use the Xilinx EDDM<->XNF translators, or the Mentor EDDM<->EDIF translators to communicate. NeoCAD and Xilinx recommend using XNF rather than EDDM. NeoCAD can provide timing information to QuickSim. NeoCAD also allows placement "hints," manual placement, and/or manual routing if desired. Here is how the "standard" design flow is envisioned: .TXT Create specification in English. | | | Enter design. Schematic/VHDL via Mentor | Design Architect/System 1076. What about | state machine or other equation-style V format? It is not necessary (but may be Design Entry desirable) to consider FPGA architecture | at this stage (need Xilinx libraries to | do so in schematics). Output is Mentor | EDDM data. NeoCAD does nothing here. | +-----+--+ | | | | | |(logic information) | | | | | V | | Simulation Logic only, or logic and timing. Mentor | | ^ ^ QuickSim II (or QuickSim FPGA). NeoCAD | | | | does not include a simulator but can | | | | provide back annotation to QuickSim. | | | | | | | | | | | | | V | | Convert VHDL/equation/high level | Synthesis | | schematic to elements related to | | | | | FPGA architecture. This is NOT | | | | | FPGA place and route. Mentor AutoLogic | | +--+ | (or AutoLogic FPGA) is one such tool. Input | | | can be VHDL, Mentor schematic (EDDM), or | | | some other "equation" type formats (KISS, | | | PLA, EQU). Need libraries from Mentor. | | | Output is EDIF, XNF, or EDDM (which can | | | be converted to EDIF or XNF with a | | | Xilinx translator which comes with | | | the Xilinx libraries for Des Arch. | | | Synopsys is another synthesis vendor, | | | which uses EDIF for in and out. Synopsys | | | needs libraries from Xilinx. | | | Hints | | | | | | | Implement design in a given FPGA. NeoCAD | V V | is tool to do this. Input formats: EDIF, +-->FPGA Place/Route | XNF (Xilinx Netlist File), several others. | | | Buy needed libraries from NeoCAD. | | | Can also graphically see/edit placement/ | +-----+ routing. Can use "hints" for placement | (timing and routing. Can specify timing constraints | info) which must be met. Can return back anno | upstream. What needs to be done upstream | in order to make place/route doable? | V FPGA configuration Or, just listing software that we plan to use: +>> QuickSim II/Quicksim FPGA <<+<<<<<<<<<<+ ^ ^ ^ ^ ^ ^ EVE >>> Design Architect >>+>> AutoLogic/AutoLogic FPGA >>>+>> NeoCAD +> FPGA + System-1076 V + AutoLogic libs (from ^ + libs + Xilinx libs V Mentor) ^ (DS-344) V ^ +>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>+ Software we already have: EVE Design Architect System-1076 QuickSim II AutoLogic Mentor software that is in V8.4 but not in the subset of V8.2_5 that we have loaded: QuickSim FPGA AutoLogic FPGA QuickVHDL (all part of Top-Down FPGA Station which is new in V8.4) AutoLogic libraries for Xilinx AutoLogic libraries for NeoCAD Software that we don't have: NeoCAD + libraries for Xilinx Xilinx interface for Mentor Graphics Synopsys Things that may drive our choice of FPGA ---------------------------------------- "Capability" of the Si. Need to predict the Si which will be available in 1996. Consider "capability" in general (i.e not directed to specific designs), which is admittedly mushy. Some points to consider: - number of gates - number of I/O's - reprogrammability - internal architecture - routing Ability to use the "capability" of the Si for specific designs. This is a hard topic--we don't have any detailed specific designs. Points to consider: - does the architecture (logic elements and routing capability) work with our designs? Or is the architecture something which is supposed to be ignored (e.g. Mot). What about the "geometry" (i.e. layout of logic elements)? - do we need to given placement/routing "hints" in order to make our designs fly? if so does the architecture lend itself to hinting? does the software allow this easily? Software issues - compatibility with our system (Sun, Solaris 2.4, Mentor V8.2_5) - design entry methods - simulation--integrated with Mentor? Multiple "levels" of simulation (logic only, logic with timing from fully placed/routed design). - ease of use - vendor-specific vs. generic Ability to become experts with the Si and software - vendor provides help (app. engineers, printed materials, maybe intensive short classes) - one chip for every design Questions that we need to ask to the finalists' application engineers --------------------------------------------------------------------- Hardware: What improvements does your company expect to make in its products over the next 2 years? i.e. # of gates, # of I/O's, routing, speed. 3V? What is typical power consumption of your biggest part at "normal" speed? What software do you have libraries/interfaces/etc. for? Is it possible/easy to take advantage of the architecture of your FPGA during early stages of design entry? Do we need to use a particular design entry method in order to do this? Software: Describe the typical design entry, simulation, implementation flow of your software? Assume schematic capture and VHDL as input mode, via Mentor Graphics. Which parts are done in Mentor and which in your software? Does your design entry software interface with Mentor Graphics? Specifically for design capture and also timing information back to QuickSim. What types of design entry (i.e. schematic, state machine, VHDL) does your software support (Sun/Mentor version)? Are additional 3rd party tools required for any of these methods? What libraries/additional software/etc. are required and where do I get them? What silicon do you support, what don't you support, and what is your typical delay? Can I specify or give hints about placement? What about routing? Do I need to specify routing if I specify placement? How is all of this done? When is it necessary/desirable to specify placement? Graphical or text? Reproducible? Does your software run on our machine? Sun SS20 w/Solaris 2.4, 64MB RAM, 2 screens. What documentation is included? What documentation should be purchased separately? Does your company offer "test drives" of the design software? (not technical) University program? (not technical) Both: Does your company offer any intensive short courses in the use of its products for new users? For users who want to extract maximum performance (both speed and density) from its products? Do you have any printed materials which would help (collections of app. notes, tutorial books, etc.)? Software details ---------------- All software must run on a Sun SPARCstation 20 under Solaris 2.4. CDROM should be the first choice for distribution media, 4mm DAT only if CDROM is not available. No other distribution media should be considered under normal circumstances. (1) NeoCAD NeoCAD FPGA Foundry and Timing Wizard for Xilinx devices with Mentor Graphics CAE integration kit. This includes 1 year of maintenance, and on-line docs. Need to verify with Chris Kiel of Comtel about printed docs and how to order. He is out of town until 1-May. part number: non-university price: university price: (2) Xilinx Xilinx Interface to Mentor Graphics part number: DS-344-SN2-C non-university price: $2725 (Marshall--Anthony Wetzel) university price: $1000 This includes Mentor Graphics libraries (for Design Architect and QuickSim, but NOT AutoLogic), and translators to/from Mentor Graphics data formats (e.g. EDDM). This includes 1 year of maintenance/updates, and both printed and on-line documentation. Additional years of maintenance are currently $464. No University price break is available. This does NOT include the XACT core tools or any hardware (i.e. FPGA demo board). The "full" package including XACT costs $3150 under Xilinx University program. To purchase, need only to send a P.O. to Marshall. This is verified w/ Marshall but not Xilinx. Have a call in to Xilinx about this question. Xilinx Interface to Synopsys part number: DS-401-SN2-C Only need this software if we choose Synopsys for synthesis tool. Currently we are not planning to use Synopsys. Xilinx FPGA demo board part number: HW-FPGABOARD non-university price: $285 (Marshall--Anthony Wetzel) university price: $175 OK so this isn't software. (3) Mentor Graphics AutoLogic Libraries for Xilinx AutoLogic Libraries for NeoCAD Both of these libraries will be provided on the upcoming (May) Mentor CD. They can also be downloaded via anonymous FTP from supportnet.mentorg.com. They are required in order to use AutoLogic to synthesize to Xilinx FPGA's. The NeoCAD Libraries are "optimized" for NeoCAD, but Mentor claims that they are not as robust as the Xilinx libraries, and that NeoCAD can also operate with the Xilinx libraries. We will need to understand this a bit better, but the whole question will eventually go away when Xilinx and NeoCAD become fully integrated.