Original: 12-Sep-2000 Current: 14-Dec-2000 Here is the latest snapshot of FPGA versions. Most designs have only a single interesting version (typically the most recent) listed. Some others have multiple versions listed. With the BSF, for example, each version is targeted to a different card type. With the L1_AONM and TDM, we have the version we are using now and the version we would like to be using once related technical issues are solved. This list consists of 40 unique FPGA designs. They break down as follows: L1 Framework: 12 (fom++l, gs, helper, l1_aonm, l1_foml, l1_trm, miguel, pbs, scl_helper, shed, tdm, tts) L2 Framework: 9 (fm_latch_24b, fm_latch_32b, fm_latch_4b, l1al2, l2_aonm, l2_foml, l2_helper, l2_trm, l2bad) Multiple Use: 2 (vme, bsf) Connectivity Testing: 8 (aonmct, bsfct, fm13ct, fm1ct, fm4ct, smct, tdmct, trmct) MSU Testrack Support: 3 (bigben, p1p5bsf, source) L1 Cal Trig: 4 (bougie, chtcr_regions, ctro, erpb) L2 Alpha: 2 (tsi_production, tsi_prototype) L1 and L2 FW FPGA Designs ------------------------- Design Version Note ------ ------- ---- aonmct 3_4 4036XLA AONM Rev. B 3_3 4013L FM 3_2 4013XL 2 AONM Rev. A 3_1 4013L other AONM Rev. A bigben 20_3 bougie 1_2 not tested bsf 27_1 4028XL TDM, TRM, SM 23_x 4013XL 27_2 4036XLA (note: ver 24 further tunes the state engine ver 25 fixes the token passing back into the BSF ver 26 modifies the monitor copy of trailer word 1 ver 27 adds pullup on HSRO Data Valid input) bsfct 1_7 4036XLA AONM Rev. B 1_6 4013XL 2 AONM Rev. A 1_5 4028XL TDM, TRM, SM 1_2 4013L FM 1_1 4013L other AONM Rev. A chtcr_regions 5_1 not tested ctro 1_1 not tested erpb 15_1 not tested fm13ct 3_2 4013L FM fm1ct 4_1 4013L FM fm4ct 2_1 4013L FM fm_latch_24b 2_1 4013L FM fm_latch_32b 2_1 4013L FM fm_latch_4b 1_2_2 4013L FM site 1 16_2_1 4013L FM site 16 (note: on Sun, these versions are 2_2 and 2_1 respectively. On PC, renamed to include site identifier) fom++l 3_1 4036XLA AONM Rev. B (note: currently using 2_1, 3_1 adds L3 Xfer Num to HSRO 3_1 is in the fom++l_uber directory before any changes were made to 2_1, that uber directory was copied to fom++l_orig_uber in the obsolete dir; within that directory, the design is still called fom++l) (note: on PC, directory/files named fomppl not fom++l as on Sun) gs 7_1 4028XL SM (note: ver 6 could not be reset or loaded except when the Scaler Channel Gate was asserted - ver 7 corrects this but the Xilinx software wouldn't open the design so ver 7 is in gs_uber and the original gs_uber dir has been moved to gs_orig_uber in the obsolete dir; the design is still called gs within this directory) helper 9_1 4013L FM l1_aonm 32_3 4036XLA ** no PTERMs ** 1_1 4036XLA ** w/ PTERMs ** (note: on Sun, 32_3 is based on $FPGA_DESIGNS/OBSOLETE/aonm_old) (note: currently running 32_3 everywhere) l1_foml 1_2 4036XLA AONM Rev. B l1_trm 3_1 4028XL TRM (note: currently running 1_1, 3_1 adds the FIFO Status word to HSRO 3_1 is in the l1_trm__uber directory before any changes were made to 1_1, that uber directory was copied to l1_trm_orig_uber in the obsolete dir; within that directory the design is still called l1_trm) l1al2 3_2 l2_aonm 2_1 4036XLA AONM Rev. B l2_foml 2_1 4036XLA AONM Rev. B l2_helper 15_2 4013L FM l2_trm 5_1 4028XL TRM l2bad 3_1 4036XLA AONM Rev. B miguel 5_1 4036XLA AONM Rev. B p1p5bsf 7_1 4013L FM pbs 11_1 4028XL SM scl_helper 4_1 4013L FM shed 1_1 4028XL TRM smct 1_1 4028XL SM source 1_1 4013L FM site 4 tdm 22_1 old prescaler 24_1 new prescaler (note: currently running 24_1) tdmct 2_2 4028XL TRM trmct 1_1 4028XL TRM tsi_production 3_2 tsi_prototype 13_2 tts 12_1 4028XL SM (note: currently running 12_1, 12_1 rearranges the word order for HSRO vs 11_1 12_1 is in the tts_uber directory before any changes were made to 11_1, that uber directory was copied to tts_orig_uber in the obsolete dir; within that directory the design is still called tts) vme 4_1 4013L (1) 4_6 4013L (2) 4_12 4013L (3) 4_5 4013XL (4) (notes: (1) original version with a pinout error, still used on some cards. 17256L with horizontal line under part number. (2) good for "L to XL" designs (TRM, TDM, SM). 17256L with X etched in upper right corner. (3) good for AONM Rev. A. 17256L with X etched in lower right corner. (4) good for AONM Rev. B and 2 AONM Rev. A's with 4013XL VME FPGA. 1701L with X etched in upper right corner.)