How to get #1, #2, #3, and #4 done in Two Years -------------------------------------------------- Rev. 13-OCT-1995 A. Use fancy new complex IC's and dense circuit boards to keep down the number of new circuit boards that need to be developed. 1. For each circuit board that needs to be developed you pay y=mx+b The "b" can be big, e.g. project setup on CAD, PO's for manufacture and assembly, documentation. 2. Simple non-dense circuit boards are not a guarantee of no problems. Look at the number of problems that we have had with cards like TLM and xxMBD vs how few problems we have had with cards like CHTCR and CTFE. B. Use fancy new complex IC's because: 1. Because there will be a couple of years between the start of the design work and the time when the new frameworks are ready for use and because the new frameworks will need to last for a number of years, use fancy new complex IC's in this design or else we will end up owning and taking care of some out dated piece of junk. 2. Use fancy new complex IC's in the design of the new Frameworks to keep the project interesting and educational for those who are doing the detailed design work. 3. History of the electronics industry says that what's fancy and complex and new today is standard and common within one or two years. 4. History of our Run I equipment is that it tends to have too many old obsolete parts designed into it from the start. C. Use standard mechanical packaging. D. Partition the design so that pieces may be broken off and worked on independently. 1. For example break off the board (box) that does the serial links sending commands to the front-ends and receiving error flags from the front-ends. Break off the card(s) to buffer and readout the framework data with each event, e.g. SARC, SAR. Break off the "Scalers" and other self contained functions. 2. Concentrate on getting the interfaces to these broken off pieces well defined and documented. E. Concentrate on the upper level parts of the design e.g. schematic capture and FPGA programming. Farm out the low level parts like PCB layout. This work could go to an engineering firm or too a Fermi engineer or perhaps even Dan Owen. F. Finish completely the overall descriptive design before starting the detailed engineering on any one of the pieces. In the Run I equipment the above rule was not followed and we were just lucky that all of the parts fit together in the end. 1. First completely finish the overall descriptive design documentation including the partitioning of the design. Several aspects need to be investigated, as several points of view need to be considered. - Functionality and services offered (Triggering, Programming, Readout...) - Constraints (timing, construction schedule, space, Special Control abilities...) - Physical Interfaces - Architecture - Monitoring/accountability (quantities scaled, Luminosity, Live Time, TRGMON access) - Testability (Verifier, Exercizer, Debugger) - Control (TCC, timing and synchronization source) _ Error detection and recovery, flow control, throttling, stopping, reset/init 2. Then write the "txt" files for ALL the pieces before starting the detailed engineering on any one of them. This should include a "txt" file for: - each "logical" card (functionality, programming) - each "physical" instance of THE card - each interface and for each special aspect: - cabling feasibility studies - rack layout plan, - timing studies, - power/cooling studies, - COOR programming definition - TRGMON displays definition - TCC hardware - TCC physical placement/connection - TCC/host software partitioning - Data Block format - Spy service - Readout Control (VTC) 3. write "txt" files for subcomponents, when/if applicable: - Each FPGA design - Special cabling harnesses, patch pannels,... - Special software (e.g. JTAG from TCC, exercizer) G. Build the new Frameworks first and then worry about the L1 Cal Trig buffering - readout problem. H. Do the design work carefully enough that we do not need prototypes of any of the parts. 1. Figure out carefully enough what we are going to do before we start building so that we do not need to make prototypes. 2. For the most part we did not need prototypes for the Run I equipment so lets try to get away without them in Run II. 3. It takes too long to build prototypes and D-Zero upgrade does not have the Atlas time scale where it makes sense to play around with prototypes. I. Use programmable logic everywhere that it makes sense 1. Try to stick to one vendor of programmable logic. This saves CAD software cost, learning curve time, number of schemes for loading configuration into logic. 2. Do we need to use the same vendor as Fermi or some other lab likes to use? 3. Size parts to have LOTS of spare room. J. Paint the parts different colors. K. Reliability of the new equipment. What reliability problems have we had with the Run 1 equipment that we can address with better designs in the Run II equipment. L. Make use of all common auxiliary equipment like rack power control and voltage monitoring and safety equipment. M. How can we do a better, more realistic, job of making schedules. N. Monitor everything practical with scalers so that people do not come back later and ask for something that we have not monitored. O. Design the system so that all data needed by TrgMon is always accessible to TrgMon even when something is broken and events are not flowing so that TrgMon can tell you why events are not flowing. P. Design the system so that all data needed by TrgMon is inherently contemporary data. There should be no need for TrgMon to keep two clock for Run II equipment. Q. Make certain that everyone understands that we are dumping the job of garbage collection. R. Try do design cards that are re-usable so that they can be used in other applications in the D-Zero experiment or in other experiments. S. How to use people so that they are interested, involved, contributing, and learning new stuff: 1. Steve, Not just a CAD - Electronics Engineer person but this time officially - fully involved in all the overall design steps and decisions. 2. Dan Owen, ???? Need to ask him what he wants to do, how he thinks he can contribute most. 3. Physics Guidance Person, need help with: Luminosity monitoring per Spec Trig Acq Deadtime monitoring Live beam crossings per Spec Trig L2 monitoring Number of Spec Trig's Are Spec Trig's of the And-Or type vs the And-Or-Or type 64 Spec Trig's of the And-Or type vs 32 Spec Trig's of the And-Or-Or How does CDF work Scaler per And-Or Input Term? Do you really need to read scalers with every event? or just some scalers with every event? 4. Mike Matulik, Serial link to the front ends 5. Guidance with selecting future computer platform for the TCC. Are TCC's separated for download-control vs TrgMon. Can John Featherly help us understand the world to be. What is the new platform and software support environment for Level 3. T. How to decide how many of each type of circuit board to build? Recall that we suffered in the Run 1 equipment because we did not build a sufficient number of some early types of cards. Recall also that it is a big price to pay to make a second production run of any card. Cards are needed for a number of different reasons: Running system at Fermi, MSU Test Rack, Spares at Fermi (and at MSU for development work). 1. The total number of cards available of any type should be 2x what the running system at Fermi requires. This is protection against catastrophic failure. 2. In addition to the running system at Fermi and the MSU Test rack we need at least 3 of any kind of card.