Level 1 Calorimeter Trigger Readout Helper This is for CT_Readout_Helper _10_1 and _9_1 from 24-JULY-2002 ------------------------------------------------------------------ Original: 7-AUG-2001 Latest: 1-AUG-2002 Introduction ------------ This document describes the architecture and implementation of the Level 1 Calorimeter Trigger Read Helper Function FPGA. This design provides the sequence of timing signals that are needed by the L1 CT Readout each time there is a Level 1 Accept. This FPGA design may gain additional functions as the L1 CT Readout developes. The Level 1 Calorimeter Trigger Read Helper Function is located at FPGA Site #4 on an FM Card. This FM card is currently in slot #21 of the middle crate in M101. The design of the CT_Read_Helper will use many of the same blocks that were developed for the L1 FW Helper FPGA. The CT_Read_Helper FPGA has the following input connections: BX Helper Clock CMC_TL_7 (i.e. 132 nsec clock) MSA_In_51 Spare Marker CMC_TL_6 MSA_In_53 Sync Gap Marker CMC_TL_5 MSA_In_55 Cosmic Gap Marker CMC_TL_4 MSA_In_57 53 MHz (Disabled) CMC_P_Clk MSA_In_49 L1 Accept (for this Geo Section) MSA_In_0 L1 Period (this SCL Frame contains an L1_Acpt) MSA_In_1 ERPB_Input_Clock (from Master Clock Sequencer #2 TL 20) MSA_In_21 ERPB_EM/Tot_Sel (from Master Clock Sequencer #2 TL 21) MSA_In_19 The first 5 signals in this list all come from: Carmen Master Clock via Selector Fanout #8 "Helper B" to the M101 Middle J5 of the Rear_PB at the P2 connection of Slot #21. Only the first signal (BX_Helper_Clk) from this group of 5 signals is currently used. The L1_Accept for this Geo Section and the L1_Period signals arrive from the L1 Trigger Framework via single signal Diff-ECL cables. These two signals are latched by IFD's that are clocked by BX_Helper_Clk right as they enter the FPGA. In _9_1 the positive edge of BX_Clk is used to clock these IFD's and in _10_1 the negative edge of BX_Clk is used. ERPB_Input_Clock and ERPB_EM/Tot_Sel are generated by the L1 Cal Trigger Sequencer in the Carmen Master Clock. Note that ERPB_EM/Tot_Sel MSA_In_19 is pin 57 which is a secondary global clock net. Note that BX_Helper_Clock MSA_In_51 is pin 239 which is a secondary global clock net. The CT_Read_Helper FPGA has the following output connections: Capture HSRO Data Transport HSRO Readout Data Capture Monitor Data Capture Monitor Data Armed Scaler Reset TCC Manual Control Lines (8) (used for ERPB Readback control and FPGA Configuration control) ERPB Capture Data DC Transport Data ERPB Input Clock ERPB EM/Tot Select Monitor of the BX_Helper_Clock Monitor of the "AND" of the raw GS_L1_Accept and GS_L1_Period These inputs and outputs are defined in the User Constraint File for this FPGA (including which MSA In/Out is used, where appropriate). The Geographic Section L1_Acpt signal and the L1_Period signal will need to be brought out of the Trig FW as a differential ECL signals and delivered to the FM_Card that holds this CT_Readout_Helper FPGA. As with the other systems that are readout with VRB's, the readout of the Level 1 Calorimeter Trigger will require 2 Geographic Sections: one for the VRB and a second one for the source of the data that the VRB reads out. This second Geographic Section is called a non-readout G.S. by COOR because Level 3 does not receive and data from this G.S. This CT_Read_Helper receives the L1_Acpt from this 2nd Geographic Section and then generates the sequence of timing signals that result in sending data into the VRB. The strong intent is to make this sequence of timing signals include all the signals that are involved in readout of the L1 Trig FW data Block and to place these signals on the same P1 Timing Signal pins as are used in the Trig FW. The ideas is to be able to plug a Run II FW card into the L1 Cal Trig readout crate (M101 Middle) and to be able to read it out. For example to be able to put a TRM with SHED FPGA's into this crate and read it out. Description of the Blocks within the CT_Read_Helper --------------------------------------------------- 1. On-Card Bus Interface This is the standard On-Card Bus Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. 2. The generation of the various output signals falls into a couple of categories. The generation of most of these signals is initiated by the L1_Acpt signal. The ERPB_Input_Clock and the ERPB_EM/Tot_Sel just pass through the CT_Read_Helper. Their output is just via buffers, i.e. there is no latch controling the "re-timing" of these signals. The CT_Read_Helper fpga has access to these signals for use in generating some of its other outputs. ERPB_EM/Tot_Sel is received on a Global Buffer and is used to time the output of the ERPB Capture Data signal. DC Transmit Trigger The start of this signal is delayed from the L1_Acpt by a programmable number of BX_Clock ticks. This signal is 8 BX_Clk ticks wide, i.e. about 1 usec wide. ERPB Capture Data The generation of this signal is initiated by the L1_Acpt signal. L1_Acpt and L1_Period are sampled by IFD's at the input to this FPGA using either the positive edge of BX_Clk (ver _9_1) or the negative edge of BX_Clk (ver _10_1). Then one positive edge of BX_Clk is needed to get the "AND" of these signals through the timing generation stage of this signal. Finally ERPB_Capture is asserted starting on a positive edge of EM/Tot_Select and remains asserted for 2 full periods of the EM/Tot_Select signal. So ERPB Capture Data only changes state at a point in time when the FIFO address in the ERPB has already changing. There is a control bit that lets you enable or disable the generation of the ERPB Capture Data siganl. The state of the Scaler Reset and the TCC Manual Control lines is programmed via register, and these outputs uptade on the positive BX_Clock edges. 4 of the TCC Manual Control lines are used to control how far back the read cycle is in the ERPB FIFO, i.e. the LookBack value. Capture HSRO Data Transport HSRO Readout Data Capture Monitor Data all have a number of programmable features. In general they are 1 period of the BX_Clock wide, they update on positive BX_Clock edges and they begin a programmable number of BX_Clock ticks after each L1_Acpt. Capture HSRO Data and Transport HSRO Data both work the same way. They requires the L1 Accept signal to this Geographic Section AND the L1 Period to both be active at the same time when they are clocked into this module by the Helper_Clk. These two signals should each be active for 1 Tick and the Transport HSRO Data should follow Capture HSRO Data by ?? Ticks. Capture HSRO Data itself should be ?? Ticks after the L1_Acpt. Capture Monitor Data must be initiated by TCC. It then can be generated immediately or generated upon the receipt of an L1 Accept. It should be active for 1 Tick. Like Capture HSRO Data, Capture Monitor Data will be a programmable number of ticks after the L1 Accept. Capture Monitor Data Armed indicates that on the next L1_Acpt a Capture Monitor Data signal will be issued. Programming Interface --------------------- The CT_Read_Helper Function FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) * 1 R/W Chip Control Status Register (MSW) 8 R/W Trans HSRO Data P1_TS(8) 9 R/W Capture HSRO Data P1_TS(9) 10 R/W Capture Monitor Data P1_TS(10) 11 R/W ERPB_Capture_Data 12 R/W DC_Transmit_Trigger 14 R/W TCC Manual Control Lines 15 R/W Scaler Reset P1_TS(15) The bit allocation in each of these registers is given below. Chip Control Status Register LSW Reg Adrs 0 Typical Readback Value $ffe8 Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 3 --- not allocated 4 R/W Helper Mode ('0': Normal Mode '1': Test Mode) 15:5 --- not allocated Transport HSRO Data P1_TS(8) Control Reg Adrs 8 Typical Readback Value $0003 Capture HSRO Data P1_TS(9) Control Reg Adrs 9 Typical Readback Value $0001 Capture Monitor Data P1_TS(10) Control Reg Adrs 10 Typical Readback Value $0000 ERPB Capture Control Reg Adrs 11 Typical Readback Value $0001 Bit 0 assert this bit to enable generation of the ERPB Capture Data signal Bits 7:1 are not used - they read back with what ever you have programmed into them. Bits 15:8 are not use always read back as zero. DC Transmit Control Reg Adrs 12 Typical Readback Value $000e Bit Access Contents --- ------ -------- 3:0 R/W Delay to Pulse The output TS will be asserted for a single tick, once this channel's timing chain has been "launched" (either via TCC or via an external request). The value in this register defines the delay between the "launch" stimulus and the assertion of the TS. For example, a value of "1" indicates that the output TS will go high on the 2nd Helper Clock rising edge following the stimulus, and return low on the 3rd Helper Clock rising edge following the stimulus. 4 R/W Immediate Pulse Request (Launch TS Now) (Write 0 to clear, write 1 to request. Output TS will pulse after the delay specified above.) 5 R/W Single-Cycle Arm (Launch TS on next external start, only meaningful in Single-Cycle Mode) (write 0 to clear, write 1 to arm. If TCC takes this bit low prior to the "next" external start stimulus, that stimulus will still result in the channel being launched. TCC must examine bit 9 to know whether a Single-Cycle request is currently pending) 6 R/W unallocated 7 R/W Require TCC Arming (i.e. Single-Cycle Mode) (0: Channel cycles on every external "start" 1: Channel cycles only for the first "start" after TCC has Armed the channel (via bit 5) 8 R Pending Immediate Request (0: No Immediate Request pending 1: Immediate Request pending) 9 R Pending Single-Cycle Request (0: No Single-Cycle Request pending 1: Single-Cycle Request pending, i.e. the Single-Cycle Mode was armed but there has been no external "start" stimulus.) Note: bits 8 and 9 are both cleared after the output TS has pulsed, for whatever reason (i.e. the Pending Single-Cycle request is cleared even if the TS pulses due to an Immediate Request, and vice-versa). 15:10 R/W unallocated TCC Manual Control Lines Register Address 14 Typical Readback Value $0079 Bits 7:0 are TCC Manual Control 7:0 On the TCC Manual DC-ERPB Control Signal Becomes Which Is Used For ---------------- ------- ------------------- Manual_Control_0 mtg-2 Lookback(0) Manual_Control_1 mtg-3 Lookback(1) Manual_Control_2 mtg-4 Lookback(2) Manual_Control_3 mtg-6 Lookback(3) Manual_Control_4 mtg-7 DC Config Control Manual_Control_5 mtg-8 Lookback(4) & DC Config Ctrl Manual_Control_6 mtg-9 DC Config Control Manual_Control_7 mtg-y no connection Bits 15:8 are not used read back as written Bits 5,3:0 These 5 Manual Control Lines connect to 5 of the "MTG" lines that run to the DC card and then to the ERPB cards. These 5 bits control the 5 bit Lookback value in the ERPB cards. For now a good value to load in here is $19 = 25 --> a look back of 7. Note that the Manual_Control_5 is also used by the DC card Configuration Control Logic. Bits 6:4 These 3 Manual Control Lines connect to 3 of the "MTG" lines that run to the DC card. These 3 bits control the Configuration Logic on the DC card. A certain combination of these bits will cause the DC to re-configure all the FPGA's on all the ERPB cards. Note that the Manual_Control_5 is also used by the ERPB card. The required sequence to cause LCA Configuration is described in the dc_board_description.txt file. Bit 7 This bit is tied to MTG_Y line that runs to the DC card. It is not used for anything at this time. MTG_Y is received on the DC card but it is not connected to any thing. Scaler Reset P1_TS(15) Control (Normal Mode) Reg Adrs 15 Typical Readback Value $0000 Bit Access Description --- ------ ----------- 0 R/W Reset Scalers ('0': clear P1_TS(15) '1': assert P1_TS(15)) 15:1 R/W unallocated I/O Function to MSA_ In-Out Mapping of the CT_Read_Helper ------------------------------------------------------------- BX_Clock = Helper_Clk MSA Input 51 (Glb Clk) L1_Accept MSA Input 0 L1_Period MSA Input 1 ERPB_Input_Clock (Master Clock Seq #2 TL 20) MSA_In_21 ERPB_EM/Tot_Sel (Master Clock Seq #2 TL 21) MSA_In_19 (Glb Clk) Trans_HSRO_Data MSA Output 0 Capture_HSRO_Data MSA Output 1 Capture_Monitor_Data MSA Output 2 Scaler_Reset MSA Output 3 ERPB_Capture_Data MSA Output 4 DC_Transmit MSA Output 5 Trans_HSRO_Data MSA Output 6 Capture_HSRO_Data MSA Output 7 Capture_Monitor_Data MSA Output 8 Scaler_Reset MSA Output 9 ERPB_Capture_Data MSA Output 10 DC_Transmit MSA Output 11 Trans_HSRO_Data MSA Output 12 Capture_HSRO_Data MSA Output 13 Monitor_BX_Clock MSA Output 14 Monitor Raw L1_Acpt & L1_Period MSA Output 15 Front_PB & DC Card Output Signal Output MSA Pin Nums. DC Label and Function ------------------ ------------- ---------- ----------------------- ERPB_Input_Clk_0 MSA Output 16 pins 1,2 nc ERPB_Input_Clk_1 MSA Output 17 pins 3,4 mtg-0 ERPB Input Clk ERPB_EMTot_Sel_0 MSA Output 18 pins 5,6 nc ERPB_EMTot_Sel_1 MSA Output 19 pins 7,8 mtg-1 ERPB EM/Tot Manual_Control_0 MSA Output 20 pins 9,10 mtg-2 Lookback(0) Manual_Control_1 MSA Output 21 pins 11,12 mtg-3 Lookback(1) Manual_Control_2 MSA Output 22 pins 13,14 mtg-4 Lookback(2) CMD_Armed_0 MSA Output 23 pins 15,16 nc ERPB_Capture_2 MSA Output 24 pins 17,18 mtg-5 ERPB Capture Data CMD_Armed_1 MSA Output 25 pins 19,20 nc Manual_Control_3 MSA Output 26 pins 21,22 mtg-6 Lookback(3) Manual_Control_4 MSA Output 27 pins 23,24 mtg-7 DC Config Control Manual_Control_5 MSA Output 28 pins 25,26 mtg-8 Lookback(4) & DC Config Control Manual_Control_6 MSA Output 29 pins 28,28 mtg-9 DC Config Control DC_Transmit_2 MSA Output 30 pins 29,30 mtg-x DC XMIT Trig Manual_Control_7 MSA Output 31 pins 31,32 mtg-y no connection NOTE: The strange pinout of the 16 signal immediately above is required in order to match up with the strange pinout of the MTG input connector on the DC Card. For now the ERPB_Input_Clk_0 output and the ERPB_EMTot_Sel_0 output have been disabled. These copies of these signals are not used on the DC card (and they are not even terminated on the DC). To help keep the Timing_&_Control Distribution system as quiet as possible these signals have been disabled. This setup requires modifying the DC Card so that it can receive XMIT Trig on its MTG-X signal instead of on MTG-6 as it was originally setup to do. See the dc_board_description.txt file for details. End of CT_Readout_Helper _9_1 from 24-JULY-2002 =========================================================================== The following is for CT_Readout_Helper _8_1 from 14-Nov-2001 FPGA Description Level 1 Calorimeter Trigger Read Helper Function --------------------------------------------------- Original: 7-AUG-2001 Latest: 26-NOV-2001 Introduction ------------ This document describes the architecture and implementation of the Level 1 Calorimeter Trigger Read Helper Function FPGA. This design will start by just providing the sequence of timing signals that are needed by the L1 CT Readout each time there is a Level 1 Accept. The Level 1 Calorimeter Trigger Read Helper Function is located at FPGA Site #4 on an FM Card. This FM card is currently in slot #21 of the middle crate in M101. This FPGA design may gain additional functions as the L1 CT Readout developes. The balance between functions performed by this part and functions performed by the Run I MTG is not yet fully understood. The design of the CT_Read_Helper will use many of the same blocks that were developed for the L1 FW Helper FPGA. The CT_Read_Helper FPGA has the following input connections: BX Helper Clock CMC_TL_7 (i.e. 132 nsec clock) MSA_In_51 Spare Marker CMC_TL_6 MSA_In_53 Sync Gap Marker CMC_TL_5 MSA_In_55 Cosmic Gap Marker CMC_TL_4 MSA_In_57 53 MHz (Disabled) CMC_P_Clk MSA_In_49 L1 Accept (for this Geo Section) MSA_In_0 L1 Period (i.e. this SCL Frame contains an L1_Acpt) MSA_In_1 ERPB_Input_Clock (from Master Clock Sequencer #2 TL 20) MSA_In_21 ERPB_EM/Tot_Sel (from Master Clock Sequencer #2 TL 21) MSA_In_19 The first 5 signals in this list all come from: Carmen Master Clock via Selector Fanout #8 "Helper B" to the M101 Middle J5 of the Rear_PB at the P2 connection of Slot #21. Only the first signal (BX_Helper_Clk) from this group of 5 signals is currently used. The L1_Accept for this Geo Section and the L1_Period signals arrive from the L1 Trigger Framework via single signal Diff-ECL cables. ERPB_Input_Clock and ERPB_EM/Tot_Sel arrive from the L1 Cal Trigger Sequencer in the Carmen Master Clock. Note that MSA_In_19 is pin 57 on FPGA Site #4 which is a secondary clock net Note that MSA_In_51 is pin 239 on FPGA Site #4 which is a secondary clock net The CT_Read_Helper FPGA has the following output connections: Capture HSRO Data Transport HSRO Readout Data Capture Monitor Data Capture Monitor Data Armed Scaler Reset TCC Manual Control Lines (8) (some used for ERPB Readback control) ERPB Capture Data DC Transport Data ERPB Input Clock ERPB EM/Tot Sel These inputs and outputs are defined in the User Constraint File for this FPGA (including which MSA In/Out is used, where appropriate). The 3th item is a per Geographic Section L1_Acpt signal that will need to be brought out of the Trig FW as a differential ECL signal. As with the other systems that are readout with VRB's, the readout of the Level 1 Calorimeter Trigger will require 2 Geographic Sections: one for the VRB, and a second one for the source of the data that the VRB reads out. This second Geographic Section is called a non-readout G.S. by COOR because Level 3 does not receive and data from this G.S. This CT_Read_Helper receives the L1_Acpt from this 2nd Geographic Section and then generates the sequence of timing signals that result in sending data to the VRB. The strong intent is to make this sequence of timing signals include all the signals that are involved in readout of the L1 Trig FW data Block and to place these signals on the same P1 Timing Signal pins as are used in the Trig FW. The ideas is to be able to plug a Run II FW card into the L1 Cal Trig readout crate (M101 Middle) and to be able to read it out. For example to be able to put a TRM with SHED FPGA's into this crate and read it out. Description of the Blocks within the CT_Read_Helper --------------------------------------------------- 1. On-Card Bus Interface This is the standard On-Card Bus Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. 2. The generation of the various output signals falls into a couple of categories: The ERPB_Input_Clock and the ERPB_EM/Tot_Sel just pass through the CT_Read_Helper. Their output is just via buffers, i.e. there is no latch controling the "re-timing" of these signals. The CT_Read_Helper fpga has access to these signals for use in generating some of its other outputs. ERPB_EM/Tot_Sel is received on a Global Buffer and is used to time the output of the ERPB Capture Data signal. DC Transmit Trigger The start of this signal is delayed from the L1_Acpt by a programmable number of BX_Clock ticks. This signal is about 1 usec wide. ERPB Capture Data The start of this signal is not delayed from the L1_Acpt. Rather first it is brought into sync with the BX_Clk and then it is asserted for one positive edge to positive edge period of the EM/Tot Select signal. So ERPB Capture Data only changes state at a point in time when the FIFO address in the ERPB is already changing. There is a control bit that lets you enable or disable the generation of the ERPB Capture Data siganl. The state of the Scaler Reset and the TCC Manual Control lines is programmed via register, and these outputs uptade on the positive BX_Clock edges. 4 of the TCC Manual Control lines are used to control how far back the read cycle is in the ERPB FIFO, i.e. the LookBack value. Capture HSRO Data Transport HSRO Readout Data Capture Monitor Data all have a number of programmable features. In general they are 1 period of the BX_Clock wide, they update on positive BX_Clock edges and they begin a programmable number of BX_Clock ticks after each L1_Acpt. Capture HSRO Data and Transport HSRO Data both work the same way. They requires the L1 Accept signal to this Geographic Section AND the L1 Period to both be active at the same time when they are clocked into this module by the Helper_Clk. These two signals should each be active for 1 Tick and the Transport HSRO Data should follow Capture HSRO Data by ?? Ticks. Capture HSRO Data itself should be ?? Ticks after the L1_Acpt. Capture Monitor Data must be initiated by TCC. It then can be generated immediately or generated upon the receipt of an L1 Accept. It should be active for 1 Tick. Like Capture HSRO Data, Capture Monitor Data will be a programmable number of ticks after the L1 Accept. Capture Monitor Data Armed indicates that on the next L1_Acpt a Capture Monitor Data signal will be issued. Programming Interface --------------------- The CT_Read_Helper Function FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) * 1 R/W Chip Control Status Register (MSW) 8 R/W Trans HSRO Data P1_TS(8) 9 R/W Capture HSRO Data P1_TS(9) 10 R/W Capture Monitor Data P1_TS(10) 11 R/W ERPB_Capture_Data 12 R/W DC_Transmit_Trigger 14 R/W TCC Manual Control Lines 15 R/W Scaler Reset P1_TS(15) The bit allocation in each of these registers is given below. Chip Control Status Register LSW Reg Adrs 0 Typical Readback Value $ffe8 Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 3 --- not allocated 4 R/W Helper Mode ('0': Normal Mode '1': Test Mode) 15:5 --- not allocated Transport HSRO Data P1_TS(8) Control Reg Adrs 8 Typical Readback Value $0003 Capture HSRO Data P1_TS(9) Control Reg Adrs 9 Typical Readback Value $0001 Capture Monitor Data P1_TS(10) Control Reg Adrs 10 Typical Readback Value $00a1 DC Transmit Control Reg Adrs 12 Typical Readback Value $? Bit Access Contents --- ------ -------- 3:0 R/W Delay to Pulse The output TS will be asserted for a single tick, once this channel's timing chain has been "launched" (either via TCC or via an external request). The value in this register defines the delay between the "launch" stimulus and the assertion of the TS. For example, a value of "1" indicates that the output TS will go high on the 2nd Helper Clock rising edge following the stimulus, and return low on the 3rd Helper Clock rising edge following the stimulus. 4 R/W Immediate Pulse Request (Launch TS Now) (Write 0 to clear, write 1 to request. Output TS will pulse after the delay specified above.) 5 R/W Single-Cycle Arm (Launch TS on next external start, only meaningful in Single-Cycle Mode) (write 0 to clear, write 1 to arm. If TCC takes this bit low prior to the "next" external start stimulus, that stimulus will still result in the channel being launched. TCC must examine bit 9 to know whether a Single-Cycle request is currently pending) 6 R/W unallocated 7 R/W Require TCC Arming (i.e. Single-Cycle Mode) (0: Channel cycles on every external "start" 1: Channel cycles only for the first "start" after TCC has Armed the channel (via bit 5) 8 R Pending Immediate Request (0: No Immediate Request pending 1: Immediate Request pending) 9 R Pending Single-Cycle Request (0: No Single-Cycle Request pending 1: Single-Cycle Request pending, i.e. the Single-Cycle Mode was armed but there has been no external "start" stimulus.) Note: bits 8 and 9 are both cleared after the output TS has pulsed, for whatever reason (i.e. the Pending Single-Cycle request is cleared even if the TS pulses due to an Immediate Request, and vice-versa). 15:10 R/W unallocated ERPB Capture Control Reg Adrs 11 Typical Readback Value $0001 Bit 0 assert this bit to enable generation of the ERPB Capture Data signal Bits 7:1 are not used - they read back with what ever you have programmed into them. Bits 15:8 are not use always read back as zero. TCC Manual Control Lines Register Address 14 Typical Readback Value $0079 Bits 7:0 are TCC Manual Control 7:0 On the TCC Manual DC-ERPB Control Signal Becomes Which Is Used For ---------------- ------- ------------------- Manual_Control_0 mtg-2 Lookback(0) Manual_Control_1 mtg-3 Lookback(1) Manual_Control_2 mtg-4 Lookback(2) Manual_Control_3 mtg-6 Lookback(3) Manual_Control_4 mtg-7 DC Config Control Manual_Control_5 mtg-8 Lookback(4) & DC Config Ctrl Manual_Control_6 mtg-9 DC Config Control Manual_Control_7 mtg-y no connection Bits 15:8 are not used read back as written Bits 5,3:0 These 5 Manual Control Lines connect to 5 of the "MTG" lines that run to the DC card and then to the ERPB cards. These 5 bits control the 5 bit Lookback value in the ERPB cards. For now a good value to load in here is $19 = 25 --> a look back of 7. Note that the Manual_Control_5 is also used by the DC card Configuration Control Logic. Bits 6:4 These 3 Manual Control Lines connect to 3 of the "MTG" lines that run to the DC card. These 3 bits control the Configuration Logic on the DC card. A certain combination of these bits will cause the DC to re-configure all the FPGA's on all the ERPB cards. Note that the Manual_Control_5 is also used by the ERPB card. The required sequence to cause LCA Configuration is described in the dc_board_description.txt file. Bit 7 This bit is tied to MTG_Y line that runs to the DC card. It is not used for anything at this time. MTG_Y is received on the DC card but it is not connected to any thing. Scaler Reset P1_TS(15) Control (Normal Mode) Reg Adrs 15 Typical Readback Value $0000 Bit Access Description --- ------ ----------- 0 R/W Reset Scalers ('0': clear P1_TS(15) '1': assert P1_TS(15)) 15:1 R/W unallocated I/O Function to MSA_ In-Out Mapping of the CT_Read_Helper ------------------------------------------------------------- BX_Clock = Helper_Clk MSA Input 51 L1_Accept MSA Input 0 L1_Period MSA Input 1 ERPB_Input_Clock (from Master Clock Seq #2 TL 20) MSA_In_21 ERPB_EM/Tot_Sel (from Master Clock Seq #2 TL 21) MSA_In_19 Trans_HSRO_Data MSA Output 0 Capture_HSRO_Data MSA Output 1 Capture_Monitor_Data MSA Output 2 Scaler_Reset MSA Output 3 ERPB_Capture_Data MSA Output 4 DC_Transmit MSA Output 5 Trans_HSRO_Data MSA Output 6 Capture_HSRO_Data MSA Output 7 Capture_Monitor_Data MSA Output 8 Scaler_Reset MSA Output 9 ERPB_Capture_Data MSA Output 10 DC_Transmit MSA Output 11 Trans_HSRO_Data MSA Output 12 Capture_HSRO_Data MSA Output 13 Capture_Monitor_Data MSA Output 14 Scaler_Reset MSA Output 15 Front_PB & DC Card Output Signal Output MSA Pin Nums. DC Label and Function ------------------ ------------- ---------- ----------------------- ERPB_Input_Clk_0 MSA Output 16 pins 1,2 nc ERPB_Input_Clk_1 MSA Output 17 pins 3,4 mtg-0 ERPB Input Clk ERPB_EMTot_Sel_0 MSA Output 18 pins 5,6 nc ERPB_EMTot_Sel_1 MSA Output 19 pins 7,8 mtg-1 ERPB EM/Tot Manual_Control_0 MSA Output 20 pins 9,10 mtg-2 Lookback(0) Manual_Control_1 MSA Output 21 pins 11,12 mtg-3 Lookback(1) Manual_Control_2 MSA Output 22 pins 13,14 mtg-4 Lookback(2) CMD_Armed_0 MSA Output 23 pins 15,16 nc ERPB_Capture_2 MSA Output 24 pins 17,18 mtg-5 ERPB Capture Data CMD_Armed_1 MSA Output 25 pins 19,20 nc Manual_Control_3 MSA Output 26 pins 21,22 mtg-6 Lookback(3) Manual_Control_4 MSA Output 27 pins 23,24 mtg-7 DC Config Control Manual_Control_5 MSA Output 28 pins 25,26 mtg-8 Lookback(4) & DC Config Control Manual_Control_6 MSA Output 29 pins 28,28 mtg-9 DC Config Control DC_Transmit_2 MSA Output 30 pins 29,30 mtg-x DC XMIT Trig Manual_Control_7 MSA Output 31 pins 31,32 mtg-y no connection NOTE: The strange pinout of the 16 signal immediately above is required in order to match up with the strange pinout of the MTG input connector on the DC Card. This setup requires modifying the DC Card so that it can receive XMIT Trig on its MTG-X signal instead of on MTG-6 as it was originally setup to do. See the dc_board_description.txt file for details.