***************************** * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * * and * * * * Level 2 Trigger Framework * * * * Helper Function * * * * FPGA Description * * * ***************************** Original: 15-SEP-1998 Latest: 21-APR-2000 Introduction ------------ This document concentrates on the architecture and implementation of the L1 Framework Helper Functions (HF) FPGA. Most of the Helper Functions involve allowing the Trigger Control Computer to perform operations that need to be coordinated closely in time with the Master Clock timing system that sequences the operation of the Run II Framework. Helper Functions generate an output control signal (typically a P1 Timing Signal) that is controlled by TCC and other electrical signals. Additionally, there must be a provision for some of the output signals to be generated solely by TCC for use during testing. The Helper Functions will be implemented on one or more FM cards. The current idea is to use FPGA #4. Additional FPGAs may be required as the design develops. The HF FPGA has the following input and output connections: 1. On-Card Bus input/output 2. Helper Clock input 3. L1 Accept input 4. Error lines from the 4 TRMs input 5. XOFF from the VRB (?) input 6. Transport High Speed Readout Data output 7. Capture HSRO Data output 8. Capture Monitor Data output 9. Maginot Line output 10. Scaler Reset output 11. TCC Global Disable output 12. TCC Generic Controllable outputs These inputs and outputs are defined in the User Constraint File for this FPGA (including which MSA In/Out is used, where appropriate). This file is available in the helper_functions directory on the MSU WWW server. Operation--General Comments --------------------------- The HF FPGA is composed of the following elements: 1. On-Card Bus Interface 2. Data Capture and Transfer, consisting of A. Transport Data B. Capture HSRO Data C. Capture Monitor Data D. Maginot Line 3. Other Signals, consisting of A. Scaler Reset B. TCC Global Disable C. 2 additional generic TCC Controllable Signals D. 2 copies of the "Capture Monitor Data Armed" signal Each element is described below. 1. On-Card Bus Interface This is the standard On-Card Bus Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. 2. Data Capture and Transfer Data Capture and Transfer will operate in 2 modes: Normal mode and Test mode. In Test mode, the 4 Output Signals (Transport HSRO Data, Capture HSRO Data, Capture Monitor Data, and Maginot Line) will be generated by TCC alone so that the Framework can be tested without relying on the external signals normally available during data taking. Test Mode --------- The Test mode essentially mimics the Helper Function Toy FPGA. A pattern of single pulses is produced based on a single Master Timing Signal. The Master Timing Signal clocks an 8-bit counter which is initiated by TCC. The counter counts from 0 to 255, incrementing with each rising edge of the Master Timing Signal, and then stops. Each of the 4 Output Timing Signals has a two comparators, designated Start and Stop. These comparators are programmable by TCC. When the Output Timing Signal is in Pulse Mode and the counter reaches the Start value, the Timing Signal will rise. When the counter reaches the Stop value, the Output Timing Signal will fall. Typically the Stop value will be greater than the Start value, such that the Output Timing Signal will be LOW with a brief excursion HIGH. However, programming the comparators in the opposite manner will produce the opposite behavior. When the Output Timing Signal is in Toggle mode, the Timing Signal begins to toggle when the counter reaches the Start value and stops toggling when the counter reaches the Stop value. Note that if the Stop value is the Start value + 1, the Output Timing Signal will toggle only once. The Toggle flip-flop for each Output Timing Signal can be cleared by TCC. Finally, each Output Timing Signal can be forced LOW or HIGH by TCC. Normal Mode ----------- In Normal mode the 4 Output Signals are generated by external inputs. All 4 may use the TRM Clock for synchronization. There are 2 ways to assert the Maginot Line. Method 1: The Maginot Line is the OR of the 4 Synchronization Error lines from the 4 TRM modules. It should be active for as long as an error condition exists. Method 2: The Maginot Line goes high when the Front-End Error Input goes high. It remains high until cleared by TCC. See programming interface below. Both methods are always enabled. The output Maginot Line is simply the OR of both methods described above. Transport HSRO Data requires an L1 Accept. It may also need information from the VRB as to whether or not it is ready for new data. Transport Data should be active for 1 Tick. Transport HSRO Data should follow Capture HSRO Data. Capture HSRO Data also requires an L1 Accept, and it also should be active for 1 Tick. Capture HSRO Data will be a programmable number of ticks after the L1 Accept. Capture Monitor Data must be initiated by TCC. It then can be generated immediately or generated upon the receipt of an L1 Accept. It should be active for 1 Tick. Like Capture HSRO Data, Capture Monitor Data will be a programmable number of ticks after the L1 Accept. 3. Other Signals A. Scaler Reset Scaler Reset also operates in either "Test" or "Normal" Mode, as described above. In Test Mode, it operates exactly as the other "Test Mode" signals described above. In Normal Mode, it can be set via a TCC write. B. TCC Global Disable This signal does not have a "Test" vs. "Normal" mode. It simply always reflects the state of a TCC writable register. It is used as a Global Disable to the TDM cards to stop the flow of triggers when necessary. C. TCC Generic Controllables 0 and 1 This signal works exactly like the TCC Global Disable. D. Capture Monitor Data Armed copies 1:0 These 2 copies of the "Capture Monitor Data Armed to cycle with next L1 Accept" signal are brought out to pads and driven off the L1 Helper card. One copy is delivered to the L2 Auxiliary Data TRM, while the second copy is delivered to the FOM++ to be used as a Hardware L1 Qualifier. Note: The L1 Helper no longer generates P1_TS(14:12). These signals have been moved to the L2 Helper. In Test Mode, the control for these signals remains due to the structure of the FPGA. In Normal Mode, the control for these signals has been removed as noted below. Programming Interface --------------------- The Helper Function FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) * 1 R/W Chip Control Status Register (MSW) 8 R/W P1_TS(8) [Trans HSRO Data] Control (Normal Mode) 9 R/W P1_TS(9) [Cap HSRO Data] Control (Normal Mode) 10 R/W P1_TS(10) [Cap Monitor Data] Control (Normal Mode) 11 R/W P1_TS(11) [Maginot Line] Control (Normal Mode) * 12 R/W P1_TS(12) Control (Normal Mode) * 13 R/W P1_TS(13) Control (Normal Mode) * 14 R/W P1_TS(14) Control (Normal Mode) 15 R/W P1_TS(15) [Scaler Reset] Control (Normal Mode) 16 R/W Timing Signal Control Status 0 (Test Mode) 17 R/W Timing Signal Control Status 1 (Test Mode) 18 R/W Timing Signal Control Status 2 (Test Mode) 19 R Timing Signal Status Readback Register (Test Mode) 20 R/W P1_TS(8) [Trans HSRO Data] Start/Stop Comp (TM) 21 R/W P1_TS(9) [Cap HSRO Data] Start/Stop Comp (TM) 22 R/W P1_TS(10) [Cap Mon Data] Start/Stop Comp (TM) 23 R/W P1_TS(11) [Maginot Line] Start/Stop Comp (TM) 24 R/W P1_TS(12) Start/Stop Comp (TM) 25 R/W P1_TS(13) Start/Stop Comp (TM) 26 R/W P1_TS(14) Start/Stop Comp (TM) 27 R/W P1_TS(15) [Scaler Reset] Start/Stop Comp (TM) 28 R/W TCC Global Disable/Controllable(1:0) Control * = This register not present in current version of FPGA, but reserved for future expansion. The bit allocation in each of these registers is given below. Chip Control Status Register LSW Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 3 --- not allocated 4 R/W Helper Mode ('0': Normal Mode '1': Test Mode) 15:5 --- not allocated The Chip Control Status Register is currently unused. P1_TS(8) [Transport HSRO Data] Control (Normal Mode) P1_TS(9) [Capture HSRO Data] Control (Normal Mode) P1_TS(10) [Capture Monitor Data] Control (Normal Mode) Bit Access Contents --- ------ -------- 3:0 R/W Delay to Pulse The output TS will be asserted for a single tick, once this channel's timing chain has been "launched" (either via TCC or via an external request). The value in this register defines the delay between the "launch" stimulus and the assertion of the TS. For example, a value of "1" indicates that the output TS will go high on the 2nd Helper Clock rising edge following the stimulus, and return low on the 3rd Helper Clock rising edge following the stimulus. 4 R/W Immediate Pulse Request (Launch TS Now) (Write 0 to clear, write 1 to request. Output TS will pulse after the delay specified above.) 5 R/W Single-Cycle Arm (Launch TS on next external start, only meaningful in Single-Cycle Mode) (write 0 to clear, write 1 to arm. If TCC takes this bit low prior to the "next" external start stimulus, that stimulus will still result in the channel being launched. TCC must examine bit 9 to know whether a Single-Cycle request is currently pending) 6 R/W unallocated 7 R/W Require TCC Arming (i.e. Single-Cycle Mode) (0: Channel cycles on every external "start" 1: Channel cycles only for the first "start" after TCC has Armed the channel (via bit 5) 8 R Pending Immediate Request (0: No Immediate Request pending 1: Immediate Request pending) 9 R Pending Single-Cycle Request (0: No Single-Cycle Request pending 1: Single-Cycle Request pending, i.e. the Single-Cycle Mode was armed but there has been no external "start" stimulus.) Note: bits 8 and 9 are both cleared after the output TS has pulsed, for whatever reason (i.e. the Pending Single-Cycle request is cleared even if the TS pulses due to an Immediate Request, and vice-versa). 15:10 R/W unallocated P1_TS(11) [Maginot Line] Control (Normal Mode) Bit Access Contents --- ------ -------- 0 R/W Clear Front End Errors (Clear Maginot Line) (0 for normal running 1 to clear or to disable Front End Errors) 15:1 R/W unallocated P1_TS(12) Control (Normal Mode) P1_TS(13) Control (Normal Mode) P1_TS(14) Control (Normal Mode) These registers not currently implemented P1_TS(15) [Scaler Reset] Control (Normal Mode) Bit Access Description --- ------ ----------- 0 R/W Reset Scalers ('0': clear P1_TS(15) '1': assert P1_TS(15)) 15:1 R/W unallocated Timing Signal Control Status 0 (Test Mode) Bit Access Description --- ------ ----------- 0 R/W Reset*/Initiate Counter ('0': Force Counter to 0x0000 '1': Start Counter, will run for 1 "cycle") 15:1 R/W Unallocated Timing Signal Control Status 1 (Test Mode) Bit Access Description --- ------ ----------- 0 R/W P1_TS(8) [Transport HSRO Data] Mode ('0': "Pulse" mode '1': "Toggle" mode) 1 R/W P1_TS(8) [Transport HSRO Data] Toggle Reset ('0': Toggle is allowed to toggle '1': Toggle is forced to 0) 3:2 R/W P1_TS(9) [Capture HSRO Data] Mode/Toggle Reset (see above) 5:4 R/W P1_TS(10) [Capture Monitor Data] Mode/Toggle Reset (see above) 7:6 R/W P1_TS(11) [Maginot Line] Mode/Toggle Reset (see above) 9:8 R/W P1_TS(12) Mode/Toggle Reset (see above) 11:10 R/W P1_TS(13) Mode/Toggle Reset (see above) 13:12 R/W P1_TS(14) Mode/Toggle Reset (see above) 15:14 R/W P1_TS(15) [Scaler Reset] Mode/Toggle Reset (see above) Timing Signal Control Status 2 (Test Mode) Bit Access Description --- ------ ----------- 0 R/W P1_TS(8) [Transport HSRO Data] Force LOW 1 R/W P1_TS(8) [Transport HSRO Data] Force HIGH (note: Force HIGH is dominant over Force LOW) 3:2 R/W P1_TS(9) [Capture HSRO Data] Force LOW/HIGH (see above) 5:4 R/W P1_TS(10) [Capture Monitor Data] Force LOW/HIGH (see above) 7:6 R/W P1_TS(11) [Maginot Line] Force LOW/HIGH (see above) 9:8 R/W P1_TS(12) Force LOW/HIGH (see above) 11:10 R/W P1_TS(13) Force LOW/HIGH (see above) 13:12 R/W P1_TS(14) Force LOW/HIGH (see above) 15:14 R/W P1_TS(15) [Scaler Reset] Force LOW/HIGH (see above) Timing Signal Status Readback Register (Test Mode) Bit Access Description --- ------ ----------- 0 R/W P1_TS(8) [Transport HSRO Data] Started 1 R/W P1_TS(8) [Transport HSRO Data] Stopped (note: Force HIGH is dominant over Force LOW) 3:2 R/W P1_TS(9) [Capture HSRO Data] Started/Stopped (see above) 5:4 R/W P1_TS(10) [Capture Monitor Data] Started/Stopped (see above) 7:6 R/W P1_TS(11) [Maginot Line] Started/Stopped (see above) 9:8 R/W P1_TS(12) Started/Stopped (see above) 11:10 R/W P1_TS(13) Started/Stopped (see above) 13:12 R/W P1_TS(14) Started/Stopped (see above) 15:14 R/W P1_TS(15) [Scaler Reset] Started/Stopped (see above) P1_TS(8) [Trans HSRO Data] Start/Stop Comp (Test Mode) P1_TS(9) [Cap HSRO Data] Start/Stop Comp (Test Mode) P1_TS(10) [Cap Mon Data] Start/Stop Comp (Test Mode) P1_TS(11) [Maginot Line] Start/Stop Comp (Test Mode) P1_TS(12) Start/Stop Comp (Test Mode) P1_TS(13) Start/Stop Comp (Test Mode) P1_TS(14) Start/Stop Comp (Test Mode) P1_TS(15) [Scaler Reset] Start/Stop Comp (Test Mode) Bit Access Description --- ------ ----------- 7:0 R/W Start Comparator Value 15:8 R/W Stop Comparator Value TCC Global Disable / Controllable(1:0) Control Register Bit Access Description --- ------ ----------- 0 R/W TCC Global Disable (TCC writes 1 to assert this output, this output is independent of Helper Mode) 1 R/W TCC Generic Controllable 0 (TCC writes 1 to assert this output, this output is independent of Helper Mode) 2 R/W TCC Generic Controllable 1 (TCC writes 1 to assert this output, this output is independent of Helper Mode) 15:3 R/W unassigned