// THE Card "Seed" MSA FPGA User Constraint File (good for FM and not FM) // MSU HEP 23 October 1996 // Last edit 26 November 1997 setup for FIRC FM MSA #4 // Last edit 1 December 1997 set MSA pins for FM MSA #4 // Last edit 1 December 1997 add timing constraints // Last edit 6 December 1997 constrain Quad_Done // Last edit 20 December 1997 must move Quad Done to 37 ns for Frame Enb Blk // Last edit 16 September1998 modified for helper function // 4 December 1998 modified to track helper fn changes // 8 June 1999 change TNM_NET to TNM for M1.4 compatiblity // 13 January 2000 modify pinout: some fn's moved to L2 Helper // 7 March 2000 add "CMD Armed" output (2 copies) // -------------------------------------------------------------------------- // Timing Constraints // -------------------------------------------------------------------------- // There is also a Beam Crossing Clock in this design, running at 7 * 18.8 ns // = 131.6 ns = 7.6 MHz. NET "BX_Clock" TNM = BX_Clk ; TIMESPEC TS_BX_Clk = PERIOD BX_Clk 131.6 ns high 18.8 ns ; // Need to ignore this constraint through the RESET path to this counter, // it can't meet spec but is OK anyway since I don't care if the counter // resets one clock cycle late, it does not affect the operation of // this device NET test_mode/T_C TIG ; // Additional constraints to cover the OCB. Each state in the state // engine lasts for 75 ns. // Writing. The data is input 75 ns before the write strobe is asserted. NET OCB_Data_PAD* OFFSET = IN 75 ns BEFORE "OCB_Write_Strobe_PAD*" ; // Reading. The request must propagate from the VME interface FPGA to the // PBS FPGA (estimate 25 ns), and the data must propagate back to the VME // interface FPGA (estimate 25 ns). // This leaves 100 ns for the data to be retrieved and put on to the OCB. TIMEGRP Direct_Pad = PADS ( "OCB_Direction_PAD" ) ; TIMEGRP Data_Out_Pads = PADS ( OCB_Data_PAD* ) ; // Only consider the paths through the register address decoder. NET Read_Reg* TPTHRU = Read_Reg ; TIMESPEC TS_Direct_In_to_Data_Out = FROM Direct_Pad THRU Read_Reg TO Data_Out_Pads 100 ns ; // -------------------------------------------------------------------------- // Special Characteristics Constraints // -------------------------------------------------------------------------- NET "Trans_HSRO_Data_PAD*" FAST; NET "Capture_HSRO_Data_PAD*" FAST; NET "Capture_Monitor_Data_PAD*" FAST; NET "Maginot_Line_PAD*" FAST; NET "Scaler_Reset_PAD*" FAST; // -------------------------------------------------------------------------- // Pinout Constraints // -------------------------------------------------------------------------- // Note: It is necessary to comment out certain lines to use this file // in the FM, and to comment out other lines to use this file in // non-FM cards. See comments at end of lines. // On-Card Bus and Timing Signals: DO NOT MODIFY (except FM/not FM changes) // note: OCB_Reg_Addr_PAD(8) present only on FM but not used on any card NET "OCB_Chip_Sel_PAD*" LOC = "P142" ; NET "OCB_Write_Strobe_PAD*" LOC = "P183" ; NET "OCB_Direction_PAD" LOC = "P136" ; NET "OCB_Reg_Addr_PAD(0)" LOC = "P169" ; NET "OCB_Reg_Addr_PAD(1)" LOC = "P168" ; NET "OCB_Reg_Addr_PAD(2)" LOC = "P167" ; NET "OCB_Reg_Addr_PAD(3)" LOC = "P165" ; NET "OCB_Reg_Addr_PAD(4)" LOC = "P164" ; NET "OCB_Reg_Addr_PAD(5)" LOC = "P163" ; NET "OCB_Reg_Addr_PAD(6)" LOC = "P162" ; NET "OCB_Reg_Addr_PAD(7)" LOC = "P160" ; // NET "OCB_Reg_Addr_PAD(8)" LOC = "P157" ; # not used NET "OCB_Data_PAD(0)" LOC = "P177" ; NET "OCB_Data_PAD(1)" LOC = "P173" ; NET "OCB_Data_PAD(2)" LOC = "P159" ; NET "OCB_Data_PAD(3)" LOC = "P152" ; NET "OCB_Data_PAD(4)" LOC = "P148" ; NET "OCB_Data_PAD(5)" LOC = "P141" ; NET "OCB_Data_PAD(6)" LOC = "P129" ; NET "OCB_Data_PAD(7)" LOC = "P123" ; NET "OCB_Data_PAD(8)" LOC = "P176" ; NET "OCB_Data_PAD(9)" LOC = "P172" ; NET "OCB_Data_PAD(10)" LOC = "P155" ; NET "OCB_Data_PAD(11)" LOC = "P154" ; NET "OCB_Data_PAD(12)" LOC = "P145" ; NET "OCB_Data_PAD(13)" LOC = "P138" ; NET "OCB_Data_PAD(14)" LOC = "P131" ; NET "OCB_Data_PAD(15)" LOC = "P126" ; NET "FPGA_OE_PAD*" LOC = "P187" ; NET "HQ_Timing_PAD(0)" LOC = "P2" ; NET "HQ_Timing_PAD(1)" LOC = "P63" ; NET "HQ_Timing_PAD(2)" LOC = "P124" ; NET "HQ_Timing_PAD(3)" LOC = "P184" ; NET "Chip_Status_PAD*" LOC = "P174" ; // High-Speed Read Out Signals: DO NOT MODIFY (except FM/not FM changes) // High Speed Readout Control and Data Bus Lines, Capture Control Lines // DO NOT MODIFY (except FM/not FM changes) and to exclude // NET "Capture_HSRO_Data_PAD*" LOC = "P133" ; # not on FM // NET "Capture_Monitor_Data_PAD*" LOC = "P134" ; # not on FM // NET "HSRO_DCE_In_PAD*" LOC = "P89" ; # FM only // NET "HSRO_DCE_In_PAD*" LOC = "P28" ; # not on FM // NET "HSRO_DCE_Out_PAD*" LOC = "P64" ; // NET "HSRO_Data_PAD(0)" LOC = "P178" ; // NET "HSRO_Data_PAD(1)" LOC = "P171" ; // NET "HSRO_Data_PAD(2)" LOC = "P156" ; // NET "HSRO_Data_PAD(3)" LOC = "P147" ; // NET "HSRO_Data_PAD(4)" LOC = "P146" ; // NET "HSRO_Data_PAD(5)" LOC = "P139" ; // NET "HSRO_Data_PAD(6)" LOC = "P128" ; // NET "HSRO_Data_PAD(7)" LOC = "P125" ; // NET "HSRO_Data_PAD(8)" LOC = "P175" ; // NET "HSRO_Data_PAD(9)" LOC = "P170" ; // NET "HSRO_Data_PAD(10)" LOC = "P153" ; // NET "HSRO_Data_PAD(11)" LOC = "P149" ; // NET "HSRO_Data_PAD(12)" LOC = "P144" ; // NET "HSRO_Data_PAD(13)" LOC = "P137" ; // NET "HSRO_Data_PAD(14)" LOC = "P130" ; // NET "HSRO_Data_PAD(15)" LOC = "P127" ; // NET "HSRO_Data_Valid_PAD*" LOC = "P132" ; // Dedicated and/or Reserved Signals: DO NOT MODIFY // (note: these signals not explicitly called out in FPGA design) // NET "CCLK goes here" LOC = "P179" ; // NET "DONE -- Chip_Configed" LOC = "P120" ; // NET "ERR/INIT* goes here" LOC = "P89" ; # HDI* on FM // NET "LDC* goes here" LOC = "P68" ; // NET "M0 -- VDD" LOC = "P60" ; // NET "M1 -- GROUND" LOC = "P58" ; // NET "M2 -- VDD" LOC = "P62" ; // NET "PROG* -- Config_Chip*" LOC = "P122" ; // NET "TCK goes here" LOC = "P7" ; // NET "TDI goes here" LOC = "P6" ; // NET "TDO goes here" LOC = "P181" ; // NET "TMS goes here" LOC = "P17" ; // NET "formerly OCB_Reg_Addr_PAD(8)" LOC = "P157" ; // MSA Input and MSA Output signals, these are specific to this // particular FPGA design NET "BX_Clock_PAD" LOC = "P239" ; # MSA Input 51 NET "L1_Accept_PAD" LOC = "P35" ; # MSA Input 0 // NET "L2_Accept_PAD" LOC = "P36" ; # MSA Input 1 NET "VRB_XOFF_PAD" LOC = "P38" ; # MSA Input 2 NET "TRM_Error_PAD(0)" LOC = "P27" ; # MSA Input 32 NET "TRM_Error_PAD(1)" LOC = "P26" ; # MSA Input 33 NET "TRM_Error_PAD(2)" LOC = "P25" ; # MSA Input 34 NET "TRM_Error_PAD(3)" LOC = "P24" ; # MSA Input 35 NET "Front_End_Error_PAD" LOC = "P23" ; # MSA Input 36 NET "Trans_HSRO_Data_PAD(0)" LOC = "P100" ; # MSA Output 0 NET "Capture_HSRO_Data_PAD(0)" LOC = "P99" ; # MSA Output 1 NET "Capture_Monitor_Data_PAD(0)" LOC = "P97" ; # MSA Output 2 NET "Maginot_Line_PAD(0)" LOC = "P96" ; # MSA Output 3 // NET "Inc_L3_Xfer_PAD(0)" LOC = "P95" ; # MSA Output 4 // NET "Trans_Mask_L2_PAD(0)" LOC = "P94" ; # MSA Output 5 // NET "Send_L2_Dec_PAD(0)" LOC = "P93" ; # MSA Output 6 NET "Scaler_Reset_PAD(0)" LOC = "P92" ; # MSA Output 7 NET "Trans_HSRO_Data_PAD(1)" LOC = "P88" ; # MSA Output 8 NET "Trans_HSRO_Data_PAD(2)" LOC = "P87" ; # MSA Output 9 NET "Trans_HSRO_Data_PAD(3)" LOC = "P86" ; # MSA Output 10 NET "Capture_HSRO_Data_PAD(1)" LOC = "P85" ; # MSA Output 11 NET "Capture_HSRO_Data_PAD(2)" LOC = "P84" ; # MSA Output 12 NET "Capture_HSRO_Data_PAD(3)" LOC = "P82" ; # MSA Output 13 NET "Capture_Monitor_Data_PAD(1)" LOC = "P81" ; # MSA Output 14 NET "Capture_Monitor_Data_PAD(2)" LOC = "P79" ; # MSA Output 15 NET "Capture_Monitor_Data_PAD(3)" LOC = "P225" ; # MSA Output 16 NET "Capture_Monitor_Data_PAD(4)" LOC = "P224" ; # MSA Output 17 NET "Capture_Monitor_Data_PAD(5)" LOC = "P223" ; # MSA Output 18 NET "Maginot_Line_PAD(1)" LOC = "P221" ; # MSA Output 19 NET "TCC_Global_Disable_PAD" LOC = "P220" ; # MSA Output 20 NET "TCC_Controllable_PAD(0)" LOC = "P218" ; # MSA Output 21 NET "TCC_Controllable_PAD(1)" LOC = "P217" ; # MSA Output 22 NET "Scaler_Reset_PAD(1)" LOC = "P216" ; # MSA Output 23 NET "Scaler_Reset_PAD(2)" LOC = "P215" ; # MSA Output 24 NET "Scaler_Reset_PAD(3)" LOC = "P214" ; # MSA Output 25 NET "Scaler_Reset_PAD(4)" LOC = "P213" ; # MSA Output 26 NET "Scaler_Reset_PAD(5)" LOC = "P210" ; # MSA Output 27 NET "CMD_Armed_PAD(0)" LOC = "P209" ; # MSA Output 28 NET "CMD_Armed_PAD(1)" LOC = "P208" ; # MSA Output 29 // NET "MSA_Output_PAD(30)" LOC = "P207" ; # MSA Output 30 // NET "MSA_Output_PAD(31)" LOC = "P206" ; # MSA Output 31