L2 Framework Helper Functions FPGA ----------------------------------- Original: 13-DEC-1999 Revised: 15-MAY-2000 Introduction ------------ The L2 Framework is managed by the L2 Framework Helper Function FPGA (see the document l2_fw_helper_function_design.txt in the Web directory at www.pa.msu.edu/hep/d0/ftp/l1/framework/hardware/helper_functions for more information on the design of this FPGA. This document describes the programming interface and FPGA/card pinout of this FPGA. The L2 FW Helper FPGA is intended to be used at MSA FPGA Site 4 of a FM Card. At the board level, the inputs and outputs to this FM Card (excluding the P1 VME and Timing signals, which are common to all boards) are: Inputs ------ Name MSA_In Comment ---- ------ ---------------- L2_Busy_Answer_Delay(0) 16 L2_Busy_Answer_Delay(1) 17 (unused) 19 Global Clock net Live_Crossing 21 L1_STF_FIFO_Not_Empty 23 L2_Ans_FIFO_Not_Empty 25 Transfer_to_L3_Required 27 L2_Capture_Monitor_Data_Request 29 L2_Global_Answer_Strobe 31 Helper_Clock 51 Global Clock net Outputs ------- Name MSA_Out Destination ---- ------- ----------- Input_TRM_Read_Enable(0) 0 P1_TS(13) M122 Bot Input_TRM_Read_Enable(1) 1 P1_TS(13) M123 Mid Send_L2_Decision(0) 2 P1_TS(14) M123 Mid Send_L2_Decision(1) 3 P1_TS(14) M123 Bot L3_Control_Data_Latch_Enable(0) 4 P1_TS(12) M122 Bot L3_Control_Data_Latch_Enable(1) 5 P1_TS(12) M123 Bot L3_Data_Strobe_Inc_Xfr_Number(0) 6 P1_TS(12) M123 Mid L2_Maginot_Line(0) 7 P1_TS(11) M122 Bot L2_Maginot_Line(1) 8 P1_TS(11) M123 Mid * L2_Capture_Monitor_Data(0) 9 P1_TS(10) M122 Bot Waiting_for_L2_BAD 10 P1_TS(9) M122 Bot *** The following 5 signals are only intended for TEMPORARY *** *** testing during commissioning *** Send_L2_Decision Copy 11 for Logic Analyzer L3_Control_Data_Latch_Enable Copy 12 for Logic Analyzer L3_Data_Strobe_Inc_Xfr_Number Copy 13 for Logic Analyzer L2_Capture_Monitor_Data Copy 14 for Logic Analyzer L2_Answer_TRM_Write_Clock Copy 15 for Logic Analyzer *** end of TEMPORARY signals *** L2_Answer_TRM_Write_Clock(0) 16 M122 B S4 MSA_In(33) L2_Answer_TRM_Write_Clock(1) 17 M122 B S4 MSA_In(49) L2_Answer_TRM_Write_Clock(2) 18 M122 B S4 MSA_In(97) L2_Answer_TRM_Write_Clock(3) 19 M122 B S4 MSA_In(113) L2_Answer_TRM_Write_Clock(4) 20 M122 B S3 MSA_In(33) L2_Answer_TRM_Write_Clock(5) 21 M122 B S3 MSA_In(49) L2_Answer_TRM_Write_Clock(6) 22 M122 B S3 MSA_In(97) L2_Answer_TRM_Write_Clock(7) 23 M122 B S3 MSA_In(113) Send_L2_Decision(2) 25 L2 Buffer Depth Ctr ** Send_L2_Decision_to_SCL 26 SCL Hub Cnt JP2 P5/P6 L3_Data_Strobe_Inc_Xfr_Number(1) 27 L3 ...... *** L3_Data_Strobe_Inc_Xfr_Number(2) 28 L3 Event Counter **** L2_Capture_Monitor_Data(1) 29 M123 B S20 P5(0) L2_Capture_Monitor_Data(2) 30 M123 M S18 P5(0) L2_Capture_Monitor_Data(3) 31 M123 M S17 P5(0) Notes ----- * This copy of L2 Mag Line is not currently planned to be used but cabling is installed ** The L2 Buffer Depth Counter does not yet exist *** Need to understand pinout of this connector **** The L3 Event Counter does not yet exist Scaler Functionality -------------------- The L2 Helper FPGA provides a number of scalers: (1) Number of L2 Framework Cycles - increments once for each L2 Cycle, when Send L2 Decision is high (2) Number of L2 Framework Cycles terminating with Accept - increments zero or one times for each L2 Cycle, when Send L2 Decision and Transfer to L3 Required are both high (3) Number of L2 Framework Cycles terminating with Reject - increments zero or one times for each L2 Cycle, when Send L2 Decision is high and Transfer to L3 Required is low (4) BX Number - increments once for every 132 ns tick (5) Number of BX Spent in L2 FW Cycles - increments once for every 132 ns tick during each L2 Cycle (6) Number of BX Spent Waiting in L2 BAD State - increments once for every 132 ns tick during the Waiting for L2 BAD state - NOTE: recall there are 2 requirements to exit the Waiting for L2 BAD state: need no L2 Busies (L2 BAD output) and an available slot (Carmen Master Clock signal). This scaler does not distinguish between these 2 reasons. (7) Number of BX Spent Waiting with L2 Busies - increments once for every 132 ns tick during the Waiting for L2 BAD state ONLY IF one or more L2 Busies are actually delaying the L2 Accept - NOTE: this signal is a better indicator of L2 Busy activity as it does not include the time spent waiting for an available slot WITHOUT a L2 Busy asserted. These scalers cannot be reset via the "Timing Signal" scaler reset mechanism. However, they can all be reset simultaneously via TCC. These scalers are read out via the normal Monitor Data Readout path. Programming Interface --------------------- The L2 Framework Helper FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 --- Chip Control Status Register (MSW) 2 R/W unallocated 3 R/W Force Scaler Reset Register 16 R/W State Engine Control 17 R State Engine Status 18 R/W Additional Control 19 R Input/Output Readback 21:20 R L2 Framework Cycle Count Scaler MSW:LSW 23:22 R L2 Accept Count Scaler MSW:LSW 25:24 R L2 Reject Count Scaler MSW:LSW 27:26 R BX Scaler (L2 Flavor) MSW:LSW 29:28 R Number of BX Spent in L2 Cycles Scaler MSW:LSW 31:30 R Number of BX Spent waiting in L2 BAD State MSW:LSW 33:32 R Number of BX Spent waiting with L2 Busy MSW:LSW The bit allocation of these registers is given below: Chip Control Status Register LSW Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 15:3 --- not allocated The Chip Control Status Register MSW is not used/allocated. Force Scaler Reset Register Bit Access Contents --- ------ -------- 0 R/W Force Reset for L2 Cycle Scaler 1 R/W Force Reset for L2 Accept Scaler 2 R/W Force Reset for L2 Reject Scaler 3 R/W Force Reset for BX Scaler (L2 flavor) 4 R/W Force Reset for BX in L2 Cycles Scaler 5 R/W Force Reset for BX waiting in L2 BAD State Scaler 6 R/W Force Reset for BX waiting with L2 Busy Scaler 14:7 R/W not allocated 15 R/W Force Reset all L2 FW Scalers simultaneously State Engine Control Bit Access Contents --- ------ -------- 0 R/W L2 Global Bypass Mode ('1': L2 Global Answer not required '0': L2 Global Answer required (normal mode)) 1 R/W Test Mode ('1': L2 Framework is in Test Mode '0': L2 Framework is in Normal Mode) 2 R/W Test Mode TCC Cycle Approval (TCC writes 1 to allow the L2 Cycle to proceed. TCC must write 0 to allow the L2 Cycle to conclude) 3 R/W Immediate Capture Monitor Data (TCC writes 0-1-0 to force an immediate L2 Capture Monitor Data -- this CMD will be active only for one 132 ns tick just like the normal Capture Monitor Data) 14:3 R/W unallocated 15 R/W Force State Engine Reset ('1': Force State Engine to Quiescent Mode '0': Normal Mode) State Engine Status Bit Access Contents --- ------ -------- 0 R Quiescent State 1 R Simulate L2 Delay State (set in Bypass Mode only) 2 R Check L2 Answer State (set only if NOT in Bypass Mode) 3 R Wait for L2 Busy Answer Delay State 4 R L3 Transport State (set only if event passed to L3) 5 R Capture Monitor Data State (set only if event generated Capture Monitor Data) 6 R Cooldown_1 State 7 R Waiting for TCC Cycle Approval (set in Test Mode only) 8 R Waiting for TCC Cycle Approval Removal (Test Mode only) ('1' in any state indicates that, for the current L2 Cycle, the State Engine is currently in or has progressed through that state. When the Quiescent State is reached, the "thermometer" is cleared) 13:9 R unallocated 14 R L2 Answer Timeout Flag ('1': The L2 State Engine is currently "timed out," having waited 10 seconds for an Answer from L2 Global) 15 R Busy Answer Delay Timeout Flag ('1': The L2 State Engine is currently "timed out," having waited 10 seconds for all required Front Ends to drop their L2 Busy signals. Auxiliary Control Bit Access Contents --- ------ -------- 0 R/W L2 Answer Strobe Source ('1': Controlled by TCC '0': Controlled by L2 Global) 1 R/W L2 Answer Strobe TCC Control (when bit 0 of this reg is 0, this bit is output output by the L2 Helper as the L2 Answer Strobe) Input/Output Readback Bit Access Contents --- ------ -------- 0 R L1 ST Fired FIFO Not Empty (Input) 1 R L2 Answer FIFO Not Empty (Input) 2 R Available L2 Slot (Input) 4:3 R L2 Busy Answer Delay (1:0) (Input) (note: the 1:0 above refers to the two L2 BAD cards, the outputs of which are ORed in the L2 Helper) 5 R Transfer to L3 Required (Input) 6 R Capture Monitor Data Request (Input) 7 R L2 Global Answer Strobe (Input) 8 R Input TRM Read Enable (Output) 9 R Send L2 Decision (Output) 10 R L3 Control Data Latch Enable (Output) 11 R L3 Strobe/Increment L3 Transfer Number (Output) 12 R L2 Maginot Line (Output) 13 R L2 Capture Monitor Data (Output) 14 R L2 Answer TRM Write Clock (Output) ============================================================================ L2 Framework Helper Functions FPGA ----------------------------------- Original: 13-DEC-1999 Revised: 14-MAR-2002 Introduction ------------ The L2 Framework is managed by the L2 Framework Helper Function FPGA. For a full description of the L2 Framework processing cycle see: www.pa.msu.edu/hep/d0/ftp/l1/framework/hardware/helper_functions l2_fw_helper_function_design.txt This document describes the programming interface and FPGA/card pinout of the January 2002 version of the L2_Helper. The L2 FW Helper FPGA is intended to be used at MSA FPGA Site 4 of a FM Card. The board level inputs and outputs to the L2_Helper FM Card are shown in the following table: Inputs ------ Name MSA_In Comment ---- ------ ---------------- L2_Busy_Answer_Delay(0) 16 from a L2BAD card L2_Busy_Answer_Delay(1) 17 from a L2BAD card not currently used 19 Global Clock net Live_Crossing 21 from Carmen Master Clk L1_STF_FIFO_Not_Empty 23 from L1_STF_FIFO L2_Ans_FIFO_Not_Empty 25 from L2_Ans_FIFO Transfer_to_L3_Required 27 from L2_Accept FOM G.S. 127 L2_Capture_Monitor_Data_Request 29 from L2 Aux Data FIFO L2_Global_Answer_Strobe 31 from Drew's DeMux card Helper_Clock 51 Global Clock net Outputs ------- Name MSA_Out Destination ---- ------- ----------- Input_TRM_Read_Enable(0) 0 P1_TS(13) M122 Bot Input_TRM_Read_Enable(1) 1 P1_TS(13) M123 Mid Send_L2_Decision(0) 2 P1_TS(14) M123 Mid Send_L2_Decision(1) 3 P1_TS(14) M123 Bot L3_Control_Data_Latch_Enable(0) 4 P1_TS(12) M122 Bot L3_Control_Data_Latch_Enable(1) 5 P1_TS(12) M123 Bot L3_Data_Strobe_Inc_Xfr_Number(0) 6 P1_TS(12) M123 Mid L2_Maginot_Line(0) 7 P1_TS(11) M122 Bot L2_Maginot_Line(1) 8 P1_TS(11) M123 Mid L2_Capture_Monitor_Data(0) 9 P1_TS(10) M122 Bot Waiting_for_L2_BAD 10 P1_TS(9) M122 Bot Send_L2_Decision(3) 11 Gated Scaler of L2_Decisions L3_Control_Data_Latch_Enable(2) 12 Patch Box Conn 8 pins 5,6 L3_Data_Strobe_Inc_Xfr_Number(3) 13 Gated Scaler of L2_Accepts L2_Capture_Monitor_Data(4) 14 Patch Box Conn 8 pins 9,10 L2_Answer_TRM_Write_Clock(8) 15 Patch Box Conn 8 pins 11,12 L2_Answer_TRM_Write_Clock(0) 16 M122 B S4 MSA_In(33) L2_Answer_TRM_Write_Clock(1) 17 M122 B S4 MSA_In(49) L2_Answer_TRM_Write_Clock(2) 18 M122 B S4 MSA_In(97) L2_Answer_TRM_Write_Clock(3) 19 M122 B S4 MSA_In(113) L2_Answer_TRM_Write_Clock(4) 20 M122 B S3 MSA_In(33) L2_Answer_TRM_Write_Clock(5) 21 M122 B S3 MSA_In(49) L2_Answer_TRM_Write_Clock(6) 22 M122 B S3 MSA_In(97) L2_Answer_TRM_Write_Clock(7) 23 M122 B S3 MSA_In(113) spare signal 24 Labeled spare in M122 back Send_L2_Decision(2) 25 L1AL2 Scaler "Buffer Depth" Send_L2_Decision_to_SCL 26 SCL Hub Cnt JP2 P5/P6 L3_Data_Strobe_Inc_Xfr_Number(1) 27 Pin 33,34 L3_Xfr_Num L3 Cable L3_Data_Strobe_Inc_Xfr_Number(2) 28 Labeled spare in M122 back L2_Capture_Monitor_Data(1) 29 M123 B S20 P5(0) L2_Capture_Monitor_Data(2) 30 M123 M S18 P5(0) L2_Capture_Monitor_Data(3) 31 M123 M S17 P5(0) L2_Helper Scalers ----------------- The L2 Helper FPGA provides 7 scalers for monitoring the operationg of the L2 Framework. These are all Monitor Data readout only scalers. These scalers are 32 bits long and readout in two adjacent Register Addresses. (1) Number of L2 Framework Cycles Increments once for each L2 Cycle. This counter increments at the point in time when Send L2 Decision signal is asserted. Register Addresses = 20,21 (2) Number of L2 Framework Cycles resulting in issuing L2_Accept to at least one Geographic Section (and thus requiring readout to Level 3). Increments zero or one times for each L2 Cycle. This counter increments when/if the Send_L2_Decision and the Transfer_to_L3_Required signals are both active. Register Addresses = 22,23 (3) Number of L2 Framework Cycles resulting in issuing L2_Reject to all Geographic Sections that were given a L1_Accept for this event, i.e. no readout to Level 3. Increments zero or one times for each L2 Cycle, when Send L2. This counter increments when/if the Send_L2_Decision signal is active and the Transfer_to_L3_Required signal is not asserted. Register Addresses = 24,25 (4) Tick Counter Used for the L2 FW Clock. I ncrements once for every 132 ns tick Register Addresses = 26,27 (5) Number of Ticks Spent in L2 FW Cycles. This begins incrementing when the L1_Spec_Trig_Fired_FIFO_Not_Empty signal goes active and continues incrementing until the L2_Decision has been issued and the 20 usec Cooldown period completed. Register Addresses = 28,29 (6) Number of Ticks Spent Waiting to Distribute the L2_Decision This counter increments once for every tick while the L2 FW is waiting to distribute the L2_Decision. There aretwo things that can block the distribution of a L2_Decision: Waiting for an SCL Frame that can be used to distribute an L2_Decision (the maximum wait for this is 1 tick). Waiting because an L2BAD signal is asserted (i.e. some Geographic Section that, with this L2_Decision, will receive an L2_Accept is currently reporting to the Trigger Framework that it is L2_Busy. This scaler does not distinguish between these 2 reasons for delaying the distribution of the L2_Decision. Register Addresses = 30,31 (7) Number of L2 Framework Cycles for which Issuing the L2_Decision Was Delayed because of an L2_Busy signal. This scaler increments once for each L2 Framework Cycle for which issuing its L2_Decision was delayed because one of the L2BAD cards reported that this L2_Decision will issue an L2_Accept to a Geographic Section that was reporting L2_Busy at the time this L2_Decison was first ready for distribution. Register Addresses = 32,33 These scalers cannot be reset via the "Timing Signal" scaler reset mechanism (because the L2_Helper FM card does not have a configured BSF FPGA and thus does not receive the P1 Scaler Reset Timing Signal). However, Register 3 does provide a mechanism so TCC can reset all 7 of these scalers simultaneously. L2_Helper Programming Interface ------------------------------- The L2 Framework Helper FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 --- Chip Control Status Register (MSW) 3 R/W Force Scaler Reset Register 16 R/W L2_Helper State Engine Control 17 R L2_Helper State Engine Status 18 R/W L2_Helper Additional Control 19 R L2_Helper Input/Output Control Signals Readback 21:20 R L2 Framework Cycle Count Scaler 23:22 R L2 Accept Count Scaler 25:24 R L2 Reject Count Scaler 27:26 R Tick Counter Clock Scaler for L2 Framework 29:28 R Number of Ticks Spent in L2 FW Cycles Scaler 31:30 R Number of Ticks Spent waiting to Issue a L2_Decision 33:32 R Number of L2 FW Cycles that were Delayed by L2 Busy The bit allocation of these registers is given below: Chip Control Status Register LSW Register Address = 0 Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable '1': interrupts enabled 1 R/W Chip Interrupt Request '1': request interrupt 2 R Chip Status Signal (Interrupt Request Status) Logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA 15:3 not allocated readback values are not controlled Chip Control Status Register MSW Register Address = 1 This register is not used and does not exist in this design. Readback values are not controlled. Force Scaler Reset Register Register Address = 3 Bit Access Contents --- ------ -------- 0 R/W Force Reset of L2 Cycle Count Scaler 1 R/W Force Reset of L2 Accept Scaler 2 R/W Force Reset of L2 Reject Scaler 3 R/W Force Reset of Tick Counter Clock Scaler (L2 flavor) 4 R/W Force Reset of Ticks spent in L2 Cycles Scaler 5 R/W Force Reset of Ticks spent waiting to Distribute Scaler 6 R/W Force Reset of Cycles spent delayed by L2 Busy Scaler 14:7 R/W not allocated readback as written 15 R/W Force Reset all L2 FW Scalers simultaneously Assert the bit to force the scaler to reset and hold it in reset. L2_Helper State Engine Control Register Address = 16 Bit Access Contents --- ------ -------- 0 R/W L2 Global Bypass Mode '1': L2 Global Answer not required '0': L2 Global Answer required i.e. each L2 FW Cycle waits for L2_Answer_FIFO_Not_Empty to be asserted 1 R/W Test Mode '1': L2 Framework is in Test Mode '0': L2 Framework is not in Test Mode 2 R/W Test Mode TCC Cycle Approval In Test Mode, TCC must write a 1 to allow each L2 Cycle to proceed and then TCC must write 0 to allow the L2 Cycle to conclude. This bit is not used expect in Test Mode. 3 R/W Immediate Capture Monitor Data TCC writes 0-1-0 to immediately force the L2_Capture_Monitor_Data signal to be asserted for one tick. This forced L2_CMD will be active for only one tick just like the normal Capture Monitor Data signal. This forced L2_CMD is asserted right after the 0-1 transition of this bit in the 0-1-0 sequence. 14:3 R/W not allocated readback as written 15 R/W Force State Engine Reset '1': Force State Engine to Quiescent Mode '0': Do Not Force the State Engine to Quiescent Mode The Definition of the Quiescent Mode is given below in the full description of the Helper Engine. L2_Helper State Engine Status Register Address = 17 This is a read only register that shows what state the Helper_Engine is currently in. See the description below for details about each state. Not all Helper_Engine states are seen in this 16 bit register so you could read this as all zeros. For a state to be visible in this register its must: be one that you could get stuck in, be one that you may or may not want to ever get into depending on the operating mode, be one that results in the assertion of some output control lines. Bit Contents --- -------- 0 Quiescent State 1 Exit Quiescent State in ByPass Mode 2 Wait for TCC Cycle OK 3 Simulate L2 Processing for 80 usec, i.e. simulate waiting for L2 Glb 4 Check L2_Answer_FIFO i.e. wait for the L2_Answer_FIFO_Not_Empty 5 Assert the L2_TRM_Read_Enables 6 Assert the L2_Maginot lines 7 Wait for no Busies and SCL Slot 8 Send L2_Decision 9 Latch L3 Control Data 10 Transport to L3 11 Check if Capture Monitor Data is Required 12 Capture Monitor Data 13 CoolDown for 20 usec i.e. delay at the end of each L2 FW Cycle 14 Wait for TCC OK Removal 15 not used reads low Additional Control Register Address = 18 Bit Access Contents --- ------ -------- 0 R/W L2_Answer_TRM_Write_Clock Source '1': Controlled by TCC, see bit 1 in this register '0': Comes from the L2_Answer_Strobe from L2 Global 1 R/W L2_Answer_TRM_Write_Clock TCC Control When bit 0 of this reg is 1, then this bit can be used by TCC to generate a L2_Answer_TRM_Write_Clock pulse. When TCC write a 0-1-0 patter to this bit a sigle tick wide pulse of L2_Answer_TRM_Write_Clock will be generated. Details about the L2_Answer_TRM_Write_Clock are presented below. 15:2 R/W not allocated readback as written L2_Helper Input/Output Control Signals Readback Register Address = 19 This is a read only register that shows all the input and output control lines involved with the L2_Helper card. Most of these signal are to/from the Helper Engine and are further described below. Bit Contents --- -------- 0 L1_ST_Fired_FIFO_Not_Empty Input Signal 1 L2_Answer_FIFO_Not_Empty Input Signal 2 Available_L2_Slot Input Signal 3 L2 BAD, OR of the output of the 2 L2BAD cards Input Signal 4 Transfer_to_L3_Required Input Signal 5 Capture_Monitor_Data_Request Input Signal 6 L2_Global_Answer_Strobe Input Signal 7 L2_Cycle_Envelope Output Signal 8 Input_TRM_Read_Enable Output Signal 9 L2_Maginot_Line Output Signal 10 Waiting_for_L2BAD from Helper Engine Output Signal 11 Send_L2_Decision Output Signal 12 L3_Control_Data_Latch_Enable Output Signal 13 L3_Strobe_Increment_L3_Transfer_Number Output Signal 14 L2_Capture_Monitor_Data from Helper Engine Output Signal 15 L2_Answer_TRM_Write_Clock from L2_Helper card Output Signal The following is a functional description of the L2_Helper_Engine as implemented in logic January 2002. This is the 4-Feb-2002 version of the L2_Helper_Engine. Signals to/from the L2_Helper_Engine Inputs: stf_fifo_not_empty ans_fifo_not_empty available_l2_slot l2_bad xfr_to_l3_required cap_monit_data_request l2_global_bypass_mode test_mode ttc_cycle_ok force_reset l2_helper_clock Outputs: l2_cycle_envelope input_trm_read_enable l2_maginot_line waiting_for_l2bad send_l2_decision l3_cont_data_latch_enb l3_strobe_inc_xfr_num l2_cap_monit_data States: quiescent_state quiscent_exit_test_mode_state quiscent_exit_bypass_mode_state wait_for_tcc_cycle_ok_state wait_for_tcc_cycle_ok_exit_state sim_l2_processing_state check_l2_answer_fifo_state assert_trm_read_enable_state l2_fw_process_1_state l2_fw_process_2_state assert_l2_maginot_line_state wait_for_no_busies_and_slot_state send_l2_decision_state latch_l3_control_signals_state control_to_l3_settle_1_state control_to_l3_settle_2_state check_if_trans_to_l3_required_state transport_to_l3_state check_if_cmd_required_state capture_monitor_data_state cooldown_state cooldown_exit_state wait_for_tcc_ok_removal_state State Engine Description ------------------------ Rules: Only one state is active at any point in time. All output lines that are not explicitly called out as asserted are at their negated level. Force_Reset forces you to the quiescent_state and resets counters The control signal outputs go through a FF to deglitch them so they are one clock edge behind the state outputs. Notice: l2_global_bypass_mode only means that you will skip checking for ans_fifo_not_empty and that you do a 80 usec wait instead of waiting for the ans_fifo_not_empty from L2 Global. test_mode only means that TCC must give the OK for each L2 FW cycle to start. - quiescent_state arrive here from: cooldown_exit_state only if test_mode input is negated or from: wait_for_tcc_ok_removal_state only if tcc_cycle_ok input is negated or from: force_reset during this state assert: - this state persists until input stf_fifo_not_empty is asserted and then the next state is: quiescent_exit_test_mode_state - quiescent_exit_test_mode_state arrive here from: quiescent_state only once stf_fifo_not_empty input is asserted during this state assert: l2_cycle_envelope this state persists for just one tick and then if input test_mode is asserted then the next state is: wait_for_tcc_cycle_ok_state else the next state is: quiscent_exit_bypass_mode_state - quiescent_exit_bypass_mode_state arrive here from: quiescent_exit_test_mode_state only if test_mode input is negated during this state assert: l2_cycle_envelope this state persists for just one tick and then if input l2_global_bypass_mode is asserted then the next state is: sim_l2_processing_state else the next state is: check_l2_answer_fifo_state - wait_for_tcc_cycle_ok_state arrive here from: quiescent_exit_test_mode_state only if test_mode input is asserted during this state assert: l2_cycle_envelope this state persists until tcc_cycle_ok is asserted and then the next state is: wait_for_tcc_cycle_ok_exit_state - wait_for_tcc_cycle_ok_exit_state arrive here from: wait_for_tcc_cycle_ok_state only once tcc_cycle_ok input is asserted during this state assert: l2_cycle_envelope this state persists for just one tick and then if input l2_global_bypass_mode is asserted then the next state is: sim_l2_processing_state else the next state is: check_l2_answer_fifo_state - sim_l2_processing_state arrive here from: quiescent_exit_bypass_mode_state only if l2_global_bypass_mode input is asserted or from: wait_for_tcc_cycle_ok_exit_state only if l2_global_bypass_mode input is asserted during this state assert: l2_cycle_envelope this state persists for 80 usec i.e. for 607 ticks and then the next state is: assert_trm_read_enable_state - check_l2_answer_fifo_state arrive here from: quiescent_exit_bypass_mode_state only if l2_global_bypass_mode input is negated or from: wait_for_tcc_cycle_ok_exit_state only if l2_global_bypass_mode input is negatted during this state assert: l2_cycle_envelope this state persists until ans_fifo_not_empty is asserted and then the next state is: assert_trm_read_enable_state - assert_trm_read_enable_state arrive here from: sim_l2_processing_state only once sim_l2_processing_counter reaches TC or from: check_l2_answer_fifo_state only once ans_fifo_not_empty input is asserted during this state assert: l2_cycle_envelope and assert: input_trm_read_enable this state persists for just one tick and then the next state is: l2_fw_process_1_state - l2_fw_process_1_state arrive here from: assert_trm_read_enable_state during this state assert: l2_cycle_envelope this state persists for just one tick and then the next state is: l2_fw_process_2_state - l2_fw_process_2_state arrive here from: l2_fw_process_1_state during this state assert: l2_cycle_envelope this state persists for just one tick and then the next state is: assert_l2_maginot_line_state - assert_l2_maginot_line_state arrive here from: l2_fw_process_2_state during this state assert: l2_cycle_envelope and assert: l2_maginot_line this state persists for just one tick and then the next state is: wait_for_no_busies_and_slot_state - wait_for_no_busies_and_slot_state arrive here from: assert_l2_maginot_line_state during this state assert: l2_cycle_envelope and assert: waiting_for_l2bad this state persists until: available_l2_slot input is asserted AND l2_bad input is negated then the next state is: send_l2_decision_state - send_l2_decision_state arrive here from: wait_for_no_busies_and_slot_state only once available_l2_slot input is asserted AND l2_bad input is negated during this state assert: l2_cycle_envelope and assert: send_l2_decision this state persists for just one tick and then the next state is: latch_l3_control_signals_state - latch_l3_control_signals_state arrive here from: send_l2_decision_state during this state assert: l2_cycle_envelope and assert: l3_cont_data_latch_enb this state persists for just one tick and then the next state is: control_to_l3_settle_1_state - control_to_l3_settle_1_state arrive here from: latch_l3_control_signals_state during this state assert: l2_cycle_envelope this state persists for just one tick and then the next state is: control_to_l3_settle_2_state - control_to_l3_settle_2_state arrive here from: control_to_l3_settle_1_state during this state assert: l2_cycle_envelope this state persists for just one tick and then the next state is: check_if_trans_to_l3_required_state - check_if_trans_to_l3_required_state arrive here from: control_to_l3_settle_2_state during this state assert: l2_cycle_envelope this state persists for just one tick and then if input xfr_to_l3_required is asserted then the next state is: transport_to_l3_state else the next state is: check_if_cmd_required_state - transport_to_l3_state arrive here from: check_if_trans_to_l3_required_state only if xfr_to_l3_required input is asserted during this state assert: l2_cycle_envelope and assert: l3_strobe_inc_xfr_num this state persists for just one tick and then the next state is: check_if_cmd_required_state - check_if_cmd_required_state arrive here from: check_if_trans_to_l3_required_state only if xfr_to_l3_required input is negated or from: transport_to_l3_state during this state assert: l2_cycle_envelope this state persists for just one tick and then if input cap_monit_data_request is asserted then the next state is: capture_monitor_data_state else the next state is: cooldown_state - capture_monitor_data_state arrive here from: check_if_cmd_required_state only if cap_monit_data_request input is asserted during this state assert: l2_cycle_envelope and assert: l2_cap_monit_data this state persists for just one tick and then the next state is: cooldown_state - cooldown_state arrive here from: check_if_cmd_required_state only if cap_monit_data_request input is negated or from: capture_monitor_data_state during this state assert: l2_cycle_envelope this state persists for 20 usec i.e. for 152 ticks and then the next state is: cooldown_exit_state - cooldown_exit_state arrive here from: cooldown_state only once cooldown_counter reaches TC during this state assert: l2_cycle_envelope this state persists for just one tick and then if input test_mode is asserted then the next state is: wait_for_tcc_ok_removal_state else the next state is: quiescent_state - wait_for_tcc_ok_removal_state arrive here from: cooldown_exit_state only if test_mode input is asserted during this state assert: - this state persists until input ttc_cycle_ok is negated and then the next state is: quiescent_state This ends the list of states in L2_Helper_Engine. The following is a description of a couple of the less obvious control signals used in the L2 Framework L2 Maginot Line ----------------- What is called "L2_Maginot_Line" i.e. MSA_Out_7 and MSA_Out_8, is connected to P1_TS_11 in M122B and M123M. In the L1 Spec Trig Fired Mask to L2_TRM, the L2 Glb Answer L2_TRM, the Aux Data L2_TRM, the L2_AONM's and the L2_FOM'a P1_TS_11 is mapped to HQ_1 in their BSF's. The HQ_1 signal is used to: enable one clock of their BX_History_Shift_Registers, and possibly one increment of their scalers, and in the case of the TRM's it enables their FIFO Read pointer to increment. Note that besides "L2_Maginot_Line" being a very bad name, using this signal to increment the FIFO Read Pointer seems very strange. Need to understand how all this works with the L2_TRM. L2_TRM FIFO Pointer Control ----------------------------- The signal generated by L2_Helper that is called "Input TRM Read Enable" comes out of L2_Helper on MSA_Out_0 and MSA_Out_1. These signals are routed to P1_TS_13 in M122B and M123M where they are used by the L2_TRM's as HQ_2. In the L2_TRM's HQ_2 is used only to enable their output latch to update - that's all. OK, looking at the current (MAY-2000) L2_Helper code you see that it waits for the L2_TRM FIFO NOT Empty signals then it asserts Input_TRM_Read_Enable for 1 tick then it waits two ticks then it asserts L2_Maginot_Line for 1 tick then it check for L2 Busies and SCL slot and advertises the decision. So during L2 FW cycle "N" the TRM FIFO Read Pointer is pushed forward to get it pointing at the FIFOed TRM data for L2 cycle "N+1". Input_TRM_Read_Enable just updates the TRM output latch. All of this strange setup must come from L2_TRM being strongly derived from L1_TRM. So for now need to understand how the L2 TRM FIFO control logic works. Is it setup in a way that we can live with it ? After a reset the read and write pointers start out equal. This is and Empty condition but not an error. A write, writes to the current address and then increments the write pointer. An Input_TRM_Read_Enable reads from the current address and latches this data in the output latch (and then L2_Maginot line increments the read pointer). So this all appears to work OK. Getting the FIFO Not Empty signal to the front panel P5 connector is another strange topic but this is covered in the L2_TRM description. L2_Answer_TRM_Write_Clock --------------------------- This signal causes a new entry to be written into the L2 Answer TRM FIFO. This signal is an output from the L2_Helper card. There are two sources for this signal. TCC can generate this signal for special testing or for normal operation this signal is derived from the L2_Answer_Strobe signal that comes from Drew's L2 Answer DeMux card. The source for the L2_Answer_TRM_Write_Clock is controlled by register 18. When this signal is sourced by TCC, register 18 allows TCC to control the state of this signal. The L2_Answer_Strobe from Drew's DeMux card is described in the 16:18-JAN-2002 log Book entry. It is 430 nsec long and starts 75 nsec after the final transitions of the L2 Answer lines. Because this signal is long we can use the L2_Helper to "filter" it and to generate the L2_Answer_TRM_Write_Clock off of the falling trailing edge of L2_Answer_Strobe. Using the trailing edge gives additional setup time in the L2_Answer_TRM's. So when the L2_Answer_Strobe is selected as the source of L2_Answer_TRM_Write_Clock then this clock is generated for a single 132 nsec tick soon after the falling edge of L2_Answer_Strobe. When TCC is used as the source of L2_Answer_TRM_Write_Clock it should write a 0-1-0 pattern and the L2_Answer_TRM_Write_Clock signal will be generate for a single 132 nsec tick soon after the 0-1 transition. The following is an ascii drawing of the L2 FW control flow ----------------------------------------------------------- This drawing is still being brough up to data 4-FEB-2002 1. Quiescent, Waiting for L1 Spec Trig Fired Mask FIFO Not Empty Normal Mode ByPass Mode | | V \ ------------ 2. Wait for Answer from L2, i.e. \ Wait for L2 Answer FIFO Not Empty | | Receive Timeout Waiting | L2 Answer for L2 Answer V | | 2B. Simulate L2 | V Processing | Delay, Wait | 2A. Advertize that State #2 80 usec. | Timed Out. Continue waiting | until you get an Answer from L2 | | | | | ____________________/ | | / V V V 3. Assert the L2 FW Input TRM Read Enables | V 4. Wait 3 ticks for L2 FW Input Data from the TRM's to settle. | V 5. Wait for no L2 Busy - L2 Accept conflicts and for a Serial Command Link frame that can be used to distribute this L2 Decision. All conditions meant Timeout Waiting for all the conditions to be meant | | | | V | | 5A. Advertize that State 5 | Timed Out. Continue waiting | until all conditions are meant | | | V V 6. Assert the Send L2 Decision signal for 1 tick (and its Helper Clk latched version, Distributing L2 Decision) | V 7. Assert the L3 Control Data Latch Enable signal for 1 tick | V 8. Wait 3 ticks for the L3 Control Data to settle Send to L3 Required Send to L3 Required IS asserted is NOT asserted | | V \ | 9. Assert the L3 Control Data Strobe & | Increment L3 Transfer Number signal | for 1 tick. | | | _____________/ | / V V 10. Check to see if a L2 FW Capture Monitor Data signal is to be issued for this L2 FW Cycle. Yes, Capture Monitor Data Do Not Issue Capture Mon Data | | V | | 11. Assert, for 1 tick, the L2 FW | Capture Monitor Data signal | | | __________/ | / V V 12. To guarantee a min time between distributing succissive L2 Decision, wait 20 usec before returning to State #1 at the top of this flow control sequence. | V To Step #1 ========================================================================== Signals to/from the Timing Signal Generator Inputs: Write_Reg(3:0) Read_Reg(3:0) Read_Data(15:0) Write_Data(15:0) L2_Ans_FIFO_Not_Empty L1_STF_FIFO_Not_Empty Available_L2_Slot L2_BAD(1:0) Transfer_to_L3_Required Cap_Monit_Data_Request L2_Global_Answer_Strobe L2_Helper_Clock Outputs: L2_Cycle_Envelope Input_TRM_Read_Enable Waiting_for_L2BAD Send_L2_Decision L3_Cont_Data_Latch_Enable L3_Strobe_Inc_Xfr_num L2_Maginot_Line L2_Capture_Monitor_Data L2_Answer_TRM_Write_Clock