SCL Helper Functions FPGA --------------------------- Original: 7-SEP-1999 Revised: 6-APR-2000 Introduction ------------ The L1 Framework uses the SCL Helper Function FPGA to manage the single signals it sends to the SCL. This FPGA performs several functions: 1. Latches these single signals 2. Also copies these single signals, with a different delay value, for use as And-Or Input Terms 3. Provides an interface for TCC to monitor and control signals associated with SCL Initialize The SCL Helper Function FPGA (SCL_Helper) operates as follows: 1. Carmen Master Clock Signals sent to Serial Command Link The SCL Helper receives the following 5 Carmen Master Clock signals, which it sends to the SCL as Markers: Signal Name MSA_Input MSA_Output ----------- --------- ---------- Beginning of Turn 93 32 Live Crossing 91 33 Sync Gap 119 34 Cosmic Gap 121 35 Spare Marker 117 36 The signals are delayed by 2 ticks of the SCL_Helper_Clock (which enters on MSA_Input(95)). This delay is driven by the latency of the Tick and Turn Scaler, which sets its output to Tick 1 two ticks after seeing the Beginning of Turn marker. Rather than generating two different Beginning of Turn markers (one for the TTS and one for the SCL), we only generate one and delay the copy sent to the SCL. All other signals are delayed by the same amount simply to keep the SCL_Helper processing constant across channels. 2. TCC Control and Monitoring of Serial Command Link: TCC sends 1 signal to the SCL: Signal Name MSA_Output ----------- ---------- SCL Initialize 41 The SCL Helper makes a second copy of this signal also: Signal Name MSA_Output ----------- ---------- SCL Initialize Spare Copy 47 This signal is based on a control register set by TCC, but is only allowed to update at a particular point in the turn cycle (currently, 30 ticks after the Beginning of Turn Marker). TCC receives 3 signals from the SCL: Signal Name MSA_Input ----------- --------- Initialize Acknowledge 101 SCL_GB_SynErr 102 IRQ 103 These signals appear in a status register, visible to TCC. 3. Signals sent to the L1 Framework as And-Or Input Terms Currently, all of the Carmen Master Clock generated Markers are sent to the L1 Framework as And-Or Input Terms (as well as sent to the SCL). These signals are delayed by 25 ticks of the SCL Helper Clock, to bring them into the Framework Time Zone (recall that they are generated in the Front-End Time Zone). These signals are sent as follows: Signal Name MSA_Output ----------- ---------- Beginning of Turn 48 Live Crossing 49 Sync Gap 50 Cosmic Gap 51 Spare Marker 52 These signals are updated on the FALLING edge of SCL Helper Clock. This is synchronous with the rising edge of TRM Clock as seen in the TRM MSA FPGA's (recall that the BSF delays the P1 Timing Signals by 2 buckets). Thus they get essentially a full 132 ns setup time prior to the TRM Clock (we count on causality to guarantee that they are not ingested by the TRM during the tick that they are produced by the SCL Helper). Calculation of 25 tick delay: If these signals are presented to the SCL Hub End to be distributed for Front-End Tick 1, they must be ingested into the L1 FW as AOIT's for Front-End Tick 1 (i.e. during FW Tick 1, which is the same as Front-End Tick 25). This means that they must be produced by the SCL Helper in Front-End Tick 24, i.e. delayed by 23 ticks with respect to the copy send to the SCL Hub End. Recall that this copy is delayed by 2 ticks from the incoming Carmen Master Clock signal. Therefore the appropriate delay from CMC input to AOIT output here is 23+2 = 25 ticks. Programming Interface --------------------- The SCL Helper FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 --- Chip Control Status Register (MSW) 8 R/W SCL Control 9 R SCL Status The bit allocation of these registers is given below: Chip Control Status Register LSW Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 15:3 --- not allocated The Chip Control Status Register MSW is not used/allocated. SCL Control Bit Access Contents --- ------ -------- 0 R/W SCL Initialize to Hub End ('1': SCL Initialize to Hub End ACTIVE '0': SCL Initialize to Hub End CLEARED) 15:1 R/W unallocated SCL Status Bit Access Contents --- ------ -------- 0 R SCL GB Sync Error ('1': error asserted) 1 R SCL IRQ ('1': IRQ asserted) 2 R SCL Initialize Acknowledge ('1': Initialize Acknowledge asserted) 15:3 R unallocated