P1 5 Row VME Backplane ----------------------------- Original Ver. 27-FEB-1996 Latest Ver. 18-SEP-1996 Description - Definition of the 5RP1 ------------------------------------ 1. This backplane is 21 slots long of normal 3U EuroCard format. The slots are numbered: slot #1 through slot #21. 2. This backplane provides ALL normal P1 VME signals. 3. This backplane does NOT have connections for external: SysReset, ACFail, and SysFail signals. These signals are bused on the backplane. These VME signals, if used, will be provided by the TOM or RAY cards. 4. This backplane does NOT provide "on board" VME Terminators. The VME terminators will be provided by either the TOM and RAY cards. 5. This backplane provides good strong Ground and +5V VME power distribution. This backplane provides only mild (5 Amp ) VME power distribution on +12V, -12V, and on +5V STDBY. . 6. This backplane provides big time extra Ground distribution to the P1 5 row connector. 7. This backplane provides a mild amount (e.g. 5 Amps) of -4.5V and -2V power distribution on the 5 row connector, e.g. two pins of each. 8. All power and ground connections are made to this backplane via 21 of the 10-Point power tabs. All 21 of these 10-Points are arranged along the lower edge of the circuit board. These are arranged in the following way: Slot #1 End 10-Point #1 GND 10-Point #2 -12V 10-Point #3 +5V 10-Point #4 GND 10-Point #5 +5V 10-Point #6 GND 10-Point #7 -4.5V 10-Point #8 GND 10-Point #9 +5V 10-Point #10 GND 10-Point #11 +5V STDBY 10-Point #12 GND 10-Point #13 +5V 10-Point #14 GND 10-Point #15 -2V 10-Point #16 GND 10-Point #17 +5V 10-Point #18 GND 10-Point #19 +5V 10-Point #20 +12V 10-Point #21 GND Slot #21 End This gives: 10 connections for GND 6 connections for +5V 1 connection each for +12V, +5VSDTBY, -2V, -4.5V, and -12V 9. The 5RP1 will use the same ten point connectors as were used on the P2-P3 backplane. Questions about 5RP1 -------------------- 1. Use of PCB Layers ----------------- The 5RP1 backplane is a 13 layer board. The layers are numbered 1 through 13 with layer number 1 being at the component side of the board. Different use is made of the layers depending upon whether you are looking at the: top edge, the central connector and trace section, or the bottom edge of the card. Ten Point Power Tap Above Timing TTL VME and Power Layer the Signals Row Signals Row Connections Number Connector Rows 1:9 10 Rows 11:29 30 Rows 31:32 ------ --------- ----------- ----- ----------- ----- ----------- 1 Gnd Gnd Gnd Gnd Gnd Gnd 2 Gnd A Even Gnd Gnd Gnd +12V 3 Gnd B Even Gnd Signal A Gnd -12V 4 Gnd Gnd Gnd Gnd Gnd Gnd 5 Gnd A Odd Gnd Signal B Gnd +5V 6 Gnd B Odd Gnd Gnd Gnd Gnd 7 Gnd Gnd Gnd Signal C Gnd +5V Stby 8 Gnd D Even Gnd Gnd Gnd Gnd 9 Gnd E Even Gnd Signal D Gnd +5V 10 Gnd Gnd Gnd Gnd Gnd Gnd 11 Gnd D Odd Gnd Signal E Gnd -4.5V 12 Gnd E Odd Gnd Gnd Gnd -2.0V 13 Gnd Gnd Gnd Gnd Gnd Gnd Trace widths: ------------- 1. All VME TTL traces are 0.010" or 0.012" in width. 2. All Differential ECL Traces are 0.010" or 0.012" in width. 3. Guard traces are NOT used in the TTL VME section as in some VME backplanes. Hole Sizes: ----------- DESCRIPTION OF THE DRILL FILES --------------------------------- DRILL FILE NUMBER FUNCTION ----------------- -------------------------- DRILL FILE #1 These are the holes for mounting this board to the cardfile mechanics and for mounting the connector shrouds to the board. The finished size of these holes is 0.106" diameter. These holes are NOT plated. There are ?? of these holes. DRILL FILE #3 These are the holes for connector press fit pins and other vias. The finished size after plating of these holes is 0.039" with a tolerance of + 0.003" / - 0.002" in diameter. All of these holes have pads on both sides of the board and ARE plated in the tunnel. There are ?,??? of these holes. -------------------------------------------------- ALL HOLE DIAMETERS ARE GIVEN AS THE FINISHED SIZE. -------------------------------------------------- >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< What will the DC voltage drop on the traces be: The traces are 16" long and made from 1oz Cu. This gives: Trace Resistance Resistance Voltage Drop Width per Foot per 16 inches with 50 mA Current ------- ------------ --------------- -------------------- 10 mil 0.593 Ohm 0.791 Ohm 40 mV 12 mil 0.494 Ohm 0.659 Ohm 33 mV The capacitance will be about 100 pF. So a question is, "What current must flow for the duration of a normal switching period in order to charge the trace capacitance to the level of a normal logic swing". Well let's pick a 3 Volt swing and a 5 nsec switching period and assume that the trace's capacitance to Gnd is 100 pF. This will require a 60 mA current to flow in order to charge the trace 3 Volts. >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< 5 Row VME Layout -------------------- Rev. 1-MAR-1996 The following is the layout that is used in P1 of all Run II Framework VME Crates. In addition to the normal VME signals, this 5 Row VME layout caries 16 differential ECL timing signals and additional power supplies: -2V and -4.5V. The 5 row layout of the VME signals themselves is arrived at by close packing the normal 3 row layout into the 5 row connector used in this P1 backplane. This is shown in the following table: 3 Row Layout 5 Row Layout -------------- -------------- Row Pin Row Pin ----- ----- ----- ----- 1 A - 11 A 1 B - 11 B 1 C - 11 C 2 A - 11 D 2 B - 11 E 2 C - 12 A 3 A - 12 B 3 B - 12 C . . . . . . . . The only exceptions to this straight forward packing of the VME signals into a 5 row connector are explained in the following paragraphs. The 8 GND pins in the normal 3 row VME layout were allowed to move around in order to give good protection to the signals that we care about. 5 additional GND pins were added in the array of VME signals to give better "important" signal protection and overall GND layout. The only signal pin order that was changed in moving from 3 row to 5 row was the relative order of AS* and Adrs_21. Signals that had been protected by GND in the normal 3 row VME layout and are not protected in this layout are: SYSCLK, SERCLK, and SERDATA. SYSCLK in this layout actually has GND just below it. BBSY* which is not protected in the normal 3 row layout has wall-o-GND just above it in this layout. The signals that we care about have the following protection: ACFAIL* has GND left and right, Data_01 and Data_11 on top and bottom. DS1* has GND left, right and bottom, BG3IN* on top. SYSRST* has GND left, right, top, and bottom. DS0* has GND left, top, and bottom connector edge is on the right. WRITE* has GND left, top, and right, BR3* is on the bottom DTACK* has GND left, right, top, and bottom. AS* has GND left, top, and right, AM3* is on the bottom Pins Signal Function ------------------------------------------------------------------- Pin Row Row Row Row Row Number A B C D E ------ ----------- ----------- ----------- ----------- ----------- 1 TS_00_Inv TS_00_NonInv GND TS_08_Inv TS_08_NonInv 2 GND GND GND GND GND 3 TS_01_Inv TS_01_NonInv GND TS_09_Inv TS_09_NonInv 4 TS_02_Inv TS_02_NonInv GND TS_10_Inv TS_10_NonInv 5 TS_03_Inv TS_03_NonInv GND TS_11_Inv TS_11_NonInv 6 TS_04_Inv TS_04_NonInv GND TS_12_Inv TS_12_NonInv 7 TS_05_Inv TS_05_NonInv GND TS_13_Inv TS_13_NonInv 8 TS_06_Inv TS_06_NonInv GND TS_14_Inv TS_14_NonInv 9 TS_07_Inv TS_07_NonInv GND TS_15_Inv TS_15_NonInv 10 GND GND GND GND GND 11 Data_00 BBSY* Data_08 Data_01 BCLR* 12 Data_09 Data_02 GND ACFAIL* GND 13 Data_10 Data_03 BG0IN* Data_11 Data_04 14 BG0OUT* Data_12 Data_05 BG1IN* Data_13 15 Data_06 BG1OUT* Data_14 Data_07 BG2IN* 16 Data_15 BG2OUT* SYSCLK BG3IN* SYSFAIL* 17 BG3OUT* BERR* GND DS1* GND 18 BR0* GND SYSRESET* GND DS0* 19 BR1* LWORD* GND WRITE* GND 20 BR2* GND AM5 BR3* Adrs_23 21 GND DTACK* GND AM0 Adrs_22 22 AM1 GND AS* GND Adrs_21 23 AM2 Adrs_20 AM3 Adrs_19 IACK* 24 Adrs_18 IACKIN* SERCLK Adrs_17 IACKOUT* 25 SERDAT* Adrs_16 AM4 Adrs_15 Adrs_07 26 IRQ7* Adrs_14 Adrs_06 IRQ6* Adrs_13 27 Adrs_05 IRQ5* Adrs_12 Adrs_04 IRQ4* 28 Adrs_11 Adrs_03 IRQ3* Adrs_10 Adrs_02 29 IRQ2* Adrs_09 Adrs_01 IRQ1* Adrs_08 30 GND GND GND GND GND 31 -2V -12V +5V STDBY +12V -4.5V 32 -2V +5V +5V +5V -4.5V ------ ----------- ----------- ----------- ----------- ----------- Pin A B C D E Number Row Row Row Row Row >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< The following is standard 3 row VME pinout Data_00 _BBSY*_ Data_08 Data_01 _BCLR*_ Data_09 Data_02 ACFAIL* Data_10 Data_03 BG0IN*_ Data_11 Data_04 BG0OUT* Data_12 Data_05 BG1IN*_ Data_13 Data_06 BG1OUT* Data_14 Data_07 BG2IN*_ Data_15 __GND__ BG2OUT* __GND__ SYSCLK_ BG3IN*_ SYSFAL* __GND__ BG3OUT* BERR*__ _DS1*__ _BR0*__ SYSRST* _DS0*__ _BR1*__ LWORD*_ WRITE*_ _BR2*__ __AM5__ __GND__ _BR3*__ Adrs_23 DTACK*_ __AM0__ Adrs_22 __GND__ __AM1__ Adrs_21 __AS*__ __AM2__ Adrs_20 __GND__ __AM3__ Adrs_19 _IACK*_ __GND__ Adrs_18 IACKIN* SERCLK_ Adrs_17 IAKOUT* SERDAT* Adrs_16 __AM4__ __GND__ Adrs_15 Adrs_07 _IRQ7*_ Adrs_14 Adrs_06 _IRQ6*_ Adrs_13 Adrs_05 _IRQ5*_ Adrs_12 Adrs_04 _IRQ4*_ Adrs_11 Adrs_03 _IRQ3*_ Adrs_10 Adrs_02 _IRQ2*_ Adrs_09 Adrs_01 _IRQ1*_ Adrs_08 _-12V__ +5STDBY _+12V__ __+5V__ __+5V__ __+5V__ The following is the straight change from standard 3 row VME to 5 row VME. Data_00 _BBSY*_ Data_08 Data_01 _BCLR*_ Data_09 Data_02 ACFAIL* Data_10 Data_03 BG0IN*_ Data_11 Data_04 BG0OUT* Data_12 Data_05 BG1IN*_ Data_13 Data_06 BG1OUT* Data_14 Data_07 BG2IN*_ Data_15 __GND__ BG2OUT* __GND__ SYSCLK_ BG3IN*_ SYSFAL* __GND__ BG3OUT* BERR*__ _DS1*__ _BR0*__ SYSRST* _DS0*__ _BR1*__ LWORD*_ WRITE*_ _BR2*__ __AM5__ __GND__ _BR3*__ Adrs_23 DTACK*_ __AM0__ Adrs_22 __GND__ __AM1__ Adrs_21 __AS*__ __AM2__ Adrs_20 __GND__ __AM3__ Adrs_19 _IACK*_ __GND__ Adrs_18 IACKIN* SERCLK_ Adrs_17 IAKOUT* SERDAT* Adrs_16 __AM4__ __GND__ Adrs_15 Adrs_07 _IRQ7*_ Adrs_14 Adrs_06 _IRQ6*_ Adrs_13 Adrs_05 _IRQ5*_ Adrs_12 Adrs_04 _IRQ4*_ Adrs_11 Adrs_03 _IRQ3*_ Adrs_10 Adrs_02 _IRQ2*_ Adrs_09 Adrs_01 _IRQ1*_ Adrs_08 >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< The following are old sections of text that were generated during the process of defining the P1 5 Row Backplane. These sections of text are no longer directly part of the P1 5 Row Backplane description. New P1 Now ? Review and Decision -------------------------------------- Original Rev. 25-JAN-1996 Latest Rev. 25-JAN-1996 First we look ONLY at what the differences are in terms of how much work do we have to do, i.e. custom design vs commercial purchase. We have two options: Commercial 3 Row P1 Backplane Custom 5 Row P1 Backplane ------------------------------- --------------------------- Use a commercial P1 backplane Design a custom 5 row P1 with normal 3 row connectors. backplane. Use a commercial 60mm P1 | | extender to plug in normal | | VME cards. 3 row <-> 3 row | | Design a custom P1-P2 60mm +--+ extender to use with normal Design a custom 60mm P2 | | VME cards. 3 row <-> 5 row extender to plug in normal | | VME cards. 3 row <-> 5 row | | Design fancy geometry TOM and Design simple geometry TOM and RAY cards that connect to RAY cards that plug into only P1. P1-P2-P3. Design THE card with a 3 row Design THE card with a 5 row P1 connector. connector. Now we look ONLY at the relative advantages and disadvantages of the two possible choices in terms of electrical characteristics, cable routing, flexibility, long term support, quality of finished product, technical risk, ADVANTAGES ---------- 1. We could have 16 pure clean timing signals distributed to the application cards. 2. TOM and RAY can become simple geometry P1 only back of the backplane cards instead of the fancy geometry P1-P2-P3 cards that are required now. The new P1 would have to distribute a little -2V and -4.5V to power the 100k ECL on TOM and RAY. 3. Having simple P1 only TOM and RAY cards will simplify the signal cabling and power cabling on P2-P3. 4. This solution is "guaranteed" to work. It will take a little longer to build but we will have a better finished product. We will not get stuck 6 months from now realizing that the timing distribution does not work and needing to design some kind of band-aid fix. 5. The work to date testing timing distribution on the VME TTL lines by no means looks super encouraging. We clearly can see the VME TTL activity clobber the ECL timing signals running on VME traces timing distribution. 6. We need "guaranteed" perfect timing distribution. If on one in 1,000,000 cyles we have a 30 nsec jitter on some timing signal edge we will never be able to find the problem or to fix it, but it would corrupt trigger decisions at a 7 Hz rate. 7. Up until now, the life boat to get us out of a timing signal distribution problem 6 months from now was to make a custom many layer 3 row P1 backplane that had special isolated routing for the VME signal traces that we use for our timing signals. This is still not "guaranteed" to work just because our timing signals pass through the backplane right in the middle of a pile of TTL signal pins. A custom 5 row P1 backplane gives us our own signal traces for our timing signals and isolates them from the TTL VME stuff. 8. We get full standard P1 VME functionality. 9. Prevents the worst case scenario of commercial P1 not working and them custom 3 row P1 backplane not working. 10. Eliminates the possibility of needing to rework THE Card 6 months from no to retrofit a 5 row P1 connector DIS-ADVANTAGES ? ------ Why are we building a P1 VME BAckplane ? 1. We want to distribute accurate high speed timing information on the P1 connector and stealing VME TTL bus lines does not appear to provide a workable solution. 2. Making a good P1 bus with good grounds and power distribution will allow us to make the TOM and RAY cards connect to only P1. This eliminates the power and signal cabling problems caused by TOM and RAY cards that connect to both P1 and P2-P3. 3. Making the 5 row P1 now allows us to build all of THE Cards in a way that we know will work. This eliminates the worst case scenario of building THE Cards with 3 row P1 and never being able to make the high speed timing distribution work over a 3 row P1; not even over a custom 3 row P1. 4. >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< P1 5 Row VME Backplane SECOND TRY i.e. Rev. B -----------------------------==========------------===-- Original Ver. 20-JAN-1997 Latest Ver. 30-JAN-1997 OK, the first version of the 5 Row P1, of which we received 20 on 28-OCT-1996, have the almost fatal problem of their Bus Grant In-Out lines and their Interrupt Acknowledge lines being run as bussed lines instead of Daisy-Chain lines. It may be possible to "fix" this by "blowing up" the internal traces that make these connections, but for reasons of rationality, we are going to make another set of cards. Said in words the wiring should be the following: Bus Grant OUT from slot N goes to Bus Grant IN at slot N+1 Bus Grant IN at slot #1 is an open circuit Bus Grant OUT from slot #21 is an open circuit IACK OUT from slot N goes to IACK IN at slot N+1 IACK IN at slot #1 is connected to IACK IACK OUT from slot #21 is an open circuit Pin Number locations of the signals that will have to be fixed: Signal 3 Row P1 5 Row P1 Name Location Location ---------- -------- -------- BG0IN* B4 C13 BG0OUT* B5 A14 BG1IN* B6 D14 BG1OUT* B7 B15 BG2IN* B8 E15 BG2OUT* B9 B16 BG3IN* B10 D16 BG3OUT* B11 A17 IACK* A20 E23 IACKIN* A21 B24 IACKOUT* A22 E24 Now look at the routing channels available and we find the following: Signal_Layer What Can We Route There ------------ ----------------------------------------------------- Signal_2 1/2 of BG1 Signal_5 1/2 of BG3, and 1/2 of BG2 or else All of BG3 Signal_11 All of BG0 Signal_4 1/2 of BG3, and 1/2 of BG1 Signal_7 All of the IACK stuff, and 1/2 of BG2 What will we route where: Signal_Layer What We Will Route There ------------ ----------------------------------------------------- Signal_2 BG1 slots: 2-3, 4-5, ... Signal_5 BG2 slots: 1-2, 3-4, ... BG3 slots: 2-3, 4-5, ... Signal_11 BG0 slots: all Signal_4 BG1 slots: 1-2, 3-4, ... BG3 slots: 1-2, 3-4, ... Signal_7 BG2 slots: 2-3, 4-5, ... IACK slots: all The signal traces are made 11 mills wide. Begin work on making P1 into P1 Rev B ----------------------------------------- This is the directory .../p1_uber/p1_design/pcb/mfg Note that it has a subdirectory .../p1_uber/p1_design/pcb/mfg/to_sovereign -rw-r--r-- 1 edmunds d0users 2355 Sep 18 15:07 aperture_table_report -rw-r--r-- 1 edmunds d0users 22254 Sep 18 16:04 artwork_1 -rw-r--r-- 1 edmunds d0users 147822 Sep 18 16:05 artwork_10 -rw-r--r-- 1 edmunds d0users 68474 Sep 18 16:05 artwork_11 -rw-r--r-- 1 edmunds d0users 144971 Sep 18 16:05 artwork_12 -rw-r--r-- 1 edmunds d0users 84998 Sep 18 16:05 artwork_13 -rw-r--r-- 1 edmunds d0users 70353 Sep 18 16:05 artwork_14 -rw-r--r-- 1 edmunds d0users 95862 Sep 18 16:18 artwork_15 -rw-r--r-- 1 edmunds d0users 123013 Sep 18 16:05 artwork_16 -rw-r--r-- 1 edmunds d0users 99091 Sep 18 16:05 artwork_17 -rw-r--r-- 1 edmunds d0users 70078 Sep 18 16:04 artwork_2 -rw-r--r-- 1 edmunds d0users 85274 Sep 18 16:04 artwork_3 -rw-r--r-- 1 edmunds d0users 152941 Sep 18 16:04 artwork_4 -rw-r--r-- 1 edmunds d0users 68215 Sep 18 16:04 artwork_5 -rw-r--r-- 1 edmunds d0users 143966 Sep 18 16:04 artwork_6 -rw-r--r-- 1 edmunds d0users 83540 Sep 18 16:04 artwork_7 -rw-r--r-- 1 edmunds d0users 126438 Sep 18 16:05 artwork_8 -rw-r--r-- 1 edmunds d0users 83637 Sep 18 16:05 artwork_9 -rw-r--r-- 1 edmunds d0users 52723 Sep 18 15:07 drill_plt_unplt -rw-r--r-- 1 edmunds d0users 778 Sep 18 15:06 drill_table_report -rw-r--r-- 1 edmunds d0users 86364 Sep 18 16:05 pre_edit_artwork_15 drwxr-xr-x 2 edmunds d0users 512 Sep 19 15:06 to_sovereign Step one is to make copies all of the files in this directory called *.rev_a This is done by a shell file in p1_uber called "make_copies_of_rev_a_files.sh" Note that NO work will be done in the directory .../p1_uber/p1_design/pcb/mfg/to_sovereign Rather a new "to_sovereign" directory will be created; it is .../p1_uber/to_sovereign The intent is to completely preserve the P1 Rev A material from September 1996. The only artwork files that will be remade are those for the VME TTL Layers These are artwork files: 4,6,8,10, and 12. In addition the SilkScreen Layer will need to be re made so that it can include some indication that this is Rev B of the P1 design. Note that the TARGET logical layer is edited to indicate Rev B. The default artwork order will not be changed. It is: ARTWORK_01 board_outline targets no_thermal ARTWORK_02 power_1 targets board_edge_clearance=0.05 ARTWORK_03 signal_1 power_2 power_3 targets board_edge_clearance=0.05 ARTWORK_04 signal_2 power_4 power_5 targets board_edge_clearance=0.05 ARTWORK_05 power_6 targets board_edge_clearance=0.05 ARTWORK_06 signal_5 power_7 power_8 targets board_edge_clearance=0.05 ARTWORK_07 signal_6 power_9 targets board_edge_clearance=0.05 ARTWORK_08 signal_11 power_10 power_11 targets board_edge_clearance=0.05 ARTWORK_09 signal_3 power_12 targets board_edge_clearance=0.05 ARTWORK_10 signal_4 power_13 power_14 targets board_edge_clearance=0.05 ARTWORK_11 power_15 targets board_edge_clearance=0.05 ARTWORK_12 signal_7 power_16 power_17 targets board_edge_clearance=0.05 ARTWORK_13 signal_8 power_18 power_19 targets board_edge_clearance=0.05 ARTWORK_14 power_20 targets board_edge_clearance=0.05 ARTWORK_15 solder_mask_1 targets no_thermal ARTWORK_16 silkscreen_1 targets no_thermal ARTWORK_17 silkscreen_2 targets no_thermal No new drill data will be generated. So then the steps are: 1. Fix the traces on logical layers: SIGNAL_2, 5, 11, 4, 7 2. Change the SILKSCREEN_1 logical layer to show Rev B 3. Change the TARGET logical layer to show Rev B 4. Creat Gerber data for Artwork numbers 4, 6, 8, 10, 12, 16 When making these plots under the create artwork use: "NO Reliefs", "Output All Pins", "Output All Vias", "NO Output UnPlatted Holes". 5. Run the shell file that collects all of the files that go to Sovereign and put these files in /designs/p1_uber/to_sovereign OK take these steps then Directory of the files in /home2/desings/p1_uber/p1_designs/pcb/mfg after new artwork_4, 6, 8, 10, 12, 16 files were generated. These files are marked with a **. -rw-r--r-- 1 edmunds d0users 22254 Sep 18 16:04 artwork_1 -rw-r--r-- 1 edmunds d0users 22254 Jan 30 11:28 artwork_1.Rev_A -rw-r--r-- 1 edmunds d0users 146882 Jan 30 13:59 artwork_10 ** -rw-r--r-- 1 edmunds d0users 147822 Jan 30 11:28 artwork_10.Rev_A -rw-r--r-- 1 edmunds d0users 68474 Sep 18 16:05 artwork_11 -rw-r--r-- 1 edmunds d0users 68474 Jan 30 11:28 artwork_11.Rev_A -rw-r--r-- 1 edmunds d0users 148583 Jan 30 13:59 artwork_12 ** -rw-r--r-- 1 edmunds d0users 144971 Jan 30 11:28 artwork_12.Rev_A -rw-r--r-- 1 edmunds d0users 84998 Sep 18 16:05 artwork_13 -rw-r--r-- 1 edmunds d0users 84998 Jan 30 11:28 artwork_13.Rev_A -rw-r--r-- 1 edmunds d0users 70353 Sep 18 16:05 artwork_14 -rw-r--r-- 1 edmunds d0users 70353 Jan 30 11:28 artwork_14.Rev_A -rw-r--r-- 1 edmunds d0users 95862 Sep 18 16:18 artwork_15 -rw-r--r-- 1 edmunds d0users 95862 Jan 30 11:28 artwork_15.Rev_A -rw-r--r-- 1 edmunds d0users 121555 Jan 30 13:59 artwork_16 ** -rw-r--r-- 1 edmunds d0users 123013 Jan 30 11:28 artwork_16.Rev_A -rw-r--r-- 1 edmunds d0users 99091 Sep 18 16:05 artwork_17 -rw-r--r-- 1 edmunds d0users 99091 Jan 30 11:28 artwork_17.Rev_A -rw-r--r-- 1 edmunds d0users 70078 Sep 18 16:04 artwork_2 -rw-r--r-- 1 edmunds d0users 70078 Jan 30 11:28 artwork_2.Rev_A -rw-r--r-- 1 edmunds d0users 85274 Sep 18 16:04 artwork_3 -rw-r--r-- 1 edmunds d0users 85274 Jan 30 11:28 artwork_3.Rev_A -rw-r--r-- 1 edmunds d0users 148275 Jan 30 13:58 artwork_4 ** -rw-r--r-- 1 edmunds d0users 152941 Jan 30 11:28 artwork_4.Rev_A -rw-r--r-- 1 edmunds d0users 68215 Sep 18 16:04 artwork_5 -rw-r--r-- 1 edmunds d0users 68215 Jan 30 11:28 artwork_5.Rev_A -rw-r--r-- 1 edmunds d0users 139268 Jan 30 13:58 artwork_6 ** -rw-r--r-- 1 edmunds d0users 143966 Jan 30 11:28 artwork_6.Rev_A -rw-r--r-- 1 edmunds d0users 83540 Sep 18 16:04 artwork_7 -rw-r--r-- 1 edmunds d0users 83540 Jan 30 11:28 artwork_7.Rev_A -rw-r--r-- 1 edmunds d0users 131849 Jan 30 13:59 artwork_8 ** -rw-r--r-- 1 edmunds d0users 126438 Jan 30 11:28 artwork_8.Rev_A -rw-r--r-- 1 edmunds d0users 83637 Sep 18 16:05 artwork_9 -rw-r--r-- 1 edmunds d0users 83637 Jan 30 11:28 artwork_9.Rev_A