5 Row VME Layout -------------------- Rev. 1-MAR-1996 The following is the layout that is used in P1 of all Run II Framework VME Crates. In addition to the normal VME signals, this 5 Row VME layout caries 16 differential ECL timing signals and additional power supplies: -2V and -4.5V. Pins Signal Function ------------------------------------------------------------------- Pin Row Row Row Row Row Number A B C D E ------ ----------- ----------- ----------- ----------- ----------- 1 TS_00_Inv TS_00_NonInv GND TS_08_Inv TS_08_NonInv 2 GND GND GND GND GND 3 TS_01_Inv TS_01_NonInv GND TS_09_Inv TS_09_NonInv 4 TS_02_Inv TS_02_NonInv GND TS_10_Inv TS_10_NonInv 5 TS_03_Inv TS_03_NonInv GND TS_11_Inv TS_11_NonInv 6 TS_04_Inv TS_04_NonInv GND TS_12_Inv TS_12_NonInv 7 TS_05_Inv TS_05_NonInv GND TS_13_Inv TS_13_NonInv 8 TS_06_Inv TS_06_NonInv GND TS_14_Inv TS_14_NonInv 9 TS_07_Inv TS_07_NonInv GND TS_15_Inv TS_15_NonInv 10 GND GND GND GND GND 11 Data_00 BBSY* Data_08 Data_01 BCLR* 12 Data_09 Data_02 GND ACFAIL* GND 13 Data_10 Data_03 BG0IN* Data_11 Data_04 14 BG0OUT* Data_12 Data_05 BG1IN* Data_13 15 Data_06 BG1OUT* Data_14 Data_07 BG2IN* 16 Data_15 BG2OUT* SYSCLK BG3IN* SYSFAIL* 17 BG3OUT* BERR* GND DS1* GND 18 BR0* GND SYSRESET* GND DS0* 19 BR1* LWORD* GND WRITE* GND 20 BR2* GND AM5 BR3* Adrs_23 21 GND DTACK* GND AM0 Adrs_22 22 AM1 GND AS* GND Adrs_21 23 AM2 Adrs_20 AM3 Adrs_19 IACK* 24 Adrs_18 IACKIN* SERCLK Adrs_17 IACKOUT* 25 SERDAT* Adrs_16 AM4 Adrs_15 Adrs_07 26 IRQ7* Adrs_14 Adrs_06 IRQ6* Adrs_13 27 Adrs_05 IRQ5* Adrs_12 Adrs_04 IRQ4* 28 Adrs_11 Adrs_03 IRQ3* Adrs_10 Adrs_02 29 IRQ2* Adrs_09 Adrs_01 IRQ1* Adrs_08 30 GND GND GND GND GND 31 -2V -12V +5V STDBY +12V -4.5V 32 -2V +5V +5V +5V -4.5V ------ ----------- ----------- ----------- ----------- ----------- Pin A B C D E Number Row Row Row Row Row The Following Is the Standard 3 Row VME Pinout ------------------------------------------------ Pins Signal Function --------------------------------------- Pin Row Row Row Number A B C ------ ----------- ----------- ----------- 1 Data_00 _BBSY*_ Data_08 2 Data_01 _BCLR*_ Data_09 3 Data_02 ACFAIL* Data_10 4 Data_03 BG0IN*_ Data_11 5 Data_04 BG0OUT* Data_12 6 Data_05 BG1IN*_ Data_13 7 Data_06 BG1OUT* Data_14 8 Data_07 BG2IN*_ Data_15 9 __GND__ BG2OUT* __GND__ 10 SYSCLK_ BG3IN*_ SYSFAL* 11 __GND__ BG3OUT* BERR*__ 12 _DS1*__ _BR0*__ SYSRST* 13 _DS0*__ _BR1*__ LWORD*_ 14 WRITE*_ _BR2*__ __AM5__ 15 __GND__ _BR3*__ Adrs_23 16 DTACK*_ __AM0__ Adrs_22 17 __GND__ __AM1__ Adrs_21 18 __AS*__ __AM2__ Adrs_20 19 __GND__ __AM3__ Adrs_19 20 _IACK*_ __GND__ Adrs_18 21 IACKIN* SERCLK_ Adrs_17 22 IAKOUT* SERDAT* Adrs_16 23 __AM4__ __GND__ Adrs_15 24 Adrs_07 _IRQ7*_ Adrs_14 25 Adrs_06 _IRQ6*_ Adrs_13 26 Adrs_05 _IRQ5*_ Adrs_12 27 Adrs_04 _IRQ4*_ Adrs_11 28 Adrs_03 _IRQ3*_ Adrs_10 29 Adrs_02 _IRQ2*_ Adrs_09 30 Adrs_01 _IRQ1*_ Adrs_08 31 _-12V__ +5STDBY _+12V__ 32 __+5V__ __+5V__ __+5V__ ------ ----------- ----------- ----------- Pin A B C Number Row Row Row The following table describes the center row on the P2-P3 connectors P2 Row C P3 Row C -------------- --------------- C1 Gnd-1 C1 Gnd-1 C2 +3V-1 C2 +3V-1 C3 Gnd-2 C3 Gnd-2 C4 +3V-2 C4 +3V-2 C5 -2V-1 C5 -4.5V-1 C6 Gnd-3 C6 Gnd-3 C7 +3V-3 C7 +3V-3 C8 Gnd-4 C8 Gnd-4 C9 +5V-1 C9 +5V-1 C10 Gnd-5 C10 Gnd-5 C11 +3V-4 C11 +3V-4 C12 Gnd-6 C12 Gnd-6 C13 +3V-5 C13 +3V-5 C14 Gnd-7 C14 Gnd-7 C15 -2V-2 C15 -4.5V-2 C16 Gnd-8 C16 Gnd-8 C17 +3V-6 C17 +3V-6 C18 Gnd-9 C18 Gnd-9 C19 +5V-2 C19 +5V-2 C20 +3V-7 C20 +3V-7 C21 Gnd-10 C21 Gnd-10 C22 +3V-8 C22 +3V-8 C23 Gnd-11 C23 Gnd-11 C24 -2V-3 C24 -4.5V-3 C25 Gnd-12 C25 Gnd-12 C26 +3V-9 C26 +3V-9 C27 Gnd-13 C27 Gnd-13 C28 +5V-3 C28 +5V-3 C29 +3V-10 C29 +3V-10 C30 Gnd-14 C30 Gnd-14 C31 +3V-11 C31 +3V-11 C32 Gnd-15 C32 Gnd-15