********************************* * * * DZero SsQuid Card Description * * * * Two cards constructed * * in May of 1999 * ********************************* Original: 10-MAY-1999 Last Revised: 28-MAY-1999 Introduction. SsQuid acts as an interface between Run I Level 1 Trigger and Run I Level 2 Trigger. SsQuid connects ironics ports from the VME crate directly to the COMINT card, helping to eliminate the use of a VAX computer on the COMINT card. Overview. The layout for the connections are as follows: *Ironics Ports* *COMINT* *Function* 1 Port A 7:0 Mother Board Adrs 1:8 ironics->comint 2 Port B 15:8 Card Adrs 1:6 Strobe Direction ironics->comint 3 Port B 7:0 Function Adrs 1:8 ironics->comint 4 Port C 7:0 Write Data 1:8 ironics->comint 5 Port D 7:0 Read Data comint->ironics 6 Port E 7:0 Ironics COMINT *port/bit/P2 pin* *function* *port/bit/connector/pin* 1 0 A2 Mother-Board Address 1 A 0 J12 13 1 1 A3 Mother-Board Address 2 A 1 J12 17 1 2 A4 Mother-Board Address 3 A 2 J12 15 1 3 A5 Mother-Board Address 4 A 3 J12 19 1 4 A6 Mother-Board Address 5 A 4 J12 9 1 5 A7 Mother-Board Address 6 A 5 J12 23 1 6 A8 Mother-Board Address 7 A 6 J12 11 1 7 A9 Mother-Board Address 8 A 7 J12 21 Ironics COMINT *port/bit/P2 pin* *function* *port/bit/connector/pin* 2 0 A10 Card Address 1 B 8 J11 7 2 1 A11 Card Address 2 B 9 J11 1 2 2 A12 Card Address 3 B 10 J11 13 2 3 A13 Card Address 4 B 11 J11 5 2 4 A14 Card Address 5 B 12 J11 3 2 5 A15 Card Address 6 B 13 J11 15 2 6 A16 Strobe B 14 J11 9 2 7 A17 Direction B 15 J11 11 Ironics COMINT *port/bit/P2 pin* *function* *port/bit/connector/pin* 3 0 A18 Function Address 1 B 0 J11 27 3 1 A19 Function Address 2 B 1 J11 23 3 2 A20 Function Address 3 B 2 J11 25 3 3 A21 Function Address 4 B 3 J11 21 3 4 A22 Function Address 5 B 4 J11 31 3 5 A23 Function Address 6 B 5 J11 17 3 6 A24 Function Address 7 B 6 J11 29 3 7 A25 Function Address 8 B 7 J11 19 Ironics COMINT *port/bit/P2 pin* *function* *port/bit/connector/pin* 4 0 C24 Data Output 1 C 0 J21 27 4 1 C23 Data Output 2 C 1 J21 23 4 2 C22 Data Output 3 C 2 J21 25 4 3 C21 Data Output 4 C 3 J21 21 4 4 C20 Data Output 5 C 4 J21 31 4 5 C19 Data Output 6 C 5 J21 17 4 6 C18 Data Output 7 C 6 J21 29 4 7 C17 Data Output 8 C 7 J21 19 Ironics COMINT *port/bit/P2 pin* *function* *port/bit/connector/pin* 5 0 C16 Data Input 1 D 0 J22 13 5 1 C15 Data Input 2 D 1 J22 17 5 2 C14 Data Input 3 D 2 J22 15 5 3 C13 Data Input 4 D 3 J22 19 5 4 C12 Data Input 5 D 4 J22 9 5 5 C11 Data Input 6 D 5 J22 23 5 6 C10 Data Input 7 D 6 J22 11 5 7 C9 Data Input 8 D 7 J22 21 Ironics COMINT *port/bit/P2 pin* *function* *port/bit/connector/pin* 6 0 C8 E 0 1 6 1 C7 E 1 3 6 2 C6 E 2 5 6 3 C5 E 3 7 6 4 C4 E 4 9 6 5 C3 E 5 11 6 6 C2 E 6 13 6 7 C1 E 7 15 Net List. *Resistor Network Cnxn* *signal* *Ironics Cnxn* In Out *COMINT Cnxn* 0 P2-A2 R1-1 R1-16 JA-13 1 P2-A3 R1-2 R1-15 JA-17 2 P2-A4 R1-3 R1-14 JA-15 3 P2-A5 R1-4 R1-13 JA-19 4 P2-A6 R1-5 R1-12 JA-9 5 P2-A7 R1-6 R1-11 JA-23 6 P2-A8 R1-7 R1-10 JA-11 7 P2-A9 R1-8 R1-9 JA-21 0 P2-A10 R2-1 R2-16 JB-7 1 P2-A11 R2-2 R2-15 JB-1 2 P2-A12 R2-3 R2-14 JB-13 3 P2-A13 R2-4 R2-13 JB-5 4 P2-A14 R2-5 R2-12 JB-3 5 P2-A15 R2-6 R2-11 JB-15 6 P2-A16 R2-7 R2-10 JB-9 7 P2-A17 R2-8 R2-9 JB-11 0 P2-A18 R4-1 R4-16 JB-27 1 P2-A19 R4-2 R4-15 JB-23 2 P2-A20 R4-3 R4-14 JB-25 3 P2-A21 R4-4 R4-13 JB-21 4 P2-A22 R4-5 R4-12 JB-31 5 P2-A23 R4-6 R4-11 JB-17 6 P2-A24 R4-7 R4-10 JB-29 7 P2-A25 R4-8 R4-9 JB-19 0 P2-C24 R3-8 R3-9 JC-27 1 P2-C23 R3-7 R3-10 JC-23 2 P2-C22 R3-6 R3-11 JC-25 3 P2-C21 R3-5 R3-12 JC-21 4 P2-C20 R3-4 R3-13 JC-31 5 P2-C19 R3-3 R3-14 JC-17 6 P2-C18 R3-2 R3-15 JC-29 7 P2-C17 R3-1 R3-16 JC-19 0 P2-C16 JD-13 1 P2-C15 JD-17 2 P2-C14 JD-15 3 P2-C13 JD-19 4 P2-C12 JD-9 5 P2-C11 JD-23 6 P2-C10 JD-11 7 P2-C9 JD-21 0 P2-C8 JE-1 1 P2-C7 JE-3 2 P2-C6 JE-5 3 P2-C5 JE-7 4 P2-C4 JE-9 5 P2-C3 JE-11 6 P2-C2 JE-13 7 P2-C1 JE-15 Ground Connections. All ground connections are common. Ironics P2 pin COMINT port/pin B2 JA all even no. pins B12 JD all even no. pins B22 JB all even no. pins B31 JC all even no. pins Select CBus 2/1 Port A bit 8 i.e. pin 33 to gnd Bus_CTRL_Request Port C bit 14 i.e. pin 9 to gnd Card Diagram. Component Side. +----/\-------------------/\-----------/\-------------------/\----+ | /|_____________________|\ /|_____________________|\ | | / JD \ G / JC \ | | |_________________________| N |_________________________| | | D | | | | | /\ /\ | /\ /\ | | /|_____________________|\ | /|_____________________|\ | | / JA \ | / JB \ | | |_________________________| |_________________________| | | | | | | |RESISTOR| |RESISTOR| |RESISTOR| |RESISTOR| | | |ONE--->1| |TWO--->1| |THREE->1| |FOUR-->1| | | | | /\ /\ | | /|__________|\ | | / JE \ -------------------------------- | | |______________| _| |_ | +________________________|@| IRONICS PORT |@|___+ |________________________________|