# # This is the Key In Net List file for the # ADAM Paddle Board for the Run II Level 2 Scalers # -======---------------------------------------------- # # Original Rev. 11-JULY-2001 # Most Recent Rev. 12-JULY-2001 # # # # # +----------------TOP---------------+ # | | # | 6 6 +----+-- +----+-- | # | 8 7 |O | |O | | # +-+----+ | J5| | J6| | # | | | | | | | | # | | | |24 | |24 | | # | | J1 | | Pin| | Pin| | # | | | +----+-- +----+-- | # | | | | # | |68 | | # | | pin| | # | | | +----+-- +----+-- | # | | | |0 | |0 | | # | | | | J4| | J3| | All connectors # +-+----+ | | | | | are mounted on # | 2 1 |24 | |24 | | the Component # | | Pin| | Pin| | side of the # | +----+-- +----+-- | Alpha Scaler # +----------------------------------+ paddle board. # # # # # # NET 'ALPHA_IN_01_DIR' J1-3 J4-19 # FPGA #6 CS 3 NET 'ALPHA_IN_01_COMP' J1-4 J4-20 # FPGA #8 CS 3 # NET 'ALPHA_IN_02_DIR' J1-5 J4-17 # FPGA #6 CS 2 NET 'ALPHA_IN_02_COMP' J1-6 J4-18 # FPGA #8 CS 2 # NET 'ALPHA_IN_03_DIR' J1-7 J4-15 # FPGA #6 CS 1 NET 'ALPHA_IN_03_COMP' J1-8 J4-16 # FPGA #8 CS 1 # NET 'ALPHA_IN_04_DIR' J1-9 J4-13 # FPGA #6 CS 0 NET 'ALPHA_IN_04_COMP' J1-10 J4-14 # FPGA #8 CS 0 # # NET 'ALPHA_IN_05_DIR' J1-11 J4-7 # FPGA #2 CS 3 NET 'ALPHA_IN_05_COMP' J1-12 J4-8 # FPGA #4 CS 3 # NET 'ALPHA_IN_06_DIR' J1-13 J4-5 # FPGA #2 CS 2 NET 'ALPHA_IN_06_COMP' J1-14 J4-6 # FPGA #4 CS 2 # NET 'ALPHA_IN_07_DIR' J1-15 J4-3 # FPGA #2 CS 1 NET 'ALPHA_IN_07_COMP' J1-16 J4-4 # FPGA #4 CS 1 # NET 'ALPHA_IN_08_DIR' J1-17 J4-1 # FPGA #2 CS 0 NET 'ALPHA_IN_08_COMP' J1-18 J4-2 # FPGA #4 CS 0 # # NET 'ALPHA_IN_09_DIR' J1-19 J3-19 # FPGA #5 CS 3 NET 'ALPHA_IN_09_COMP' J1-20 J3-20 # FPGA #7 CS 3 # NET 'ALPHA_IN_10_DIR' J1-21 J3-17 # FPGA #5 CS 2 NET 'ALPHA_IN_10_COMP' J1-22 J3-18 # FPGA #7 CS 2 # NET 'ALPHA_IN_11_DIR' J1-23 J3-15 # FPGA #5 CS 1 NET 'ALPHA_IN_11_COMP' J1-24 J3-16 # FPGA #7 CS 1 # NET 'ALPHA_IN_12_DIR' J1-25 J3-13 # FPGA #5 CS 0 NET 'ALPHA_IN_12_COMP' J1-26 J3-14 # FPGA #7 CS 0 # # NET 'ALPHA_IN_13_DIR' J1-27 J3-7 # FPGA #1 CS 3 NET 'ALPHA_IN_13_COMP' J1-28 J3-8 # FPGA #3 CS 3 # NET 'ALPHA_IN_14_DIR' J1-29 J3-5 # FPGA #1 CS 2 NET 'ALPHA_IN_14_COMP' J1-30 J3-6 # FPGA #3 CS 2 # NET 'ALPHA_IN_15_DIR' J1-31 J3-3 # FPGA #1 CS 1 NET 'ALPHA_IN_15_COMP' J1-32 J3-4 # FPGA #3 CS 1 # NET 'ALPHA_IN_16_DIR' J1-33 J3-1 # FPGA #1 CS 0 NET 'ALPHA_IN_16_COMP' J1-34 J3-2 # FPGA #3 CS 0 # # # # # NET 'ALPHA_IN_17_DIR' J1-35 J6-19 # FPGA #14 CS 3 NET 'ALPHA_IN_17_COMP' J1-36 J6-20 # FPGA #16 CS 3 # NET 'ALPHA_IN_18_DIR' J1-37 J6-17 # FPGA #14 CS 2 NET 'ALPHA_IN_18_COMP' J1-38 J6-18 # FPGA #16 CS 2 # NET 'ALPHA_IN_19_DIR' J1-39 J6-15 # FPGA #14 CS 1 NET 'ALPHA_IN_19_COMP' J1-40 J6-16 # FPGA #16 CS 1 # NET 'ALPHA_IN_20_DIR' J1-41 J6-13 # FPGA #14 CS 0 NET 'ALPHA_IN_20_COMP' J1-42 J6-14 # FPGA #16 CS 0 # # NET 'ALPHA_IN_21_DIR' J1-43 J6-7 # FPGA #10 CS 3 NET 'ALPHA_IN_21_COMP' J1-44 J6-8 # FPGA #12 CS 3 # NET 'ALPHA_IN_22_DIR' J1-45 J6-5 # FPGA #10 CS 2 NET 'ALPHA_IN_22_COMP' J1-46 J6-6 # FPGA #12 CS 2 # NET 'ALPHA_IN_23_DIR' J1-47 J6-3 # FPGA #10 CS 1 NET 'ALPHA_IN_23_COMP' J1-48 J6-4 # FPGA #12 CS 1 # NET 'ALPHA_IN_24_DIR' J1-49 J6-1 # FPGA #10 CS 0 NET 'ALPHA_IN_24_COMP' J1-50 J6-2 # FPGA #12 CS 0 # # NET 'ALPHA_IN_25_DIR' J1-51 J5-19 # FPGA #13 CS 3 NET 'ALPHA_IN_25_COMP' J1-52 J5-20 # FPGA #15 CS 3 # NET 'ALPHA_IN_26_DIR' J1-53 J5-17 # FPGA #13 CS 2 NET 'ALPHA_IN_26_COMP' J1-54 J5-18 # FPGA #15 CS 2 # NET 'ALPHA_IN_27_DIR' J1-55 J5-15 # FPGA #13 CS 1 NET 'ALPHA_IN_27_COMP' J1-56 J5-16 # FPGA #15 CS 1 # NET 'ALPHA_IN_28_DIR' J1-57 J5-13 # FPGA #13 CS 0 NET 'ALPHA_IN_28_COMP' J1-58 J5-14 # FPGA #15 CS 0 # # NET 'ALPHA_IN_29_DIR' J1-59 J5-7 # FPGA #9 CS 3 NET 'ALPHA_IN_29_COMP' J1-60 J5-8 # FPGA #11 CS 3 # NET 'ALPHA_IN_30_DIR' J1-61 J5-5 # FPGA #9 CS 2 NET 'ALPHA_IN_30_COMP' J1-62 J5-6 # FPGA #11 CS 2 # NET 'ALPHA_IN_31_DIR' J1-63 J5-3 # FPGA #9 CS 1 NET 'ALPHA_IN_31_COMP' J1-64 J5-4 # FPGA #11 CS 1 # NET 'ALPHA_IN_32_DIR' J1-65 J5-1 # FPGA #9 CS 0 NET 'ALPHA_IN_32_COMP' J1-66 J5-2 # FPGA #11 CS 0 # # NET 'GROUND' J1-1 J1-2 NET 'GROUND' J1-67 J1-68 NET 'GROUND' V1-1 V2-1 #