Scaler Module Paddle Board ------------------------------ Initial Rev. 16-APR-1998 Latest Rev. 31-JULY-1998 The intent is to use the same SM_PB printed circuit board for both the Gated and Per Bunch Scaler Modules. Some assembly differences may exist e.g. what terminators are loaded and whether stackable or normal headers are loaded. On 24-JULY-1998 SCRAP the above idea because a do everything for everyone SM_PB would need to be an 8 layer complicated expensive mess. Instead push on SMB_PB (i.e. scaler module Bunch paddle board). This is an ASPB (Application Specific Paddle Board). SMB_PB is designed just for the per bunch scaler modules. It is small inexpensive and takes care of all of the needs of the per bunch scaler modules. In Mentor start smb_pb_uber as the home for the PER BUNCH sm paddle board. Keep sm_pb_uber as the place to work out the design of a paddle board for the gated scalers. Both of these designs will be covered from this VMS directory. The signals that are distributed by the SM Paddle Board are in the following 2 classes: Common Control Signals that go to all 16 MSA FPGA's. There are 16 of these signals per SM Paddle Board, i.e. 32 Common Control Signals on a SM card. Signals that go to a specific MSA FPGA, 6 signals to each. Each SM Paddle Board takes care of the per FPGA control signals for 8 FPGA's. Thus there are 8 x 6 = 48 of these per FPGA signals per SM Paddle Board. PER BUNCH SM_PB --------------- The following is an outline of the SM Paddle Board as seen looking at its "component" side. ------TOP-------+ / | +----- +----+-- | | |0 | | +-+----+ | J2| | | | O | R1 | | | | | | R2 |32 | | | | J1 | R3 | Pin| | | | | R4 | | | | | | | | | | | | +----+-- | | | | R5 | | | | R6 +----+-- | | | | R7 |O | | | | | R8 | J3| | All connectors +-+----+ |16 | | are mounted on | | Pin| | the Component +----- +----+-- | side of the TDM \ | Paddle Board. ----------------+ Connector J2 is either: a 34 pin 90 degree solder tail 4 wall header without latches a 34 pin 90 degree wire wrap pin 4 wall header without latches or a Panduit 32 pin straight press fit stackable connector Panduit 100-632-951 for 13 mm pins or Panduit 100-632-959 for 17 mm pins J2 carries the 16 Common Control Signals that are received on either P2 or P3. Connector J3 is a pattern for a 16 pin header. It will not be installed unless we need access to some of the per FPGA signals. Connections to the PER BUNCH SM_PB input connector J2 Common Control Signal Numbers J2 Pin ------------------------------------ Numbers At Location P2 At Location P3 ------- ---------------- ---------------- 1-2 Com_Control_0 Com_Control_16 3-4 Com_Control_1 Com_Control_17 5-6 Com_Control_2 Com_Control_18 7-8 Com_Control_3 Com_Control_19 9-10 Com_Control_4 Com_Control_20 11-12 Com_Control_5 Com_Control_21 13-14 Com_Control_6 Com_Control_22 15-16 Com_Control_7 Com_Control_23 17-18 Com_Control_8 Com_Control_24 19-20 Com_Control_9 Com_Control_25 21-22 Com_Control_10 Com_Control_26 23-24 Com_Control_11 Com_Control_27 25-26 Com_Control_12 Com_Control_28 27-28 Com_Control_13 Com_Control_29 29-30 Com_Control_14 Com_Control_30 31-32 Com_Control_15 Com_Control_31 For additional details see the Per Bunch Scaler PB Net List. GATED SM_PB ----------- The following is an outline of the SM Paddle Board as seen looking at its "component" side. -------------TOP-----------+ / | +----- +----+-- +----+-- | | |O | |O | | +-+----+ | J3| | J5| | | | O | R1 |24 | |24 | | | | | R2 | Pin| | Pin| | | | J1 | R3 +----+-- +----+-- | | | | R4 | | | | +-------------------+ | | | | | J2 32 pin 0 | | | | | R5 +-------------------+ | | | | R6 | | | | R7 +----+-- +----+-- | | | | R8 |O | |O | | All connectors +-+----+ | J4| | J6| | are mounted on | |24 | |24 | | the Component +----- | Pin| | Pin| | side of the TDM \ +----+-- +----+-- | Paddle Board. ---------------------------+ Connector J2 is either: a 34 pin 90 degree solder tail 4 wall header without latches a 34 pin 90 degree wire wrap pin 4 wall header without latches or a Panduit 32 pin straight press fit stackable connector Panduit 100-632-951 for 13 mm pins or Panduit 100-632-959 for 17 mm pins Note for 34 pin J2's remove pins 33 and 34. J2 carries the 16 Common Control Signals that are received on either P2 or P3. For most Gated Scaler application this connector will not be used and may not even be installed. The pinout of this connector is the same as is shown in the table for the Per Bunch SM_PB above. Connectors J3, J4, J5, and J6 are actually 24 pin 90 degree solder tail 4 wall headers without latches. The signals received by these connectors are most ofter terminated by 110 Ohms resistors. These 4 connectors carry the PER FPGA CONTROL SIGNALS. Connections to the J3,J4,J5,J6 connectors are described in the following tables. Per FPGA Control Signals __________________________________ Connector At Location P2 At Location P3 --------- -------------- -------------- J3 FPGA's 1,5 FPGA's 3,7 J4 FPGA's 2,6 FPGA's 4,8 J5 FPGA's 9,13 FPGA's 11,15 J6 FPGA's 10,14 FPGA's 12,16 The pinout for anyone of these 4 connectors is: Connector Pins Per FPGA Control Signal -------------- ------------------------------------ 1-2 Lower Number FPGA Control Signal 0 3-4 Lower Number FPGA Control Signal 1 5-6 Lower Number FPGA Control Signal 2 7-8 Lower Number FPGA Control Signal 3 9-10 Lower Number FPGA Control Signal 4 11-12 Lower Number FPGA Control Signal 5 13-14 Upper Number FPGA Control Signal 0 15-16 Upper Number FPGA Control Signal 1 17-18 Upper Number FPGA Control Signal 2 19-20 Upper Number FPGA Control Signal 3 21-22 Upper Number FPGA Control Signal 4 23-24 Upper Number FPGA Control Signal 5 For additional details see the Gated Scaler PB Net List. ************************************************************************* +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ ************************************************************************* Everything below this line is old stuff from when I was trying to do everything with one type of Scale Module paddle board. I have not junked this section of text yet just because I need to check it to verify that it does not contain information that is not covered elsewhere. But remember, look only at the actual next list files to understand how the two Scaler Module Paddle Boards that were produced are wired. Most likely the SM_PB pcb will want to be assembled in two different ways: one for per bunch scalers and a second configuration for the gated scalers. Per Bunch SM_PB Common Control Signals: Stackable connectors on the Common Control Signals with either high resistance terminators or else open terminator for all but the 16th SM_PB which would have 110 Ohm. Per FPGA Control Signals: Do not need to have either a connector or a terminator installed. Gated Scaler SM_PB Common Control Signals: Some of these SM_PB's will want stackable connectors with no terminator or high value terminator and some of these SM_PB's will want a normal cable header and 110 Ohm Terminators. Per FPGA Control Signals: Normal cable headers with 110 Ohm Terminators. The following is an outline of the SM Paddle Board as seen looking at its "component" side. -------------TOP-----------+ / +----+-- +----+-- | / |0 | |O | | +----- | J2| | J4| | | | | |24 | | +-+----+ |32 | | Pin| | | | O | R1 | Pin| +----+-- | | | | R2 | | | | | J1 | R3 | | +----+-- | | | | R4 +----+-- |O | | | | | | J5| | | | | |24 | | | | | R5 | Pin| | | | | R6 +----+-- | | | | R7 | | | | R8 +----+-- +----+-- | All connectors +-+----+ |O | |O | | are mounted on | | J3| | J6| | the Component +----- |24 | |24 | | side of the TDM \ | Pin| | Pin| | Paddle Board. \ +----+-- +----+-- | ---------------------------+ Connector J2 is either: a 34 pin 90 degree solder tail 4 wall header without latches a 34 pin 90 degree wire wrap pin 4 wall header without latches or a Panduit 32 pin straight press fit stackable connector Panduit 100-632-951 for 13 mm pins or Panduit 100-632-959 for 17 mm pins J2 carries the 16 Common Control Signals that are received on either P2 or P3. The signals received by this connectors are either: not terminated, terminated in a high resistance or terminated by 110 Ohms resistors. The holes in the pcb for this connector need to be the right size for the Panduit stackable connectors (i.e. 40 mil diameter finished size). On many of the SM paddle boards (i.e. those used with the per bunch scaler sets) the J2 connector will be stackable straight pin Panduit connector used to carry the same Common Control Signals to all of the Scaler Modules. Connectors J3, J4, J5, and J6 are actually 24 pin 90 degree solder tail 4 wall headers without latches. The signals received by these connectors are most ofter terminated by 110 Ohms resistors. These 4 connectors carry the per FPGA Control Signals. The following table shows for J3, J4, J5, and J6 which of these Scaler Module Paddle Board connectors carries which per FPGA Control Signals when this paddle board is used at both the P2 and P3 locations. When the SM_PB is used on SM_PB ------------------------------- Connector Backplane P2 Backplane P3 --------- ------------- ------------- J4 FPGA's # 1, 5 FPGA's # 3, 7 J5 FPGA's # 9,13 FPGA's #11,15 J6 FPGA's # 2, 6 FPGA's # 4, 8 J3 FPGA's #10,14 FPGA's #12,16 View of the Scaler Module signals on Backplane P2 and P3 Backplane Rows and # of Pins --------- P3 P2 ED BA P2 P3 -------------- ----- ----- ------- -------------- ----- ----- Common Control 23:20 7:4 4 4 Common Control 3:0 19:16 Per FPGA FPGA #11 #9 6 6 Per FPGA FPGA #1 #3 Per FPGA FPGA #15 #13 6 6 Per FPGA FPGA #5 #7 Common Control 31:28 15:12 4 4 Common Control 11:8 27:24 Per FPGA FPGA #12 #10 6 6 Per FPGA FPGA #2 #4 Per FPGA FPGA #16 #14 6 6 Per FPGA FPGA #6 #8 /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ Details of the Connectors on the SM Paddle Board Connector J2 34 (32) pin Male Header Common Control Signals (7:0) & (23:16) ------------ (15:8) & (31:24) J2 Conn Pin Num Destination when used at P2 Destination when used at P3 ------- ---------------------------==--- ---------------------------==--- Dir Cmp Signal MSA Conn Pin Signal MSA Conn Pin --- --- -------------- ---------------- -------------- ---------------- 1 2 Common Cntl 0 0 P2 1 B,A Common Cntl 16 64 P3 1 B,A 3 4 Common Cntl 1 1 P2 2 B,A Common Cntr 17 65 P3 2 B,A 5 6 Common Cntl 2 2 P2 3 B,A Common Cntr 18 66 P3 3 B,A 7 8 Common Cntl 3 3 P2 4 B,A Common Cntr 19 67 P3 4 B,A 9 10 Common Cntl 4 32 P2 1 E,D Common Cntr 20 96 P3 1 E,D 11 12 Common Cntl 5 33 P2 2 E,D Common Cntr 21 97 P3 2 E,D 13 14 Common Cntl 6 34 P2 3 E,D Common Cntr 22 98 P3 3 E,D 15 16 Common Cntl 7 35 P2 4 E,D Common Cntr 23 99 P3 4 E,D 17 18 Common Cntl 8 16 P2 17 B,A Common Cntl 24 80 P3 17 B,A 19 20 Common Cntl 9 17 P2 18 B,A Common Cntr 25 81 P3 18 B,A 21 22 Common Cntl 10 18 P2 19 B,A Common Cntr 26 82 P3 19 B,A 23 24 Common Cntl 11 19 P2 20 B,A Common Cntr 27 83 P3 20 B,A 25 26 Common Cntl 12 48 P2 17 E,D Common Cntr 28 112 P3 17 E,D 27 28 Common Cntl 13 49 P2 18 E,D Common Cntr 29 113 P3 18 E,D 29 30 Common Cntl 14 40 P2 19 E,D Common Cntr 30 114 P3 19 E,D 31 32 Common Cntl 15 51 P2 20 E,D Common Cntr 31 115 P3 20 E,D Connector J4 24 pin Male Header FPGA #1 (3) Control Signals (5:0) & FPGA #5 (7) Control Signals (5:0) J4 Conn Pin Num Destination when used at P2 Destination when used at P3 ------- ---------------------------==--- ---------------------------==--- Dir Cmp Signal MSA Conn Pin Signal MSA Conn Pin --- --- -------------- ---------------- -------------- ---------------- 1 2 FPGA #1 CS 0 4 P2 5 B,A FPGA #3 CS 0 68 P3 5 B,A 3 4 FPGA #1 CS 1 5 P2 6 B,A FPGA #3 CS 1 69 P3 6 B,A 5 6 FPGA #1 CS 2 6 P2 7 B,A FPGA #3 CS 2 70 P3 7 B,A 7 8 FPGA #1 CS 3 7 P2 8 B,A FPGA #3 CS 3 71 P3 8 B,A 9 10 FPGA #1 CS 4 8 P2 9 B,A FPGA #3 CS 4 72 P3 9 B,A 11 12 FPGA #1 CS 5 9 P2 10 B,A FPGA #3 CS 5 73 P3 10 B,A 13 14 FPGA #5 CS 0 10 P2 11 B,A FPGA #7 CS 0 74 P3 11 B,A 15 16 FPGA #5 CS 1 11 P2 12 B,A FPGA #7 CS 1 75 P3 12 B,A 17 18 FPGA #5 CS 2 12 P2 13 B,A FPGA #7 CS 2 76 P3 13 B,A 19 20 FPGA #5 CS 3 13 P2 14 B,A FPGA #7 CS 3 77 P3 14 B,A 21 22 FPGA #5 CS 4 14 P2 15 B,A FPGA #7 CS 4 78 P3 15 B,A 23 24 FPGA #5 CS 5 15 P2 16 B,A FPGA #7 CS 5 79 P3 16 B,A Connector J5 24 pin Male Header FPGA #9 (11) Control Signals (5:0) & FPGA #13 (15) Control Signals (5:0) J5 Conn Pin Num Destination when used at P2 Destination when used at P3 ------- ---------------------------==--- ---------------------------==--- Dir Cmp Signal MSA Conn Pin Signal MSA Conn Pin --- --- -------------- ---------------- -------------- ---------------- 1 2 FPGA #9 CS 0 36 P2 5 E,D FPGA #11 CS 0 100 P3 5 E,D 3 4 FPGA #9 CS 1 37 P2 6 E,D FPGA #11 CS 1 101 P3 6 E,D 5 6 FPGA #9 CS 2 38 P2 7 E,D FPGA #11 CS 2 102 P3 7 E,D 7 8 FPGA #9 CS 3 39 P2 8 E,D FPGA #11 CS 3 103 P3 8 E,D 9 10 FPGA #9 CS 4 40 P2 9 E,D FPGA #11 CS 4 104 P3 9 E,D 11 12 FPGA #9 CS 5 41 P2 10 E,D FPGA #11 CS 5 105 P3 10 E,D 13 14 FPGA #13 CS 0 42 P2 11 E,D FPGA #15 CS 0 106 P3 11 E,D 15 16 FPGA #13 CS 1 43 P2 12 E,D FPGA #15 CS 1 107 P3 12 E,D 17 18 FPGA #13 CS 2 44 P2 13 E,D FPGA #15 CS 2 108 P3 13 E,D 19 20 FPGA #13 CS 3 45 P2 14 E,D FPGA #15 CS 3 109 P3 14 E,D 21 22 FPGA #13 CS 4 46 P2 15 E,D FPGA #15 CS 4 110 P3 15 E,D 23 24 FPGA #13 CS 5 47 P2 16 E,D FPGA #15 CS 5 111 P3 16 E,D Connector J6 24 pin Male Header FPGA #2 (4) Control Signals (5:0) & FPGA #6 (8) Control Signals (5:0) J6 Conn Pin Num Destination when used at P2 Destination when used at P3 ------- ---------------------------==--- ---------------------------==--- Dir Cmp Signal MSA Conn Pin Signal MSA Conn Pin --- --- -------------- ---------------- -------------- ---------------- 1 2 FPGA #2 CS 0 20 P2 21 B,A FPGA #4 CS 0 84 P3 21 B,A 3 4 FPGA #2 CS 1 21 P2 22 B,A FPGA #4 CS 1 85 P3 22 B,A 5 6 FPGA #2 CS 2 22 P2 23 B,A FPGA #4 CS 2 86 P3 23 B,A 7 8 FPGA #2 CS 3 23 P2 24 B,A FPGA #4 CS 3 87 P3 24 B,A 9 10 FPGA #2 CS 4 24 P2 25 B,A FPGA #4 CS 4 88 P3 25 B,A 11 12 FPGA #2 CS 5 25 P2 26 B,A FPGA #4 CS 5 89 P3 26 B,A 13 14 FPGA #6 CS 0 26 P2 27 B,A FPGA #8 CS 0 90 P3 27 B,A 15 16 FPGA #6 CS 1 27 P2 28 B,A FPGA #8 CS 1 91 P3 28 B,A 17 18 FPGA #6 CS 2 28 P2 29 B,A FPGA #8 CS 2 92 P3 29 B,A 19 20 FPGA #6 CS 3 29 P2 30 B,A FPGA #8 CS 3 93 P3 30 B,A 21 22 FPGA #6 CS 4 30 P2 31 B,A FPGA #8 CS 4 94 P3 31 B,A 23 24 FPGA #6 CS 5 31 P2 32 B,A FPGA #8 CS 5 95 P3 32 B,A Connector J3 24 pin Male Header FPGA #10 (12) Control Signals (5:0) & FPGA #14 (16) Control Signals (5:0) J3 Conn Pin Num Destination when used at P2 Destination when used at P3 ------- ---------------------------==--- ---------------------------==--- Dir Cmp Signal MSA Conn Pin Signal MSA Conn Pin --- --- -------------- ---------------- -------------- ---------------- 1 2 FPGA #10 CS 0 52 P2 21 E,D FPGA #12 CS 0 116 P3 21 E,D 3 4 FPGA #10 CS 1 53 P2 22 E,D FPGA #12 CS 1 117 P3 22 E,D 5 6 FPGA #10 CS 2 54 P2 23 E,D FPGA #12 CS 2 118 P3 23 E,D 7 8 FPGA #10 CS 3 55 P2 24 E,D FPGA #12 CS 3 119 P3 24 E,D 9 10 FPGA #10 CS 4 56 P2 25 E,D FPGA #12 CS 4 120 P3 25 E,D 11 12 FPGA #10 CS 5 57 P2 26 E,D FPGA #12 CS 5 121 P3 26 E,D 13 14 FPGA #14 CS 0 58 P2 27 E,D FPGA #16 CS 0 122 P3 27 E,D 15 16 FPGA #14 CS 1 59 P2 28 E,D FPGA #16 CS 1 123 P3 28 E,D 17 18 FPGA #14 CS 2 60 P2 29 E,D FPGA #16 CS 2 124 P3 29 E,D 19 20 FPGA #14 CS 3 61 P2 30 E,D FPGA #16 CS 3 125 P3 30 E,D 21 22 FPGA #14 CS 4 62 P2 31 E,D FPGA #16 CS 4 126 P3 31 E,D 23 24 FPGA #14 CS 5 63 P2 32 E,D FPGA #16 CS 5 127 P3 32 E,D /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ ######################################################################## ---------------------------------------------------------------------- P2: 160-pin E-style DIN connector for Trigger Framework P2 input bus ---------------------------------------------------------------------- The "E" Column is the Direct Input The "B" Column is the Direct Input The "D" Column is the Complmt Input The "A" Column is the Complmt Input ----------------------------------- ----------------------------------- MSA MSA _In _In Pin Signal Description ID Signal Description ID --- --------------------------- --- --------------------------- --- 1 Common Control Signal 4 32 Common Control Signal 0 00 2 Common Control Signal 5 33 Common Control Signal 1 01 3 Common Control Signal 6 34 Common Control Signal 2 02 4 Common Control Signal 7 35 Common Control Signal 3 03 5 FPGA #9 Control Signal 0 36 FPGA #1 Control Signal 0 04 6 FPGA #9 Control Signal 1 37 FPGA #1 Control Signal 1 05 7 FPGA #9 Control Signal 2 38 FPGA #1 Control Signal 2 06 8 FPGA #9 Control Signal 3 39 FPGA #1 Control Signal 3 07 9 FPGA #9 Control Signal 4 40 FPGA #1 Control Signal 4 08 10 FPGA #9 Control Signal 5 41 FPGA #1 Control Signal 5 09 11 FPGA #13 Control Signal 0 42 FPGA #5 Control Signal 0 10 12 FPGA #13 Control Signal 1 43 FPGA #5 Control Signal 1 11 13 FPGA #13 Control Signal 2 44 FPGA #5 Control Signal 2 12 14 FPGA #13 Control Signal 3 45 FPGA #5 Control Signal 3 13 15 FPGA #13 Control Signal 4 46 FPGA #5 Control Signal 4 14 16 FPGA #13 Control Signal 5 47 FPGA #5 Control Signal 5 15 17 Common Control Signal 12 48 Common Control Signal 8 16 18 Common Control Signal 13 49 Common Control Signal 9 17 19 Common Control Signal 14 50 Common Control Signal 10 18 20 Common Control Signal 15 51 Common Control Signal 11 19 21 FPGA #10 Control Signal 0 52 FPGA #2 Control Signal 0 20 22 FPGA #10 Control Signal 1 53 FPGA #2 Control Signal 1 21 23 FPGA #10 Control Signal 2 54 FPGA #2 Control Signal 2 22 24 FPGA #10 Control Signal 3 55 FPGA #2 Control Signal 3 23 25 FPGA #10 Control Signal 4 56 FPGA #2 Control Signal 4 24 26 FPGA #10 Control Signal 5 57 FPGA #2 Control Signal 5 25 27 FPGA #14 Control Signal 0 58 FPGA #6 Control Signal 0 26 28 FPGA #14 Control Signal 1 59 FPGA #6 Control Signal 1 27 29 FPGA #14 Control Signal 2 60 FPGA #6 Control Signal 2 28 30 FPGA #14 Control Signal 3 61 FPGA #6 Control Signal 3 29 31 FPGA #14 Control Signal 4 62 FPGA #6 Control Signal 4 30 32 FPGA #14 Control Signal 5 63 FPGA #6 Control Signal 5 31 ######################################################################## ---------------------------------------------------------------------- P3: 160-pin E-style DIN connector for Trigger Framework P3 input bus ---------------------------------------------------------------------- The "E" Column is the Direct Input The "B" Column is the Direct Input The "D" Column is the Complmt Input The "A" Column is the Complmt Input ----------------------------------- ----------------------------------- MSA MSA _In _In Pin Signal Description ID Signal Description ID --- --------------------------- --- --------------------------- --- 1 Common Control Signal 20 96 Common Control Signal 16 64 2 Common Control Signal 21 97 Common Control Signal 17 65 3 Common Control Signal 22 98 Common Control Signal 18 66 4 Common Control Signal 23 99 Common Control Signal 19 67 5 FPGA #11 Control Signal 0 100 FPGA #3 Control Signal 0 68 6 FPGA #11 Control Signal 1 101 FPGA #3 Control Signal 1 69 7 FPGA #11 Control Signal 2 102 FPGA #3 Control Signal 2 70 8 FPGA #11 Control Signal 3 103 FPGA #3 Control Signal 3 71 9 FPGA #11 Control Signal 4 104 FPGA #3 Control Signal 4 72 10 FPGA #11 Control Signal 5 105 FPGA #3 Control Signal 5 73 11 FPGA #15 Control Signal 0 106 FPGA #7 Control Signal 0 74 12 FPGA #15 Control Signal 1 107 FPGA #7 Control Signal 1 75 13 FPGA #15 Control Signal 2 108 FPGA #7 Control Signal 2 76 14 FPGA #15 Control Signal 3 109 FPGA #7 Control Signal 3 77 15 FPGA #15 Control Signal 4 110 FPGA #7 Control Signal 4 78 16 FPGA #15 Control Signal 5 111 FPGA #7 Control Signal 5 79 17 Common Control Signal 28 112 Common Control Signal 24 80 18 Common Control Signal 29 113 Common Control Signal 25 81 19 Common Control Signal 30 114 Common Control Signal 26 82 20 Common Control Signal 31 115 Common Control Signal 27 83 21 FPGA #12 Control Signal 0 116 FPGA #4 Control Signal 0 84 22 FPGA #12 Control Signal 1 117 FPGA #4 Control Signal 1 85 23 FPGA #12 Control Signal 2 118 FPGA #4 Control Signal 2 86 24 FPGA #12 Control Signal 3 119 FPGA #4 Control Signal 3 87 25 FPGA #12 Control Signal 4 120 FPGA #4 Control Signal 4 88 26 FPGA #12 Control Signal 5 121 FPGA #4 Control Signal 5 89 27 FPGA #16 Control Signal 0 122 FPGA #8 Control Signal 0 90 28 FPGA #16 Control Signal 1 123 FPGA #8 Control Signal 1 91 29 FPGA #16 Control Signal 2 124 FPGA #8 Control Signal 2 92 30 FPGA #16 Control Signal 3 125 FPGA #8 Control Signal 3 93 31 FPGA #16 Control Signal 4 126 FPGA #8 Control Signal 4 94 32 FPGA #16 Control Signal 5 127 FPGA #8 Control Signal 5 95 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! ######################################################################## For reference the following is a diagram of the Main Array Signal Input Term Number vs backplane pin number as viewed from the back of the backplane. Connector P2 Connector P3 MSA Input Terms 0:63 MSA Input Terms 64:127 ---------------------- ---------------------- E D C B A E D C B A 1 1 1 1 1 1 1 1 1 1 32 0 96 64 : : <--- Term Number ---> : : 47 15 111 79 E D C B A E D C B A 1 1 1 1 1 1 1 1 1 1 6 6 6 6 6 6 6 6 6 6 E D C B A E D C B A 1 1 1 1 1 1 1 1 1 1 7 7 7 7 7 7 7 7 7 7 48 16 112 80 : : <--- Term Number ---> : : 63 31 127 95 E D C B A E D C B A 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 ######################################################################## The following is Extracted from the SM Description file. ---------------------------------------------------------------------- P2: 160-pin E-style DIN connector for Trigger Framework P2 input bus ---------------------------------------------------------------------- Pin # Signal Description Dir Identifier ----- ------------------ --- ---------- A1 Common Control Signal 0 COM INPUT MSA_In_000 B1 Common Control Signal 0 DIR INPUT MSA_In_000 A2 Common Control Signal 1 COM INPUT MSA_In_001 B2 Common Control Signal 1 DIR INPUT MSA_In_001 A3 Common Control Signal 2 COM INPUT MSA_In_002 B3 Common Control Signal 2 DIR INPUT MSA_In_002 A4 Common Control Signal 3 COM INPUT MSA_In_003 B4 Common Control Signal 3 DIR INPUT MSA_In_003 A5 MSA FPGA 1 Per-FPGA Control Signal 0 COM INPUT MSA_In_004 B5 MSA FPGA 1 Per-FPGA Control Signal 0 DIR INPUT MSA_In_004 A6 MSA FPGA 1 Per-FPGA Control Signal 1 COM INPUT MSA_In_005 B6 MSA FPGA 1 Per-FPGA Control Signal 1 DIR INPUT MSA_In_005 A7 MSA FPGA 1 Per-FPGA Control Signal 2 COM INPUT MSA_In_006 B7 MSA FPGA 1 Per-FPGA Control Signal 2 DIR INPUT MSA_In_006 A8 MSA FPGA 1 Per-FPGA Control Signal 3 COM INPUT MSA_In_007 B8 MSA FPGA 1 Per-FPGA Control Signal 3 DIR INPUT MSA_In_007 A9 MSA FPGA 1 Per-FPGA Control Signal 4 COM INPUT MSA_In_008 B9 MSA FPGA 1 Per-FPGA Control Signal 4 DIR INPUT MSA_In_008 A10 MSA FPGA 1 Per-FPGA Control Signal 5 COM INPUT MSA_In_009 B10 MSA FPGA 1 Per-FPGA Control Signal 5 DIR INPUT MSA_In_009 A11 MSA FPGA 5 Per-FPGA Control Signal 0 COM INPUT MSA_In_010 B11 MSA FPGA 5 Per-FPGA Control Signal 0 DIR INPUT MSA_In_010 A12 MSA FPGA 5 Per-FPGA Control Signal 1 COM INPUT MSA_In_011 B12 MSA FPGA 5 Per-FPGA Control Signal 1 DIR INPUT MSA_In_011 A13 MSA FPGA 5 Per-FPGA Control Signal 2 COM INPUT MSA_In_012 B13 MSA FPGA 5 Per-FPGA Control Signal 2 DIR INPUT MSA_In_012 A14 MSA FPGA 5 Per-FPGA Control Signal 3 COM INPUT MSA_In_013 B14 MSA FPGA 5 Per-FPGA Control Signal 3 DIR INPUT MSA_In_013 A15 MSA FPGA 5 Per-FPGA Control Signal 4 COM INPUT MSA_In_014 B15 MSA FPGA 5 Per-FPGA Control Signal 4 DIR INPUT MSA_In_014 A16 MSA FPGA 5 Per-FPGA Control Signal 5 COM INPUT MSA_In_015 B16 MSA FPGA 5 Per-FPGA Control Signal 5 DIR INPUT MSA_In_015 A17 Common Control Signal 8 COM INPUT MSA_In_016 B17 Common Control Signal 8 DIR INPUT MSA_In_016 A18 Common Control Signal 9 COM INPUT MSA_In_017 B18 Common Control Signal 9 DIR INPUT MSA_In_017 A19 Common Control Signal 10 COM INPUT MSA_In_018 B19 Common Control Signal 10 DIR INPUT MSA_In_018 A20 Common Control Signal 11 COM INPUT MSA_In_019 B20 Common Control Signal 11 DIR INPUT MSA_In_019 A21 MSA FPGA 2 Per-FPGA Control Signal 0 COM INPUT MSA_In_020 B21 MSA FPGA 2 Per-FPGA Control Signal 0 DIR INPUT MSA_In_020 A22 MSA FPGA 2 Per-FPGA Control Signal 1 COM INPUT MSA_In_021 B22 MSA FPGA 2 Per-FPGA Control Signal 1 DIR INPUT MSA_In_021 A23 MSA FPGA 2 Per-FPGA Control Signal 2 COM INPUT MSA_In_022 B23 MSA FPGA 2 Per-FPGA Control Signal 2 DIR INPUT MSA_In_022 A24 MSA FPGA 2 Per-FPGA Control Signal 3 COM INPUT MSA_In_023 B24 MSA FPGA 2 Per-FPGA Control Signal 3 DIR INPUT MSA_In_023 A25 MSA FPGA 2 Per-FPGA Control Signal 4 COM INPUT MSA_In_024 B25 MSA FPGA 2 Per-FPGA Control Signal 4 DIR INPUT MSA_In_024 A26 MSA FPGA 2 Per-FPGA Control Signal 5 COM INPUT MSA_In_025 B26 MSA FPGA 2 Per-FPGA Control Signal 5 DIR INPUT MSA_In_025 A27 MSA FPGA 6 Per-FPGA Control Signal 0 COM INPUT MSA_In_026 B27 MSA FPGA 6 Per-FPGA Control Signal 0 DIR INPUT MSA_In_026 A28 MSA FPGA 6 Per-FPGA Control Signal 1 COM INPUT MSA_In_027 B28 MSA FPGA 6 Per-FPGA Control Signal 1 DIR INPUT MSA_In_027 A29 MSA FPGA 6 Per-FPGA Control Signal 2 COM INPUT MSA_In_028 B29 MSA FPGA 6 Per-FPGA Control Signal 2 DIR INPUT MSA_In_028 A30 MSA FPGA 6 Per-FPGA Control Signal 3 COM INPUT MSA_In_029 B30 MSA FPGA 6 Per-FPGA Control Signal 3 DIR INPUT MSA_In_029 A31 MSA FPGA 6 Per-FPGA Control Signal 4 COM INPUT MSA_In_030 B31 MSA FPGA 6 Per-FPGA Control Signal 4 DIR INPUT MSA_In_030 A32 MSA FPGA 6 Per-FPGA Control Signal 5 COM INPUT MSA_In_031 B32 MSA FPGA 6 Per-FPGA Control Signal 5 DIR INPUT MSA_In_031 C1 GROUND C32 GROUND D1 Common Control Signal 4 COM INPUT MSA_In_032 E1 Common Control Signal 4 DIR INPUT MSA_In_032 D2 Common Control Signal 5 COM INPUT MSA_In_033 E2 Common Control Signal 5 DIR INPUT MSA_In_033 D3 Common Control Signal 6 COM INPUT MSA_In_034 E3 Common Control Signal 6 DIR INPUT MSA_In_034 D4 Common Control Signal 7 COM INPUT MSA_In_035 E4 Common Control Signal 7 DIR INPUT MSA_In_035 D5 MSA FPGA 9 Per-FPGA Control Signal 0 COM INPUT MSA_In_036 E5 MSA FPGA 9 Per-FPGA Control Signal 0 DIR INPUT MSA_In_036 D6 MSA FPGA 9 Per-FPGA Control Signal 1 COM INPUT MSA_In_037 E6 MSA FPGA 9 Per-FPGA Control Signal 1 DIR INPUT MSA_In_037 D7 MSA FPGA 9 Per-FPGA Control Signal 2 COM INPUT MSA_In_038 E7 MSA FPGA 9 Per-FPGA Control Signal 2 DIR INPUT MSA_In_038 D8 MSA FPGA 9 Per-FPGA Control Signal 3 COM INPUT MSA_In_039 E8 MSA FPGA 9 Per-FPGA Control Signal 3 DIR INPUT MSA_In_039 D9 MSA FPGA 9 Per-FPGA Control Signal 4 COM INPUT MSA_In_040 E9 MSA FPGA 9 Per-FPGA Control Signal 4 DIR INPUT MSA_In_040 D10 MSA FPGA 9 Per-FPGA Control Signal 5 COM INPUT MSA_In_041 E10 MSA FPGA 9 Per-FPGA Control Signal 5 DIR INPUT MSA_In_041 D11 MSA FPGA 13 Per-FPGA Control Signal 0 COM INPUT MSA_In_042 E11 MSA FPGA 13 Per-FPGA Control Signal 0 DIR INPUT MSA_In_042 D12 MSA FPGA 13 Per-FPGA Control Signal 1 COM INPUT MSA_In_043 E12 MSA FPGA 13 Per-FPGA Control Signal 1 DIR INPUT MSA_In_043 D13 MSA FPGA 13 Per-FPGA Control Signal 2 COM INPUT MSA_In_044 E13 MSA FPGA 13 Per-FPGA Control Signal 2 DIR INPUT MSA_In_044 D14 MSA FPGA 13 Per-FPGA Control Signal 3 COM INPUT MSA_In_045 E14 MSA FPGA 13 Per-FPGA Control Signal 3 DIR INPUT MSA_In_045 D15 MSA FPGA 13 Per-FPGA Control Signal 4 COM INPUT MSA_In_046 E15 MSA FPGA 13 Per-FPGA Control Signal 4 DIR INPUT MSA_In_046 D16 MSA FPGA 13 Per-FPGA Control Signal 5 COM INPUT MSA_In_047 E16 MSA FPGA 13 Per-FPGA Control Signal 5 DIR INPUT MSA_In_047 D17 Common Control Signal 12 COM INPUT MSA_In_048 E17 Common Control Signal 12 DIR INPUT MSA_In_048 D18 Common Control Signal 13 COM INPUT MSA_In_049 E18 Common Control Signal 13 DIR INPUT MSA_In_049 D19 Common Control Signal 14 COM INPUT MSA_In_050 E19 Common Control Signal 14 DIR INPUT MSA_In_050 D20 Common Control Signal 15 COM INPUT MSA_In_051 E20 Common Control Signal 15 DIR INPUT MSA_In_051 D21 MSA FPGA 10 Per-FPGA Control Signal 0 COM INPUT MSA_In_052 E21 MSA FPGA 10 Per-FPGA Control Signal 0 DIR INPUT MSA_In_052 D22 MSA FPGA 10 Per-FPGA Control Signal 1 COM INPUT MSA_In_053 E22 MSA FPGA 10 Per-FPGA Control Signal 1 DIR INPUT MSA_In_053 D23 MSA FPGA 10 Per-FPGA Control Signal 2 COM INPUT MSA_In_054 E23 MSA FPGA 10 Per-FPGA Control Signal 2 DIR INPUT MSA_In_054 D24 MSA FPGA 10 Per-FPGA Control Signal 3 COM INPUT MSA_In_055 E24 MSA FPGA 10 Per-FPGA Control Signal 3 DIR INPUT MSA_In_055 D25 MSA FPGA 10 Per-FPGA Control Signal 4 COM INPUT MSA_In_056 E25 MSA FPGA 10 Per-FPGA Control Signal 4 DIR INPUT MSA_In_056 D26 MSA FPGA 10 Per-FPGA Control Signal 5 COM INPUT MSA_In_057 E26 MSA FPGA 10 Per-FPGA Control Signal 5 DIR INPUT MSA_In_057 D27 MSA FPGA 14 Per-FPGA Control Signal 0 COM INPUT MSA_In_058 E27 MSA FPGA 14 Per-FPGA Control Signal 0 DIR INPUT MSA_In_058 D28 MSA FPGA 14 Per-FPGA Control Signal 1 COM INPUT MSA_In_059 E28 MSA FPGA 14 Per-FPGA Control Signal 1 DIR INPUT MSA_In_059 D29 MSA FPGA 14 Per-FPGA Control Signal 2 COM INPUT MSA_In_060 E29 MSA FPGA 14 Per-FPGA Control Signal 2 DIR INPUT MSA_In_060 D30 MSA FPGA 14 Per-FPGA Control Signal 3 COM INPUT MSA_In_061 E30 MSA FPGA 14 Per-FPGA Control Signal 3 DIR INPUT MSA_In_061 D31 MSA FPGA 14 Per-FPGA Control Signal 4 COM INPUT MSA_In_062 E31 MSA FPGA 14 Per-FPGA Control Signal 4 DIR INPUT MSA_In_062 D32 MSA FPGA 14 Per-FPGA Control Signal 5 COM INPUT MSA_In_063 E32 MSA FPGA 14 Per-FPGA Control Signal 5 DIR INPUT MSA_In_063 ---------------------------------------------------------------------- P3: 160-pin E-style DIN connector for Trigger Framework P3 input bus ---------------------------------------------------------------------- Pin # Signal Description Dir Identifier ----- ------------------ --- ---------- A1 Common Control Signal 16 COM INPUT MSA_In_064 B1 Common Control Signal 16 DIR INPUT MSA_In_064 A2 Common Control Signal 17 COM INPUT MSA_In_065 B2 Common Control Signal 17 DIR INPUT MSA_In_065 A3 Common Control Signal 18 COM INPUT MSA_In_066 B3 Common Control Signal 18 DIR INPUT MSA_In_066 A4 Common Control Signal 19 COM INPUT MSA_In_067 B4 Common Control Signal 19 DIR INPUT MSA_In_067 A5 MSA FPGA 3 Per-FPGA Control Signal 0 COM INPUT MSA_In_068 B5 MSA FPGA 3 Per-FPGA Control Signal 0 DIR INPUT MSA_In_068 A6 MSA FPGA 3 Per-FPGA Control Signal 1 COM INPUT MSA_In_069 B6 MSA FPGA 3 Per-FPGA Control Signal 1 DIR INPUT MSA_In_069 A7 MSA FPGA 3 Per-FPGA Control Signal 2 COM INPUT MSA_In_070 B7 MSA FPGA 3 Per-FPGA Control Signal 2 DIR INPUT MSA_In_070 A8 MSA FPGA 3 Per-FPGA Control Signal 3 COM INPUT MSA_In_071 B8 MSA FPGA 3 Per-FPGA Control Signal 3 DIR INPUT MSA_In_071 A9 MSA FPGA 3 Per-FPGA Control Signal 4 COM INPUT MSA_In_072 B9 MSA FPGA 3 Per-FPGA Control Signal 4 DIR INPUT MSA_In_072 A10 MSA FPGA 3 Per-FPGA Control Signal 5 COM INPUT MSA_In_073 B10 MSA FPGA 3 Per-FPGA Control Signal 5 DIR INPUT MSA_In_073 A11 MSA FPGA 7 Per-FPGA Control Signal 0 COM INPUT MSA_In_074 B11 MSA FPGA 7 Per-FPGA Control Signal 0 DIR INPUT MSA_In_074 A12 MSA FPGA 7 Per-FPGA Control Signal 1 COM INPUT MSA_In_075 B12 MSA FPGA 7 Per-FPGA Control Signal 1 DIR INPUT MSA_In_075 A13 MSA FPGA 7 Per-FPGA Control Signal 2 COM INPUT MSA_In_076 B13 MSA FPGA 7 Per-FPGA Control Signal 2 DIR INPUT MSA_In_076 A14 MSA FPGA 7 Per-FPGA Control Signal 3 COM INPUT MSA_In_077 B14 MSA FPGA 7 Per-FPGA Control Signal 3 DIR INPUT MSA_In_077 A15 MSA FPGA 7 Per-FPGA Control Signal 4 COM INPUT MSA_In_078 B15 MSA FPGA 7 Per-FPGA Control Signal 4 DIR INPUT MSA_In_078 A16 MSA FPGA 7 Per-FPGA Control Signal 5 COM INPUT MSA_In_079 B16 MSA FPGA 7 Per-FPGA Control Signal 5 DIR INPUT MSA_In_079 A17 Common Control Signal 24 COM INPUT MSA_In_080 B17 Common Control Signal 24 DIR INPUT MSA_In_080 A18 Common Control Signal 25 COM INPUT MSA_In_081 B18 Common Control Signal 25 DIR INPUT MSA_In_081 A19 Common Control Signal 26 COM INPUT MSA_In_082 B19 Common Control Signal 26 DIR INPUT MSA_In_082 A20 Common Control Signal 27 COM INPUT MSA_In_083 B20 Common Control Signal 27 DIR INPUT MSA_In_083 A21 MSA FPGA 4 Per-FPGA Control Signal 0 COM INPUT MSA_In_084 B21 MSA FPGA 4 Per-FPGA Control Signal 0 DIR INPUT MSA_In_084 A22 MSA FPGA 4 Per-FPGA Control Signal 1 COM INPUT MSA_In_085 B22 MSA FPGA 4 Per-FPGA Control Signal 1 DIR INPUT MSA_In_085 A23 MSA FPGA 4 Per-FPGA Control Signal 2 COM INPUT MSA_In_086 B23 MSA FPGA 4 Per-FPGA Control Signal 2 DIR INPUT MSA_In_086 A24 MSA FPGA 4 Per-FPGA Control Signal 3 COM INPUT MSA_In_087 B24 MSA FPGA 4 Per-FPGA Control Signal 3 DIR INPUT MSA_In_087 A25 MSA FPGA 4 Per-FPGA Control Signal 4 COM INPUT MSA_In_088 B25 MSA FPGA 4 Per-FPGA Control Signal 4 DIR INPUT MSA_In_088 A26 MSA FPGA 4 Per-FPGA Control Signal 5 COM INPUT MSA_In_089 B26 MSA FPGA 4 Per-FPGA Control Signal 5 DIR INPUT MSA_In_089 A27 MSA FPGA 8 Per-FPGA Control Signal 0 COM INPUT MSA_In_090 B27 MSA FPGA 8 Per-FPGA Control Signal 0 DIR INPUT MSA_In_090 A28 MSA FPGA 8 Per-FPGA Control Signal 1 COM INPUT MSA_In_091 B28 MSA FPGA 8 Per-FPGA Control Signal 1 DIR INPUT MSA_In_091 A29 MSA FPGA 8 Per-FPGA Control Signal 2 COM INPUT MSA_In_092 B29 MSA FPGA 8 Per-FPGA Control Signal 2 DIR INPUT MSA_In_092 A30 MSA FPGA 8 Per-FPGA Control Signal 3 COM INPUT MSA_In_093 B30 MSA FPGA 8 Per-FPGA Control Signal 3 DIR INPUT MSA_In_093 A31 MSA FPGA 8 Per-FPGA Control Signal 4 COM INPUT MSA_In_094 B31 MSA FPGA 8 Per-FPGA Control Signal 4 DIR INPUT MSA_In_094 A32 MSA FPGA 8 Per-FPGA Control Signal 5 COM INPUT MSA_In_095 B32 MSA FPGA 8 Per-FPGA Control Signal 5 DIR INPUT MSA_In_095 C1 GROUND C32 GROUND D1 Common Control Signal 20 COM INPUT MSA_In_096 E1 Common Control Signal 20 DIR INPUT MSA_In_096 D2 Common Control Signal 21 COM INPUT MSA_In_097 E2 Common Control Signal 21 DIR INPUT MSA_In_097 D3 Common Control Signal 22 COM INPUT MSA_In_098 E3 Common Control Signal 22 DIR INPUT MSA_In_098 D4 Common Control Signal 23 COM INPUT MSA_In_099 E4 Common Control Signal 23 DIR INPUT MSA_In_099 D5 MSA FPGA 11 Per-FPGA Control Signal 0 COM INPUT MSA_In_100 E5 MSA FPGA 11 Per-FPGA Control Signal 0 DIR INPUT MSA_In_100 D6 MSA FPGA 11 Per-FPGA Control Signal 1 COM INPUT MSA_In_101 E6 MSA FPGA 11 Per-FPGA Control Signal 1 DIR INPUT MSA_In_101 D7 MSA FPGA 11 Per-FPGA Control Signal 2 COM INPUT MSA_In_102 E7 MSA FPGA 11 Per-FPGA Control Signal 2 DIR INPUT MSA_In_102 D8 MSA FPGA 11 Per-FPGA Control Signal 3 COM INPUT MSA_In_103 E8 MSA FPGA 11 Per-FPGA Control Signal 3 DIR INPUT MSA_In_103 D9 MSA FPGA 11 Per-FPGA Control Signal 4 COM INPUT MSA_In_104 E9 MSA FPGA 11 Per-FPGA Control Signal 4 DIR INPUT MSA_In_104 D10 MSA FPGA 11 Per-FPGA Control Signal 5 COM INPUT MSA_In_105 E10 MSA FPGA 11 Per-FPGA Control Signal 5 DIR INPUT MSA_In_105 D11 MSA FPGA 15 Per-FPGA Control Signal 0 COM INPUT MSA_In_106 E11 MSA FPGA 15 Per-FPGA Control Signal 0 DIR INPUT MSA_In_106 D12 MSA FPGA 15 Per-FPGA Control Signal 1 COM INPUT MSA_In_107 E12 MSA FPGA 15 Per-FPGA Control Signal 1 DIR INPUT MSA_In_107 D13 MSA FPGA 15 Per-FPGA Control Signal 2 COM INPUT MSA_In_108 E13 MSA FPGA 15 Per-FPGA Control Signal 2 DIR INPUT MSA_In_108 D14 MSA FPGA 15 Per-FPGA Control Signal 3 COM INPUT MSA_In_109 E14 MSA FPGA 15 Per-FPGA Control Signal 3 DIR INPUT MSA_In_109 D15 MSA FPGA 15 Per-FPGA Control Signal 4 COM INPUT MSA_In_110 E15 MSA FPGA 15 Per-FPGA Control Signal 4 DIR INPUT MSA_In_110 D16 MSA FPGA 15 Per-FPGA Control Signal 5 COM INPUT MSA_In_111 E16 MSA FPGA 15 Per-FPGA Control Signal 5 DIR INPUT MSA_In_111 D17 Common Control Signal 28 COM INPUT MSA_In_112 E17 Common Control Signal 28 DIR INPUT MSA_In_112 D18 Common Control Signal 29 COM INPUT MSA_In_113 E18 Common Control Signal 29 DIR INPUT MSA_In_113 D19 Common Control Signal 30 COM INPUT MSA_In_114 E19 Common Control Signal 30 DIR INPUT MSA_In_114 D20 Common Control Signal 31 COM INPUT MSA_In_115 E20 Common Control Signal 31 DIR INPUT MSA_In_115 D21 MSA FPGA 12 Per-FPGA Control Signal 0 COM INPUT MSA_In_116 E21 MSA FPGA 12 Per-FPGA Control Signal 0 DIR INPUT MSA_In_116 D22 MSA FPGA 12 Per-FPGA Control Signal 1 COM INPUT MSA_In_117 E22 MSA FPGA 12 Per-FPGA Control Signal 1 DIR INPUT MSA_In_117 D23 MSA FPGA 12 Per-FPGA Control Signal 2 COM INPUT MSA_In_118 E23 MSA FPGA 12 Per-FPGA Control Signal 2 DIR INPUT MSA_In_118 D24 MSA FPGA 12 Per-FPGA Control Signal 3 COM INPUT MSA_In_119 E24 MSA FPGA 12 Per-FPGA Control Signal 3 DIR INPUT MSA_In_119 D25 MSA FPGA 12 Per-FPGA Control Signal 4 COM INPUT MSA_In_120 E25 MSA FPGA 12 Per-FPGA Control Signal 4 DIR INPUT MSA_In_120 D26 MSA FPGA 12 Per-FPGA Control Signal 5 COM INPUT MSA_In_121 E26 MSA FPGA 12 Per-FPGA Control Signal 5 DIR INPUT MSA_In_121 D27 MSA FPGA 16 Per-FPGA Control Signal 0 COM INPUT MSA_In_122 E27 MSA FPGA 16 Per-FPGA Control Signal 0 DIR INPUT MSA_In_122 D28 MSA FPGA 16 Per-FPGA Control Signal 1 COM INPUT MSA_In_123 E28 MSA FPGA 16 Per-FPGA Control Signal 1 DIR INPUT MSA_In_123 D29 MSA FPGA 16 Per-FPGA Control Signal 2 COM INPUT MSA_In_124 E29 MSA FPGA 16 Per-FPGA Control Signal 2 DIR INPUT MSA_In_124 D30 MSA FPGA 16 Per-FPGA Control Signal 3 COM INPUT MSA_In_125 E30 MSA FPGA 16 Per-FPGA Control Signal 3 DIR INPUT MSA_In_125 D31 MSA FPGA 16 Per-FPGA Control Signal 4 COM INPUT MSA_In_126 E31 MSA FPGA 16 Per-FPGA Control Signal 4 DIR INPUT MSA_In_126 D32 MSA FPGA 16 Per-FPGA Control Signal 5 COM INPUT MSA_In_127 E32 MSA FPGA 16 Per-FPGA Control Signal 5 DIR INPUT MSA_In_127