#
#                   SMB  Paddle Board Net List
#                  -===------------------------
#
#                                                 Original Rev. 22-JULY-1998
#                                              Most Recent Rev. 24-JULY-1998
#
#
#
#     This file is the Mentor Net List for the  SM  Paddle Board.
#
#
#
# The following is an outline of the SM Paddle Board as seen looking at
# its "component" side.
#
#                          ------TOP-------+
#                         /                |
#                   +-----       +----+--  |
#                   |            |0   |    |
#                 +-+----+       |  J2|    |
#                 | | O  | R1    |    |    |
#                 | |    | R2    |32  |    |
#                 | | J1 | R3    | Pin|    |
#                 | |    | R4    |    |    |
#                 | |    |       |    |    |
#                 | |    |       +----+--  |
#                 | |    | R5              |
#                 | |    | R6    +----+--  |
#                 | |    | R7    |O   |    |
#                 | |    | R8    |  J3|    |             All connectors
#                 +-+----+       |16  |    |             are mounted on
#                   |            | Pin|    |             the Component
#                   +-----       +----+--  |             side of the TDM
#                         \                |             Paddle Board.
#                          ----------------+
#
#
#
# Connector  J2 is either:
#    a 34 pin 90 degree solder tail 4 wall header without latches
#    a 34 pin 90 degree wire wrap pin 4 wall header without latches
#    or a Panduit 32 pin straight press fit stackable connector
#    Panduit 100-632-951 for 13 mm pins or  Panduit 100-632-959 for 17 mm pins
#
#   J2 carries the 16 Common Control Signals that are received on either P2
#   or P3.
#
# Connector J3  is a pattern for a 16 pin header.  It will not be installed
# unless we need access to some of the per FPGA signals.
#
#
#
#   The following is the actual Mentor Net List for the SMB Paddle Board
#
#    The 64 nets listed below are labeled by their net names  (MSA_IN_00
#    through MSA_IN_63)  which is appropriate when this paddle board is
#    used at the J2 backplane location.
#
#    The text in the comment field of the "DIRECT" side of the signal
#    shows the function of the signal when the paddle board is used in
#    the J2 location.
#
#    The table also shows the function of the signal when the paddle board
#    is used in the J3 location.   This is shown under the comment field
#    of the "COMPLIMENT" side of the signal.  In the J3 case the
#    appropriate MSA_IN number is found by adding 64 to the MSA_IN number
#    shown.
#
#
#
#
NET   'MAS_IN_00_DIR'     J2-1     J1-B1      R1-1     # Common Cntl 0
NET   'MAS_IN_00_COMP'    J2-2     J1-A1      R1-16    # Common Cntl 16
#
NET   'MAS_IN_01_DIR'     J2-3     J1-B2      R1-3     # Common Cntl 1
NET   'MAS_IN_01_COMP'    J2-4     J1-A2      R1-14    # Common Cntl 17
#
NET   'MAS_IN_02_DIR'     J2-5     J1-B3      R1-5     # Common Cntl 2
NET   'MAS_IN_02_COMP'    J2-6     J1-A3      R1-12    # Common Cntl 18
#
NET   'MAS_IN_03_DIR'     J2-7     J1-B4      R1-7     # Common Cntl 3
NET   'MAS_IN_03_COMP'    J2-8     J1-A4      R1-10    # Common Cntl 19
#
#
#
NET   'MAS_IN_04_DIR'              J1-B5      R2-1     # FPGA #1  CS 0
NET   'MAS_IN_04_COMP'             J1-A5      R2-16    # FPGA #3  CS 0
#
NET   'MAS_IN_05_DIR'              J1-B6      R2-3     # FPGA #1  CS 1
NET   'MAS_IN_05_COMP'             J1-A6      R2-14    # FPGA #3  CS 1
#
NET   'MAS_IN_06_DIR'              J1-B7      R2-5     # FPGA #1  CS 2
NET   'MAS_IN_06_COMP'             J1-A7      R2-12    # FPGA #3  CS 2
#
NET   'MAS_IN_07_DIR'              J1-B8      R2-7     # FPGA #1  CS 3
NET   'MAS_IN_07_COMP'             J1-A8      R2-10    # FPGA #3  CS 3
#
NET   'MAS_IN_08_DIR'              J1-B9      R3-1     # FPGA #1  CS 4
NET   'MAS_IN_08_COMP'             J1-A9      R3-16    # FPGA #3  CS 4
#
NET   'MAS_IN_09_DIR'              J1-B10     R3-3     # FPGA #1  CS 5
NET   'MAS_IN_09_COMP'             J1-A10     R3-14    # FPGA #3  CS 5
#
#
#
NET   'MAS_IN_10_DIR'              J1-B11     R3-5     # FPGA #5  CS 0
NET   'MAS_IN_10_COMP'             J1-A11     R3-12    # FPGA #7  CS 0
#
NET   'MAS_IN_11_DIR'              J1-B12     R3-7     # FPGA #5  CS 1
NET   'MAS_IN_11_COMP'             J1-A12     R3-10    # FPGA #7  CS 1
#
NET   'MAS_IN_12_DIR'              J1-B13     R4-1     # FPGA #5  CS 2
NET   'MAS_IN_12_COMP'             J1-A13     R4-16    # FPGA #7  CS 2
#
NET   'MAS_IN_13_DIR'              J1-B14     R4-3     # FPGA #5  CS 3
NET   'MAS_IN_13_COMP'             J1-A14     R4-14    # FPGA #7  CS 3
#
NET   'MAS_IN_14_DIR'              J1-B15     R4-5     # FPGA #5  CS 4
NET   'MAS_IN_14_COMP'             J1-A15     R4-12    # FPGA #7  CS 4
#
NET   'MAS_IN_15_DIR'              J1-B16     R4-7     # FPGA #5  CS 5
NET   'MAS_IN_15_COMP'             J1-A16     R4-10    # FPGA #7  CS 5
#
#
#
#
NET   'MAS_IN_16_DIR'     J2-17    J1-B17     R5-2     # Common Cntl 8
NET   'MAS_IN_16_COMP'    J2-18    J1-A17     R5-15    # Common Cntl 24
#
NET   'MAS_IN_17_DIR'     J2-19    J1-B18     R5-4     # Common Cntl 9
NET   'MAS_IN_17_COMP'    J2-20    J1-A18     R5-13    # Common Cntl 25
#
NET   'MAS_IN_18_DIR'     J2-21    J1-B19     R5-6     # Common Cntl 10
NET   'MAS_IN_18_COMP'    J2-22    J1-A19     R5-11    # Common Cntl 26
#
NET   'MAS_IN_19_DIR'     J2-23    J1-B20     R5-8     # Common Cntl 11
NET   'MAS_IN_19_COMP'    J2-24    J1-A20     R5-9     # Common Cntl 27
#
#
#
NET   'MAS_IN_20_DIR'              J1-B21     R6-2     # FPGA #2  CS 0
NET   'MAS_IN_20_COMP'             J1-A21     R6-15    # FPGA #4  CS 0
#
NET   'MAS_IN_21_DIR'              J1-B22     R6-4     # FPGA #2  CS 1
NET   'MAS_IN_21_COMP'             J1-A22     R6-13    # FPGA #4  CS 1
#
NET   'MAS_IN_22_DIR'              J1-B23     R6-6     # FPGA #2  CS 2
NET   'MAS_IN_22_COMP'             J1-A23     R6-11    # FPGA #4  CS 2
#
NET   'MAS_IN_23_DIR'              J1-B24     R6-8     # FPGA #2  CS 3
NET   'MAS_IN_23_COMP'             J1-A24     R6-9     # FPGA #4  CS 3
#
NET   'MAS_IN_24_DIR'              J1-B25     R7-2     # FPGA #2  CS 4
NET   'MAS_IN_24_COMP'             J1-A25     R7-15    # FPGA #4  CS 4
#
NET   'MAS_IN_25_DIR'              J1-B26     R7-4     # FPGA #2  CS 5
NET   'MAS_IN_25_COMP'             J1-A26     R7-13    # FPGA #4  CS 5
#
#
#
NET   'MAS_IN_26_DIR'              J1-B27     R7-6     # FPGA #6  CS 0
NET   'MAS_IN_26_COMP'             J1-A27     R7-11    # FPGA #8  CS 0
#
NET   'MAS_IN_27_DIR'              J1-B28     R7-8     # FPGA #6  CS 1
NET   'MAS_IN_27_COMP'             J1-A28     R7-9     # FPGA #8  CS 1
#
NET   'MAS_IN_28_DIR'              J1-B29     R8-2     # FPGA #6  CS 2
NET   'MAS_IN_28_COMP'             J1-A29     R8-15    # FPGA #8  CS 2
#
NET   'MAS_IN_29_DIR'              J1-B30     R8-4     # FPGA #6  CS 3
NET   'MAS_IN_29_COMP'             J1-A30     R8-13    # FPGA #8  CS 3
#
NET   'MAS_IN_30_DIR'              J1-B31     R8-6     # FPGA #6  CS 4
NET   'MAS_IN_30_COMP'             J1-A31     R8-11    # FPGA #8  CS 4
#
NET   'MAS_IN_31_DIR'              J1-B32     R8-8     # FPGA #6  CS 5
NET   'MAS_IN_31_COMP'             J1-A32     R8-9     # FPGA #8  CS 5
#
#
#
#
#
NET   'MAS_IN_32_DIR'     J2-9     J1-E1      R1-2     # Common Cntl 4
NET   'MAS_IN_32_COMP'    J2-10    J1-D1      R1-15    # Common Cntl 20
#
NET   'MAS_IN_33_DIR'     J2-11    J1-E2      R1-4     # Common Cntl 5
NET   'MAS_IN_33_COMP'    J2-12    J1-D2      R1-13    # Common Cntl 21
#
NET   'MAS_IN_34_DIR'     J2-13    J1-E3      R1-6     # Common Cntl 6
NET   'MAS_IN_34_COMP'    J2-14    J1-D3      R1-11    # Common Cntl 22
#
NET   'MAS_IN_35_DIR'     J2-15    J1-E4      R1-8     # Common Cntl 7
NET   'MAS_IN_35_COMP'    J2-16    J1-D4      R1-9     # Common Cntl 23
#
#
#
NET   'MAS_IN_36_DIR'              J1-E5      R2-2     # FPGA #9  CS 0
NET   'MAS_IN_36_COMP'             J1-D5      R2-15    # FPGA #11 CS 0
#
NET   'MAS_IN_37_DIR'              J1-E6      R2-4     # FPGA #9  CS 1
NET   'MAS_IN_37_COMP'             J1-D6      R2-13    # FPGA #11 CS 1
#
NET   'MAS_IN_38_DIR'              J1-E7      R2-6     # FPGA #9  CS 2
NET   'MAS_IN_38_COMP'             J1-D7      R2-11    # FPGA #11 CS 2
#
NET   'MAS_IN_39_DIR'              J1-E8      R2-8     # FPGA #9  CS 3
NET   'MAS_IN_39_COMP'             J1-D8      R2-9     # FPGA #11 CS 3
#
NET   'MAS_IN_40_DIR'              J1-E9      R3-2     # FPGA #9  CS 4
NET   'MAS_IN_40_COMP'             J1-D9      R3-15    # FPGA #11 CS 4
#
NET   'MAS_IN_41_DIR'              J1-E10     R3-4     # FPGA #9  CS 5
NET   'MAS_IN_41_COMP'             J1-D10     R3-13    # FPGA #11 CS 5
#
#
#
NET   'MAS_IN_42_DIR'              J1-E11     R3-6     # FPGA #13 CS 0
NET   'MAS_IN_42_COMP'             J1-D11     R3-11    # FPGA #15 CS 0
#
NET   'MAS_IN_43_DIR'              J1-E12     R3-8     # FPGA #13 CS 1
NET   'MAS_IN_43_COMP'             J1-D12     R3-9     # FPGA #15 CS 1
#
NET   'MAS_IN_44_DIR'              J1-E13     R4-2     # FPGA #13 CS 2
NET   'MAS_IN_44_COMP'             J1-D13     R4-15    # FPGA #15 CS 2
#
NET   'MAS_IN_45_DIR'              J1-E14     R4-4     # FPGA #13 CS 3
NET   'MAS_IN_45_COMP'             J1-D14     R4-13    # FPGA #15 CS 3
#
NET   'MAS_IN_46_DIR'              J1-E15     R4-6     # FPGA #13 CS 4
NET   'MAS_IN_46_COMP'             J1-D15     R4-11    # FPGA #15 CS 4
#
NET   'MAS_IN_47_DIR'              J1-E16     R4-8     # FPGA #13 CS 5
NET   'MAS_IN_47_COMP'             J1-D16     R4-9     # FPGA #15 CS 5
#
#
#
#
NET   'MAS_IN_48_DIR'     J2-25    J1-E17     R5-1     # Common Cntl 12
NET   'MAS_IN_48_COMP'    J2-26    J1-D17     R5-16    # Common Cntl 28
#
NET   'MAS_IN_49_DIR'     J2-27    J1-E18     R5-3     # Common Cntl 13
NET   'MAS_IN_49_COMP'    J2-28    J1-D18     R5-14    # Common Cntl 29
#
NET   'MAS_IN_50_DIR'     J2-29    J1-E19     R5-5     # Common Cntl 14
NET   'MAS_IN_50_COMP'    J2-30    J1-D19     R5-12    # Common Cntl 30
#
NET   'MAS_IN_51_DIR'     J2-31    J1-E20     R5-7     # Common Cntl 15
NET   'MAS_IN_51_COMP'    J2-32    J1-D20     R5-10    # Common Cntl 31
#
#
#
NET   'MAS_IN_52_DIR'              J1-E21     R6-1     # FPGA #10 CS 0
NET   'MAS_IN_52_COMP'             J1-D21     R6-16    # FPGA #12 CS 0
#
NET   'MAS_IN_53_DIR'              J1-E22     R6-3     # FPGA #10 CS 1
NET   'MAS_IN_53_COMP'             J1-D22     R6-14    # FPGA #12 CS 1
#
NET   'MAS_IN_54_DIR'              J1-E23     R6-5     # FPGA #10 CS 2
NET   'MAS_IN_54_COMP'             J1-D23     R6-12    # FPGA #12 CS 2
#
NET   'MAS_IN_55_DIR'              J1-E24     R6-7     # FPGA #10 CS 3
NET   'MAS_IN_55_COMP'             J1-D24     R6-10    # FPGA #12 CS 3
#
NET   'MAS_IN_56_DIR'              J1-E25     R7-1     # FPGA #10 CS 4
NET   'MAS_IN_56_COMP'             J1-D25     R7-16    # FPGA #12 CS 4
#
NET   'MAS_IN_57_DIR'              J1-E26     R7-3     # FPGA #10 CS 5
NET   'MAS_IN_57_COMP'             J1-D26     R7-14    # FPGA #12 CS 5
#
#
#
NET   'MAS_IN_58_DIR'              J1-E27     R7-5     # FPGA #14 CS 0
NET   'MAS_IN_58_COMP'             J1-D27     R7-12    # FPGA #16 CS 0
#
NET   'MAS_IN_59_DIR'              J1-E28     R7-7     # FPGA #14 CS 1
NET   'MAS_IN_59_COMP'             J1-D28     R7-10    # FPGA #16 CS 1
#
NET   'MAS_IN_60_DIR'              J1-E29     R8-1     # FPGA #14 CS 2
NET   'MAS_IN_60_COMP'             J1-D29     R8-16    # FPGA #16 CS 2
#
NET   'MAS_IN_61_DIR'              J1-E30     R8-3     # FPGA #14 CS 3
NET   'MAS_IN_61_COMP'             J1-D30     R8-14    # FPGA #16 CS 3
#
NET   'MAS_IN_62_DIR'              J1-E31     R8-5     # FPGA #14 CS 4
NET   'MAS_IN_62_COMP'             J1-D31     R8-12    # FPGA #16 CS 4
#
NET   'MAS_IN_63_DIR'              J1-E32     R8-7     # FPGA #14 CS 5
NET   'MAS_IN_63_COMP'             J1-D32     R8-10    # FPGA #16 CS 5
#
#
#
#
#
#
#   Ground Nets that connect the J1 center row Gnd pins to the Gnd Plane
#
NET  'GROUND'      J1-C1
NET  'GROUND'      J1-C3
NET  'GROUND'      J1-C6
NET  'GROUND'      J1-C8
NET  'GROUND'      J1-C10
NET  'GROUND'      J1-C12
NET  'GROUND'      J1-C14
NET  'GROUND'      J1-C16
NET  'GROUND'      J1-C18
NET  'GROUND'      J1-C21
NET  'GROUND'      J1-C23
NET  'GROUND'      J1-C25
NET  'GROUND'      J1-C27
NET  'GROUND'      J1-C30
NET  'GROUND'      J1-C32
#
#
#   Ground Via's
#
NET  'GROUND'      V1-1   V2-1
#
#
#
#
#   Spare 16 Pin Connector Via Nets
#
NET  'SPARE_1'      V3-1    J3-1
NET  'SPARE_2'      V4-1    J3-2
#
NET  'SPARE_3'      V5-1    J3-3
NET  'SPARE_4'      V6-1    J3-4
#
NET  'SPARE_5'      V7-1    J3-5
NET  'SPARE_6'      V8-1    J3-6
#
NET  'SPARE_7'      V9-1    J3-7
NET  'SPARE_8'      V10-1   J3-8
#
NET  'SPARE_9'      V11-1   J3-9
NET  'SPARE_10'     V12-1   J3-10
#
NET  'SPARE_11'     V13-1   J3-11
NET  'SPARE_12'     V14-1   J3-12
#
NET  'SPARE_13'     V15-1   J3-13
NET  'SPARE_14'     V16-1   J3-14
#
NET  'SPARE_15'     V17-1   J3-15
NET  'SPARE_16'     V18-1   J3-16
#
#
#