Term Receiver Module Paddle Board Description -------------------------------------------------- Original Rev. 20-MAY-1997 Most Recent Rev. 26-JAN-1998 This file describes the Paddle Board that goes on the back of the backplane P2 and P3 connectors of slots with the Term Receiver Module card. This card has a standard 160 pin female 90 degree solder tail DIN connector on one side and two 40 pin 4 wall 90 degree solder tail male headers with latches on the opposite side. There are also layout patterns on this card for two 26 pin 4 wall 90 degree solder tail male headers. These two 26 pin headers are for the "spare" Main Signal Array inputs and normally these 26 pin headers will not be installed. The following is an outline of the TRM Paddle Board as seen looking at its "component" side. ---------------------------+ / TOP | / +----+-- +----+-- | +----- |O | |O | | | | | | J2 | | +-+----+ | J4 | | | | | | O | | | | Spr| | | | | | Trm| +----+-- | | | J1 | |0:15| | | | | +----+-- +----+-- | | | | |O | | | | | +----+-- | | | | | | |O | | J3 | | All connectors +-+----+ | J5 | | | | are mounted on | | | | Trm| | the Component +----- | Spr| |16:31 | side of the TRM \ +----+-- +----+-- | Paddle Board. \ | ---------------------------+ J4 TERMS 0:15 which are connected to signals in the MAS_IN_0 : MAS_IN_15 range The GAP Signal for Terms 0:15 is on MAS_IN_32 The STROBE Signal for Terms 0:15 is on MAS_IN_33 J2 Spare signals in the MAS_IN_34 : MAS_IN_47 range J3 TERMS 16:31 which are connected to signals in the MAS_IN_16 : MAS_IN_31 range The GAP Signal for Terms 16:31 is on MAS_IN_48 The STROBE Signal for Terms 16:31 is on MAS_IN_49 J5 Spare Signals in the MAS_IN_50 : MAS_IN_63 range Connections to the Two Level 1 Term Input Cable Connectors ----------------------------------------------------------------- Connector J4 is for Level 1 And-Or Input TERMS 0:15 it has the following connections to the Main Signal Array Inputs: TERMS 0:15 connect to MAS_IN_0 : MAS_IN_15 The GAP Signal for Terms 0:15 connects to MAS_IN_32 The STROBE Signal for Terms 0:15 connects to MAS_IN_33 Connector J3 is for Level 1 And-Or Input TERMS 16:31 it has the following connections to the Main Signal Array Inputs: TERMS 16:31 connect to MAS_IN_16 : MAS_IN_31 The GAP Signal for Terms 16:31 connects to MAS_IN_48 The STROBE Signal for Terms 16:31 connects to MAS_IN_49 Recall the Layout of the Main Array Signal Inputs AS VIEWED from the BACKPLANE P2 P3 ----------------- ----------------- E D C B A E D C B A +-------------------+ +-------------------+ | +----+ + +----+ | | +----+ + +----+ | | | 32 | P | 00 | | | | 96 | P | 64 | | | |DrCp| O |DrCp| | | |DrCp| O |DrCp| | | | 47 | W | 15 | | | |111 | W | 79 | | | +----+ + +----+ | | +----+ + +----+ | | & | | & | | +----+ + +----+ | | +----+ + +----+ | | | 48 | G | 16 | | | |112 | G | 80 | | | |DrCp| N |DrCp| | | |DrCp| N |DrCp| | | | 63 | D | 31 | | | |127 | D | 95 | | | +----+ + +----+ | | +----+ + +----+ | +-------------------+ +-------------------+ In all cases the Direct signal of a differential pair is received by a pin in rows B or E and the Complement half of the pair is received by a pin in row A or D. MSA_In_000 : MSA_In_031 received on P2 rows A,B pins 1:32 MSA_In_032 : MSA_In_063 received on P2 rows D,E pins 1:32 MSA_In_064 : MSA_In_095 received on P3 rows A,B pins 1:32 MSA_In_096 : MSA_In_127 received on P3 rows D,E pins 1:32 Design Details -------------- The card is 2.900" x 4.950" Physical Layer Order Logical Layer Function ---------- ----- ------------------ ----------------------- Physical_1 1 Pad_1, Signal_1 Comp Side Direct Half Physical_2 2 Pad_2, Signal_2 Comp Half Physical_3 3 Power_1 GROUND Physical_4 4 Pad_3, Signal_3 Direct Half Physical_5 5 Pad_4, Signal_4 Solder Side Comp Half DAM_1 Label for Board Outline Test Plot Artwork Order Logical Layers Special Stuff ------- ----------------------------- -------------------------- 1 Board_Outline, Dam_1, Target Test Plot 2 Signal_1, Pad_1, Target 3 Signal_2, Pad_2, Target 4 Power_1, Target Thermo Relief Clr 150 mil 5 Signal_3, Pad_3, Target 6 Signal_4, Pad_4, Target 7 Silkscreen_1, Target 8 SolderMask_1, Target 9 SolderMask_2, Target DAM_1 is the target area label for the board outline test plot. Gerber File vs Baord Layer File Name Contents Location in Board Stack -------------- ---------------------------- --------------------------- ArtWork_01.Grb Test plot of board outline ArtWork_02.Grb Component side Traces & Pads Component Side ArtWork_03.Grb Layer #2 traces Next to Component Side ArtWork_04.Grb Ground Planes Used on BOTH Center Layers ArtWork_05.Grb Layer #5 traces Next to Solder Side ArtWork_06.Grb Solder side Traces & Pads Solder Side ArtWork_07.Grb Component side Silkscreen On the Component Side ArtWork_08.Grb Solder Mask Component Side On the Component Side ArtWork_09.Grb Solder Mask Solder Side On the Solder Side Hand Edit the two Solder Mask files to cover up all 33 mil vias. SolderMask Pen Table ------------------------- D10 10 mil D12 65 mil Holes Finished Size -------------------------- 13 mil x 96 38 mil x 294 106 mil x 8 Hand copy the following files to the ../trm_pb_uber/copy_to_flop_dir TRM_Pabble_Brd_Aperture_Table_Report.txt --> aperture.txt TRM_Pabble_Brd_Drill_Table_Report.txt --> drill.txt TRM_Pabble_Brd_Manufacture_Instructions.txt --> instruct.txt COPY_TO_FLOPPY_DIRECTORY.SH located in /a_card_uber is used to move Gerber and drill data files from /pcb/mfg to the /Copy_to_Flop_Dir xXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxX From the description of the Term Receiver Module circuit board ---------------------------------------------------------------------- P2: 160-pin E-style DIN connector for Trigger Framework P2 input bus -------------------------------------------------------------------- (note: 0 <= n <= 3) Pin # Signal Description Dir Identifier ----- ------------------ --- ---------- A1 Subsystem And-Or Input Term 64*n + 0 COM INPUT MSA_In_000 B1 Subsystem And-Or Input Term 64*n + 0 DIR INPUT MSA_In_000 A2 Subsystem And-Or Input Term 64*n + 1 COM INPUT MSA_In_001 B2 Subsystem And-Or Input Term 64*n + 1 DIR INPUT MSA_In_001 A3 Subsystem And-Or Input Term 64*n + 2 COM INPUT MSA_In_002 B3 Subsystem And-Or Input Term 64*n + 2 DIR INPUT MSA_In_002 A4 Subsystem And-Or Input Term 64*n + 3 COM INPUT MSA_In_003 B4 Subsystem And-Or Input Term 64*n + 3 DIR INPUT MSA_In_003 A5 Subsystem And-Or Input Term 64*n + 4 COM INPUT MSA_In_004 B5 Subsystem And-Or Input Term 64*n + 4 DIR INPUT MSA_In_004 A6 Subsystem And-Or Input Term 64*n + 5 COM INPUT MSA_In_005 B6 Subsystem And-Or Input Term 64*n + 5 DIR INPUT MSA_In_005 A7 Subsystem And-Or Input Term 64*n + 6 COM INPUT MSA_In_006 B7 Subsystem And-Or Input Term 64*n + 6 DIR INPUT MSA_In_006 A8 Subsystem And-Or Input Term 64*n + 7 COM INPUT MSA_In_007 B8 Subsystem And-Or Input Term 64*n + 7 DIR INPUT MSA_In_007 A9 Subsystem And-Or Input Term 64*n + 8 COM INPUT MSA_In_008 B9 Subsystem And-Or Input Term 64*n + 8 DIR INPUT MSA_In_008 A10 Subsystem And-Or Input Term 64*n + 9 COM INPUT MSA_In_009 B10 Subsystem And-Or Input Term 64*n + 9 DIR INPUT MSA_In_009 A11 Subsystem And-Or Input Term 64*n + 10 COM INPUT MSA_In_010 B11 Subsystem And-Or Input Term 64*n + 10 DIR INPUT MSA_In_010 A12 Subsystem And-Or Input Term 64*n + 11 COM INPUT MSA_In_011 B12 Subsystem And-Or Input Term 64*n + 11 DIR INPUT MSA_In_011 A13 Subsystem And-Or Input Term 64*n + 12 COM INPUT MSA_In_012 B13 Subsystem And-Or Input Term 64*n + 12 DIR INPUT MSA_In_012 A14 Subsystem And-Or Input Term 64*n + 13 COM INPUT MSA_In_013 B14 Subsystem And-Or Input Term 64*n + 13 DIR INPUT MSA_In_013 A15 Subsystem And-Or Input Term 64*n + 14 COM INPUT MSA_In_014 B15 Subsystem And-Or Input Term 64*n + 14 DIR INPUT MSA_In_014 A16 Subsystem And-Or Input Term 64*n + 15 COM INPUT MSA_In_015 B16 Subsystem And-Or Input Term 64*n + 15 DIR INPUT MSA_In_015 A17 Subsystem And-Or Input Term 64*n + 16 COM INPUT MSA_In_016 B17 Subsystem And-Or Input Term 64*n + 16 DIR INPUT MSA_In_016 A18 Subsystem And-Or Input Term 64*n + 17 COM INPUT MSA_In_017 B18 Subsystem And-Or Input Term 64*n + 17 DIR INPUT MSA_In_017 A19 Subsystem And-Or Input Term 64*n + 18 COM INPUT MSA_In_018 B19 Subsystem And-Or Input Term 64*n + 18 DIR INPUT MSA_In_018 A20 Subsystem And-Or Input Term 64*n + 19 COM INPUT MSA_In_019 B20 Subsystem And-Or Input Term 64*n + 19 DIR INPUT MSA_In_019 A21 Subsystem And-Or Input Term 64*n + 20 COM INPUT MSA_In_020 B21 Subsystem And-Or Input Term 64*n + 20 DIR INPUT MSA_In_020 A22 Subsystem And-Or Input Term 64*n + 21 COM INPUT MSA_In_021 B22 Subsystem And-Or Input Term 64*n + 21 DIR INPUT MSA_In_021 A23 Subsystem And-Or Input Term 64*n + 22 COM INPUT MSA_In_022 B23 Subsystem And-Or Input Term 64*n + 22 DIR INPUT MSA_In_022 A24 Subsystem And-Or Input Term 64*n + 23 COM INPUT MSA_In_023 B24 Subsystem And-Or Input Term 64*n + 23 DIR INPUT MSA_In_023 A25 Subsystem And-Or Input Term 64*n + 24 COM INPUT MSA_In_024 B25 Subsystem And-Or Input Term 64*n + 24 DIR INPUT MSA_In_024 A26 Subsystem And-Or Input Term 64*n + 25 COM INPUT MSA_In_025 B26 Subsystem And-Or Input Term 64*n + 25 DIR INPUT MSA_In_025 A27 Subsystem And-Or Input Term 64*n + 26 COM INPUT MSA_In_026 B27 Subsystem And-Or Input Term 64*n + 26 DIR INPUT MSA_In_026 A28 Subsystem And-Or Input Term 64*n + 27 COM INPUT MSA_In_027 B28 Subsystem And-Or Input Term 64*n + 27 DIR INPUT MSA_In_027 A29 Subsystem And-Or Input Term 64*n + 28 COM INPUT MSA_In_028 B29 Subsystem And-Or Input Term 64*n + 28 DIR INPUT MSA_In_028 A30 Subsystem And-Or Input Term 64*n + 29 COM INPUT MSA_In_029 B30 Subsystem And-Or Input Term 64*n + 29 DIR INPUT MSA_In_029 A31 Subsystem And-Or Input Term 64*n + 30 COM INPUT MSA_In_030 B31 Subsystem And-Or Input Term 64*n + 30 DIR INPUT MSA_In_030 A32 Subsystem And-Or Input Term 64*n + 31 COM INPUT MSA_In_031 B32 Subsystem And-Or Input Term 64*n + 31 DIR INPUT MSA_In_031 C1 GROUND C2 +3.3V UPPER C3 GROUND C4 +3.3V UPPER C5 -2.0V UPPER C6 GROUND C7 +3.3V UPPER C8 GROUND C9 +5.0V UPPER C10 GROUND C11 +3.3V UPPER C12 GROUND C13 +3.3V UPPER C14 GROUND C15 -2.0V UPPER C16 GROUND C17 +3.3V UPPER C18 GROUND C19 +5.0V UPPER C20 +3.3V UPPER C21 GROUND C22 +3.3V UPPER C23 GROUND C24 -2.0V UPPER C25 GROUND C26 +3.3V UPPER C27 GROUND C28 +5.0V UPPER C29 +3.3V UPPER C30 GROUND C31 +3.3V UPPER C32 GROUND D1 Subsystem Gap COM INPUT MSA_In_032 E1 Subsystem Gap DIR INPUT MSA_In_032 D2 Subsystem Strobe to AOITs 64*n + (0:15) COM INPUT MSA_In_033 E2 Subsystem Strobe to AOITs 64*n + (0:15) DIR INPUT MSA_In_033 D3 Spare: Column 1, Per-Column Spare 0 COM INPUT MSA_In_034 E3 Spare: Column 1, Per-Column Spare 0 DIR INPUT MSA_In_034 D4 Spare: Column 1, Per-Column Spare 1 COM INPUT MSA_In_035 E4 Spare: Column 1, Per-Column Spare 1 DIR INPUT MSA_In_035 D5 Spare: Global 0 COM INPUT MSA_In_036 E5 Spare: Global 0 DIR INPUT MSA_In_036 D6 Spare: Global 1 COM INPUT MSA_In_037 E6 Spare: Global 1 DIR INPUT MSA_In_037 D7 Spare: Global 2 COM INPUT MSA_In_038 E7 Spare: Global 2 DIR INPUT MSA_In_038 D8 Spare: Global 3 COM INPUT MSA_In_039 E8 Spare: Global 3 DIR INPUT MSA_In_039 D9 Spare: MSA FPGA 1 Per-FPGA Spare COM INPUT MSA_In_040 E9 Spare: MSA FPGA 1 Per-FPGA Spare DIR INPUT MSA_In_040 D10 Spare: MSA FPGA 5 Per-FPGA Spare COM INPUT MSA_In_041 E10 Spare: MSA FPGA 5 Per-FPGA Spare DIR INPUT MSA_In_041 D11 Spare: MSA FPGA 9 Per-FPGA Spare COM INPUT MSA_In_042 E11 Spare: MSA FPGA 9 Per-FPGA Spare DIR INPUT MSA_In_042 D12 Spare: MSA FPGA 13 Per-FPGA Spare COM INPUT MSA_In_043 E12 Spare: MSA FPGA 13 Per-FPGA Spare DIR INPUT MSA_In_043 D13 Spare: Unrouted 0 COM INPUT MSA_In_044 E13 Spare: Unrouted 0 DIR INPUT MSA_In_044 D14 Spare: Unrouted 1 COM INPUT MSA_In_045 E14 Spare: Unrouted 1 DIR INPUT MSA_In_045 D15 Spare: Unrouted 2 COM INPUT MSA_In_046 E15 Spare: Unrouted 2 DIR INPUT MSA_In_046 D16 Spare: Unrouted 3 COM INPUT MSA_In_047 E16 Spare: Unrouted 3 DIR INPUT MSA_In_047 D17 Subsystem Gap COM INPUT MSA_In_048 E17 Subsystem Gap DIR INPUT MSA_In_048 D18 Subsystem Strobe to AOITS 64*n + (16:31) COM INPUT MSA_In_049 E18 Subsystem Strobe to AOITS 64*n + (16:31) DIR INPUT MSA_In_049 D19 Spare: Column 2, Per-Column Spare 0 COM INPUT MSA_In_050 E19 Spare: Column 2, Per-Column Spare 0 DIR INPUT MSA_In_050 D20 Spare: Column 2, Per-Column Spare 1 COM INPUT MSA_In_051 E20 Spare: Column 2, Per-Column Spare 1 DIR INPUT MSA_In_051 D21 Spare: Global 4 COM INPUT MSA_In_052 E21 Spare: Global 4 DIR INPUT MSA_In_052 D22 Spare: Global 5 COM INPUT MSA_In_053 E22 Spare: Global 5 DIR INPUT MSA_In_053 D23 Spare: Global 6 COM INPUT MSA_In_054 E23 Spare: Global 6 DIR INPUT MSA_In_054 D24 Spare: Global 7 COM INPUT MSA_In_055 E24 Spare: Global 7 DIR INPUT MSA_In_055 D25 Spare: MSA FPGA 2 Per-FPGA Spare COM INPUT MSA_In_056 E25 Spare: MSA FPGA 2 Per-FPGA Spare DIR INPUT MSA_In_056 D26 Spare: MSA FPGA 6 Per-FPGA Spare COM INPUT MSA_In_057 E26 Spare: MSA FPGA 6 Per-FPGA Spare DIR INPUT MSA_In_057 D27 Spare: MSA FPGA 10 Per-FPGA Spare COM INPUT MSA_In_058 E27 Spare: MSA FPGA 10 Per-FPGA Spare DIR INPUT MSA_In_058 D28 Spare: MSA FPGA 14 Per-FPGA Spare COM INPUT MSA_In_059 E28 Spare: MSA FPGA 14 Per-FPGA Spare DIR INPUT MSA_In_059 D29 Spare: Unrouted 4 COM INPUT MSA_In_060 E29 Spare: Unrouted 4 DIR INPUT MSA_In_060 D30 Spare: Unrouted 5 COM INPUT MSA_In_061 E30 Spare: Unrouted 5 DIR INPUT MSA_In_061 D31 Spare: Unrouted 6 COM INPUT MSA_In_062 E31 Spare: Unrouted 6 DIR INPUT MSA_In_062 D32 Spare: Unrouted 7 COM INPUT MSA_In_063 E32 Spare: Unrouted 7 DIR INPUT MSA_In_063 ---------------------------------------------------------------------- P3: 160-pin E-style DIN connector for Trigger Framework P3 input bus ---------------------------------------------------------------------- (note: 0 <= n <= 3) Pin # Signal Description Dir Identifier ----- ------------------ --- ---------- A1 Subsystem And-Or Input Term 64*n + 32 COM INPUT MSA_In_064 B1 Subsystem And-Or Input Term 64*n + 32 DIR INPUT MSA_In_064 A2 Subsystem And-Or Input Term 64*n + 33 COM INPUT MSA_In_065 B2 Subsystem And-Or Input Term 64*n + 33 COM INPUT MSA_In_065 B3 Subsystem And-Or Input Term 64*n + 34 COM INPUT MSA_In_066 B3 Subsystem And-Or Input Term 64*n + 34 DIR INPUT MSA_In_066 A4 Subsystem And-Or Input Term 64*n + 35 COM INPUT MSA_In_067 B4 Subsystem And-Or Input Term 64*n + 35 DIR INPUT MSA_In_067 A5 Subsystem And-Or Input Term 64*n + 36 COM INPUT MSA_In_068 B5 Subsystem And-Or Input Term 64*n + 36 DIR INPUT MSA_In_068 A6 Subsystem And-Or Input Term 64*n + 37 COM INPUT MSA_In_069 B6 Subsystem And-Or Input Term 64*n + 37 DIR INPUT MSA_In_069 A7 Subsystem And-Or Input Term 64*n + 38 COM INPUT MSA_In_070 B7 Subsystem And-Or Input Term 64*n + 38 DIR INPUT MSA_In_070 A8 Subsystem And-Or Input Term 64*n + 39 COM INPUT MSA_In_071 B8 Subsystem And-Or Input Term 64*n + 39 DIR INPUT MSA_In_071 A9 Subsystem And-Or Input Term 64*n + 40 COM INPUT MSA_In_072 B9 Subsystem And-Or Input Term 64*n + 40 DIR INPUT MSA_In_072 A10 Subsystem And-Or Input Term 64*n + 41 COM INPUT MSA_In_073 B10 Subsystem And-Or Input Term 64*n + 41 DIR INPUT MSA_In_073 A11 Subsystem And-Or Input Term 64*n + 42 COM INPUT MSA_In_074 B11 Subsystem And-Or Input Term 64*n + 42 DIR INPUT MSA_In_074 A12 Subsystem And-Or Input Term 64*n + 43 COM INPUT MSA_In_075 B12 Subsystem And-Or Input Term 64*n + 43 DIR INPUT MSA_In_075 A13 Subsystem And-Or Input Term 64*n + 44 COM INPUT MSA_In_076 B13 Subsystem And-Or Input Term 64*n + 44 DIR INPUT MSA_In_076 A14 Subsystem And-Or Input Term 64*n + 45 COM INPUT MSA_In_077 B14 Subsystem And-Or Input Term 64*n + 45 DIR INPUT MSA_In_077 A15 Subsystem And-Or Input Term 64*n + 46 COM INPUT MSA_In_078 B15 Subsystem And-Or Input Term 64*n + 46 DIR INPUT MSA_In_078 A16 Subsystem And-Or Input Term 64*n + 47 COM INPUT MSA_In_079 B16 Subsystem And-Or Input Term 64*n + 47 DIR INPUT MSA_In_079 A17 Subsystem And-Or Input Term 64*n + 48 COM INPUT MSA_In_080 B17 Subsystem And-Or Input Term 64*n + 48 DIR INPUT MSA_In_080 A18 Subsystem And-Or Input Term 64*n + 49 COM INPUT MSA_In_081 B18 Subsystem And-Or Input Term 64*n + 49 DIR INPUT MSA_In_081 A19 Subsystem And-Or Input Term 64*n + 50 COM INPUT MSA_In_082 B19 Subsystem And-Or Input Term 64*n + 50 DIR INPUT MSA_In_082 A20 Subsystem And-Or Input Term 64*n + 51 COM INPUT MSA_In_083 B20 Subsystem And-Or Input Term 64*n + 51 DIR INPUT MSA_In_083 A21 Subsystem And-Or Input Term 64*n + 52 COM INPUT MSA_In_084 B21 Subsystem And-Or Input Term 64*n + 52 DIR INPUT MSA_In_084 A22 Subsystem And-Or Input Term 64*n + 53 COM INPUT MSA_In_085 B22 Subsystem And-Or Input Term 64*n + 53 DIR INPUT MSA_In_085 A23 Subsystem And-Or Input Term 64*n + 54 COM INPUT MSA_In_086 B23 Subsystem And-Or Input Term 64*n + 54 DIR INPUT MSA_In_086 A24 Subsystem And-Or Input Term 64*n + 55 COM INPUT MSA_In_087 B24 Subsystem And-Or Input Term 64*n + 55 DIR INPUT MSA_In_087 A25 Subsystem And-Or Input Term 64*n + 56 COM INPUT MSA_In_088 B25 Subsystem And-Or Input Term 64*n + 56 DIR INPUT MSA_In_088 A26 Subsystem And-Or Input Term 64*n + 57 COM INPUT MSA_In_089 B26 Subsystem And-Or Input Term 64*n + 57 DIR INPUT MSA_In_089 A27 Subsystem And-Or Input Term 64*n + 58 COM INPUT MSA_In_090 B27 Subsystem And-Or Input Term 64*n + 58 DIR INPUT MSA_In_090 A28 Subsystem And-Or Input Term 64*n + 59 COM INPUT MSA_In_091 B28 Subsystem And-Or Input Term 64*n + 59 DIR INPUT MSA_In_091 A29 Subsystem And-Or Input Term 64*n + 60 COM INPUT MSA_In_092 B29 Subsystem And-Or Input Term 64*n + 60 DIR INPUT MSA_In_092 A30 Subsystem And-Or Input Term 64*n + 61 COM INPUT MSA_In_093 B30 Subsystem And-Or Input Term 64*n + 61 DIR INPUT MSA_In_093 A31 Subsystem And-Or Input Term 64*n + 62 COM INPUT MSA_In_094 B31 Subsystem And-Or Input Term 64*n + 62 DIR INPUT MSA_In_094 A32 Subsystem And-Or Input Term 64*n + 63 COM INPUT MSA_In_095 B32 Subsystem And-Or Input Term 64*n + 63 DIR INPUT MSA_In_095 C1 GROUND C2 +3.3V LOWER C3 GROUND C4 +3.3V LOWER C5 -4.5V LOWER C6 GROUND C7 +3.3V LOWER C8 GROUND C9 +5.0V LOWER C10 GROUND C11 +3.3V LOWER C12 GROUND C13 +3.3V LOWER C14 GROUND C15 -4.5V LOWER C16 GROUND C17 +3.3V LOWER C18 GROUND C19 +5.0V LOWER C20 +3.3V LOWER C21 GROUND C22 +3.3V LOWER C23 GROUND C24 -4.5V LOWER C25 GROUND C26 +3.3V LOWER C27 GROUND C28 +5.0V LOWER C29 +3.3V LOWER C30 GROUND C31 +3.3V LOWER C32 GROUND D1 Subsystem Gap COM INPUT MSA_In_096 E1 Subsystem Gap DIR INPUT MSA_In_096 D2 Subsystem Strobe to AOITs 64*n + (32:47) COM INPUT MSA_In_097 E2 Subsystem Strobe to AOITs 64*n + (32:47) DIR INPUT MSA_In_097 D3 Spare: Column 3, Per-Column Spare 0 COM INPUT MSA_In_098 E3 Spare: Column 3, Per-Column Spare 0 DIR INPUT MSA_In_098 D4 Spare: Column 3, Per-Column Spare 1 COM INPUT MSA_In_099 E4 Spare: Column 3, Per-Column Spare 1 DIR INPUT MSA_In_099 D5 Spare: Global 8 COM INPUT MSA_In_100 E5 Spare: Global 8 DIR INPUT MSA_In_100 D6 Spare: Global 9 COM INPUT MSA_In_101 E6 Spare: Global 9 DIR INPUT MSA_In_101 D7 Spare: Global 10 COM INPUT MSA_In_102 E7 Spare: Global 10 DIR INPUT MSA_In_102 D8 Spare: Global 11 COM INPUT MSA_In_103 E8 Spare: Global 11 DIR INPUT MSA_In_103 D9 Spare: MSA FPGA 3 Per-FPGA Spare COM INPUT MSA_In_104 E9 Spare: MSA FPGA 3 Per-FPGA Spare DIR INPUT MSA_In_104 D10 Spare: MSA FPGA 7 Per-FPGA Spare COM INPUT MSA_In_105 E10 Spare: MSA FPGA 7 Per-FPGA Spare DIR INPUT MSA_In_105 D11 Spare: MSA FPGA 11 Per-FPGA Spare COM INPUT MSA_In_106 E11 Spare: MSA FPGA 11 Per-FPGA Spare DIR INPUT MSA_In_106 D12 Spare: MSA FPGA 15 Per-FPGA Spare COM INPUT MSA_In_107 E12 Spare: MSA FPGA 15 Per-FPGA Spare DIR INPUT MSA_In_107 D13 Spare: Unrouted 8 COM INPUT MSA_In_108 E13 Spare: Unrouted 8 DIR INPUT MSA_In_108 D14 Spare: Unrouted 9 COM INPUT MSA_In_109 E14 Spare: Unrouted 9 DIR INPUT MSA_In_109 D15 Spare: Unrouted 10 COM INPUT MSA_In_110 E15 Spare: Unrouted 10 DIR INPUT MSA_In_110 D16 Spare: Unrouted 11 COM INPUT MSA_In_111 E16 Spare: Unrouted 11 DIR INPUT MSA_In_111 D17 Subsystem Gap COM INPUT MSA_In_112 E17 Subsystem Gap DIR INPUT MSA_In_112 D18 Subsystem Strobe to AOITs 64*n + (48:63) COM INPUT MSA_In_113 E18 Subsystem Strobe to AOITs 64*n + (48:63) DIR INPUT MSA_In_113 D19 Spare: Column 4, Per-Column Spare 0 COM INPUT MSA_In_114 E19 Spare: Column 4, Per-Column Spare 0 DIR INPUT MSA_In_114 D20 Spare: Column 4, Per-Column Spare 1 COM INPUT MSA_In_115 E20 Spare: Column 4, Per-Column Spare 1 DIR INPUT MSA_In_115 D21 Spare: Global 12 COM INPUT MSA_In_116 E21 Spare: Global 12 DIR INPUT MSA_In_116 D22 Spare: Global 13 COM INPUT MSA_In_117 E22 Spare: Global 13 DIR INPUT MSA_In_117 D23 Spare: Global 14 COM INPUT MSA_In_118 E23 Spare: Global 14 DIR INPUT MSA_In_118 D24 Spare: Global 15 COM INPUT MSA_In_119 E24 Spare: Global 15 DIR INPUT MSA_In_119 D25 Spare: MSA FPGA 4 Per-FPGA Spare COM INPUT MSA_In_120 E25 Spare: MSA FPGA 4 Per-FPGA Spare DIR INPUT MSA_In_120 D26 Spare: MSA FPGA 8 Per-FPGA Spare COM INPUT MSA_In_121 E26 Spare: MSA FPGA 8 Per-FPGA Spare DIR INPUT MSA_In_121 D27 Spare: MSA FPGA 12 Per-FPGA Spare COM INPUT MSA_In_122 E27 Spare: MSA FPGA 12 Per-FPGA Spare DIR INPUT MSA_In_122 D28 Spare: MSA FPGA 16 Per-FPGA Spare COM INPUT MSA_In_123 E28 Spare: MSA FPGA 16 Per-FPGA Spare DIR INPUT MSA_In_123 D29 Spare: Unrouted 12 COM INPUT MSA_In_124 E29 Spare: Unrouted 12 DIR INPUT MSA_In_124 D30 Spare: Unrouted 13 COM INPUT MSA_In_125 E30 Spare: Unrouted 13 DIR INPUT MSA_In_125 D31 Spare: Unrouted 14 COM INPUT MSA_In_126 E31 Spare: Unrouted 14 DIR INPUT MSA_In_126 D32 Spare: Unrouted 15 COM INPUT MSA_In_127 E32 Spare: Unrouted 15 DIR INPUT MSA_In_127 xXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxXxX From the description of the Receiving Terms L1 And-Or Network Terms to the L1 Framework Pin Out ------------------------------------------------------------- Pair Pin Number - Function Pin Number - Function ---- ------------------------ ----------------------- 1 1 Term_0 Non_Inv 2 Term_0 Inv 2 3 Term_1 Non_Inv 4 Term_1 Inv 3 5 Term_2 Non_Inv 6 Term_2 Inv 4 7 Term_3 Non_Inv 8 Term_3 Inv 5 9 Term_4 Non_Inv 10 Term_4 Inv 6 11 Term_5 Non_Inv 12 Term_5 Inv 7 13 Term_6 Non_Inv 14 Term_6 Inv 8 15 Term_7 Non_Inv 16 Term_7 Inv 9 17 Term_8 Non_Inv 18 Term_8 Inv 10 19 Term_9 Non_Inv 20 Term_9 Inv 11 21 Term_10 Non_Inv 22 Term_10 Inv 12 23 Term_11 Non_Inv 24 Term_11 Inv 13 25 Term_12 Non_Inv 26 Term_12 Inv 14 27 Term_13 Non_Inv 28 Term_13 Inv 15 29 Term_14 Non_Inv 30 Term_14 Inv 16 31 Term_15 Non_Inv 32 Term_15 Inv 17 33 Gap Non_Inv 34 Gap Inv 18 35 Gnd 36 Gnd 19 37 Strobe Non_Inv 38 Strobe Inv 20 39 Gnd 40 Gnd