***************************** * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * * and * * * * Level 2 Trigger Framework * * * * Gated Scaler FPGA * * * ***************************** Original: 2-JUN-1997 Latest: 8-NOV-2000 Introduction ------------ The Gated Scaler FPGA is used in all MSA FPGA locations on the Gated Scaler cards (which are instances of the Scaler Module). Each Gated Scaler FPGA has the following input and output connections: 1. On-Card Bus (including High-Quality Timing Signals). 2. High-Speed Readout Interface 3. 32 Common Control Signals (these are Main Signal Array (MSA) Input Signals). 4. 6 Unique (per-FPGA) Control Signals (these are also MSA Input Signals). 5. 32 Scaler Output Signals (these are MSA Output Signals). As with the Per-Bunch Scaler FPGA, the idea is to make a single configuration with sufficient flexibility to support known and reasonably forseeable Gated Scaling needs. Unlike the Per-Bunch Scaler, however, the gating needs of each Scaler Channel are less well-known The general idea behind this FPGA is to make a single configuration with a reasonable amount of flexibility, to support known and reasonably forseeable Per-Bunch Scaling needs, without adding unnecessary complexity. Recall that special FPGA configurations, while undesirable, can be used to implement Per-Bunch Scaling functions which are not supported by this FPGA configuration. Questions to be resolved ------------------------ 1. What about P5 Global I/O? Operation--General Comments --------------------------- The general-purpose Gated Scaler must be a very flexible scaler, with extensive control over both gating and loading the scaler. It is used in all scaling applications except Per-bunch Scaling. Some examples of functions this FPGA must perform are: 1. Tick scaling: count from 1 to 159, then return to 1, using only P1 Timing signals for clock, gate and reload. 2. Turn scaling: count up from 1, using only P1 Timing signals for clock and gate. 3. General gated scaling: count up from 0, using a P1 Timing signal for clock, and various combinations of external signals for gate. 4. Timer: count time between events, using P1 Timing signals for clock and gate, and various combinations of external signals for reload. All of these types of scalers must be resettable via TCC, using the (yet to be determined) standard scaler reset mechanism. Note that this reset is different from the "reload" function mentioned above. The Gated Scaler FPGA is composed of the following elements: 1. On-Card Bus Interface 2. High-Speed Readout Interface 3. Common Control Signal Gate Selection and Processing Logic 4. Common Control Signal Load Selection and Processing Logic 5. Four Separate Scaler Channels, each consisting of A. Channel Gate Processing Logic B. Channel Load Processing Logic C. 32-bit Loadable and Resettable Scaler D. Beam Crossing History Shift Register E. Monitor Data Capture and Readout F. 32-bit Count Electrical Format Output (Channel 0 only) G. High-Speed Data Capture and Readout (Channel 0 only) Each element is described below. 1. On-Card Bus Interface This is the standard On-Card Bus Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. 2. High-Speed Readout Interface This is the standard High-Speed Readout Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. 3. Common Control Signal Gate Selection and Processing Logic The 32 Common Control Signals can be used in the gate generation logic of all Scaler Channels on this FPGA. The Common Control Signal Gate Selection and Processing Logic for the Gated Scaler FPGA is identical to that used in the Per-Bunch Scaler FPGA. A detailed description of that logic is found in that FPGA's documentation, while a shorter summary of this logic is below. Up to 4 (one from each "set" of 8) of the 32 Common Control Signals can be used as all or part of the gate of each Scaler Channel on this FPGA. These signals can be either ANDed or ORed together programmable inversion on any or all to form the Common Gate Signal. The Common Gate Signal can also be forced LOW or HIGH by TCC. Note that, as is the case with the Per-Bunch Scaler FPGA, all four Scaler Channels share a single Common Control Signal Gate Selection and Processing Logic unit. All channels can use the Common Scaler Gate in their gate generation logic. 4. Common Control Signal Load Selection and Processing Logic The 32 Common Control Signals can also be combined (independently from the combination described above) and used in the synchronous load generation logic of all Scaler Channels. The combination logic is identical to that described above. 5. Four Separate Scaler Channels This FPGA has four separate, similar (but not identical) Scaler Channels. Each Scaler Channel consists of the following elements: A. Channel Gate Processing Logic B. Channel Load Processing Logic C. 32-bit Loadable and Resettable Scaler D. Beam Crossing History Shift Register E. Monitor Data Capture and Readout F. 32-bit Count Electrical Format Output (Channel 0 only) G. High-Speed Data Capture and Readout (Channel 0 only) 5.A Channel Gate Processing Logic The Gate Logic for each Scaler Channel is very flexible. In addition to the Common Scaler Gate described above, the gate for each Scaler Channel can be built from Individual Control Signals and High-Quality Timing Signals, as described below. All Scaler Channels on this FPGA have access to 6 Individual Control Signals (these are the "Per-FPGA" Control Signals described in the Scaler Module documentation--note that every MSA FPGA on the Scaler Module receives DIFFERENT Per-FPGA Control Signals). Any number of the 6 Individual Control Signals can be ANDed or ORed together, with programmable inversion on any or all, to form the Channel ICS Gate. Additionally, HQ_TS(1) can be used as the Channel Timing Signal Gate. Finally, the Carry Enable Output, ANDed together with the Channel Gate, from each Scaler Channel is available to the next Scaler Channel, allowing simple construction of 64-bit (or even larger) Scalers. Note that at present Channel 0 does not accept a Carry signal input. Channel 3's Carry Gate could be wrapped around back to Channel 0, but this is not implemented right now. These gate components can be combined, under TCC control, to produce the Scaler Channel Gate. The possibilities are: Common Scaler Gate OR Channel ICS Gate OR Channel Timing Signal Gate OR any 2 or 3 of the above ANDed together OR Channel CEO AND Scaler Channel Gate OR LOW OR HIGH 5.B Channel Load Processing Logic Several scaling functions require a real-time reloading of the 32-bit Scaler with a specified value. Examples of this are turn counting and inter-event timing. Note that this function is separate from the overall Scaler Reset mechanism, which all Scaler Channels must also have. The Scaler Channel Load function must also be flexible, and in fact receives processing similar to the Scaler Channel Gate. The 32 Common Control Signals can be combined to form the Common Scaler Load Signal. The Individual Control Signals can be combined, as in (but independently of) the Scaler Channel Gate Processing Logic, Logic, to form the Channel ICS Load. Also, HQ_TS(1) can be used as the Channel Timing Signal Load. These signals can then be combined to form the Scaler Channel Load. The possibilities are: Common Scaler Load OR Channel ICS Load OR Channel Timing Signal Load OR any 2 or 3 of the above ANDed together OR LOW OR HIGH The value to be loaded is programmed by TCC into a Scaler Channel Load Register. Note that this is a SYNCHRONOUS load. The Scaler Channel will be reloaded on the rising edge of the Scaler Channel Clock. 5.C 32-bit Loadable and Resettable Scaler The actual scaling function of each Scaler Channel is performed by a standard 32-bit (synchronously) loadable and (synchronously) resettable scaler. The outputs of this Scaler Channel are the 32-bit Scaler Channel Count, and also the CEO ANDed with the Scaler Channel Gate, used for concatenating multiple Scaler Channels to produce 64-bit (or larger) Scalers. Note that both the reset and load signals are passed through the Beam Crossing History Shift Register with the same latency as the data which is being scaled. Note also that since the scaler is a LogiBlox scaler, the clock enable must be high in order for the load or reset to take place. This is guaranteed by making the load and reset signals inputs to a multiple input OR controlling the clock enable pin. (The third and final input to the OR is the Scaler Channel Gate.) 5.D Beam Crossing History Shift Register The basic principle of the Beam Crossing History Shift Register (BXHSR) is to delay the scaler value to be readout until the readout signal arrives. However, in order to reduce the resources required by this FPGA, some simplifications can be made. Specifically, the BXHSR can be put before the 32-bit Scaler described in 5.C. The BXHSR thus records the clock enable signal for each 32-bit scaler rather than the actual output of the scaler. At present, it is effectively the third stage of the BXHSR which is tapped (in practice it is the second state, but the scaler itself acts as a third stage). The latency (delay from Triggered tick to the Capture Monitor/HSRO Data signals) is programmable by TCC (within a limited range, currently TCC can program 0 to 7 which results in an actual latency of 3 to 10). Note that the Carry Gate Input is NOT passed through the BXHSR since Scaler Channels which have been concatenated should all increment at the same time. 5.E Monitor Data Capture and Readout The 32-bit Count from each Scaler Channel is available for Monitor Data Readout by TCC (via VME). This is done using the standard Monitor Data Capture and Readout techniques, which are described in detail elsewhere. 5.F 32-bit Count Electrical Format Output (Channel 0 only) The 32-bit Count from Scaler Channel 0 is available on output pins of this FPGA. Two selected FPGA's on the Gated Scaler Module have these electrical outputs routed to the P4 front panel output connector. 5.G High-Speed Data Capture and Readout (Channel 0 only) The 32-bit Count from Scaler Channel 0 is also available for High-Speed Readout. This is a standard High-Speed Readout element, which is described in detail elsewhere. Programming Interface --------------------- The Gated Scaler FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Enable Timing Signal Reset 3 R/W Force Scaler Reset 8 R/W Common Gate: CCS Set 0 Mux Control Register 9 R/W Common Gate: CCS Set 1 Mux Control Register 10 R/W Common Gate: CCS Set 2 Mux Control Register 11 R/W Common Gate: CCS Set 3 Mux Control Register 12 R/W Common Gate: Combination Logic Control Register 16 R/W Common Load: CCS Set 0 Mux Control Register 17 R/W Common Load: CCS Set 1 Mux Control Register 18 R/W Common Load: CCS Set 2 Mux Control Register 19 R/W Common Load: CCS Set 3 Mux Control Register 20 R/W Common Load: Combination Logic Control Register 24 R Scaler Channel 0: HSRO State 25 R/W Scaler Channel 0: HSRO Terminal Count 26 R Scaler Channel 0: HSRO Current Count 128 R/W Scaler Channel 0: Load Value LSWord 129 R/W Scaler Channel 0: Load Value MSWord 130 R/W Scaler Channel 0: Gate Control Register 131 R/W Scaler Channel 0: Load Control Register 132 R/W Scaler Channel 0: Tick History SR MUX Control 133 R Scaler Channel 0: Monitor Register LSWord 134 R Scaler Channel 0: Monitor Register MSWord 136 R/W Scaler Channel 1: Load Value LSWord 137 R/W Scaler Channel 1: Load Value MSWord 138 R/W Scaler Channel 1: Gate Control Register 139 R/W Scaler Channel 1: Load Control Register 140 R/W Scaler Channel 1: Tick History SR MUX Control 141 R Scaler Channel 1: Monitor Register LSWord 142 R Scaler Channel 1: Monitor Register MSWord 143 R/W Scaler Channel 1: Scaler Gate MUX Control 144 R/W Scaler Channel 2: Load Value LSWord 145 R/W Scaler Channel 2: Load Value MSWord 146 R/W Scaler Channel 2: Gate Control Register 147 R/W Scaler Channel 2: Load Control Register 148 R/W Scaler Channel 2: Tick History SR MUX Control 149 R Scaler Channel 2: Monitor Register LSWord 150 R Scaler Channel 2: Monitor Register MSWord 151 R/W Scaler Channel 2: Scaler Gate MUX Control 152 R/W Scaler Channel 3: Load Value LSWord 153 R/W Scaler Channel 3: Load Value MSWord 154 R/W Scaler Channel 3: Gate Control Register 155 R/W Scaler Channel 3: Load Control Register 156 R/W Scaler Channel 3: Tick History SR MUX Control 157 R Scaler Channel 3: Monitor Register LSWord 158 R Scaler Channel 3: Monitor Register MSWord 159 R/W Scaler Channel 3: Scaler Gate MUX Control The bit allocation in each of these registers is: Chip Control Status Register LSW (Register Address 0) Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 3:15 --- not allocated The Chip Status Register MSW is currently unused. Enable Timing Signal Reset Bit Access Contents --- ------ -------- 0 R/W Enable Timing Signal Reset for Channel 0 Scaler 1 R/W Enable Timing Signal Reset for Channel 1 Scaler 2 R/W Enable Timing Signal Reset for Channel 2 Scaler 3 R/W Enable Timing Signal Reset for Channel 3 Scaler 15:4 R/W not allocated Force Scaler Reset Bit Access Contents --- ------ -------- 0 R/W Force Reset for Channel 0 Scaler 1 R/W Force Reset for Channel 1 Scaler 2 R/W Force Reset for Channel 2 Scaler 3 R/W Force Reset for Channel 3 Scaler 15:4 R/W not allocated Common Control Signal Set Mux Control Registers (Gate and Load) Bit Access Contents --- ------ -------- 2:0 R/W Input Select (: Select Common Control Signal 8*n + m) 3 R/W Mux Input Invert ('1': selected CCS is inverted) 4 R/W Mux Enable ('0': this CCS Set is ignored in the CCS processing '1': Mux Output = selected CCS / inverted sel CCS) 15:5 R/W not allocated Scaler Gate (Load) Combination Control Registers Bit Access Contents --- ------ -------- 0 R/W Output Invert ('0': Output = AND of all selected inputs '1': Output = NAND of all selected inputs) 1 R/W Common Scaler Gate (Load) Enable ('0': Common Scaler Gate (Load) forced LOW) 15:2 R/W not allocated Notes: To OR the selected Common Control Signals, invert all selected Common Control Signals via the CCS Mux Control Registers, and select the NAND flavor of Scaler Common Gate (Load) combination logic via this Control Register. To force Common Gate (Load) LOW for all Scaler Channels, set Common Gate (Load) Enable LOW. To force Common Gate (Load) HIGH for all Scaler Channels, disable all 4 CCS Set Muxes and set Common Scaler Gate (Load) Enable HIGH. Scaler Channel 0 HSRO State Bit Access Contents --- ------ -------- 0 R HSRO_DCE_IN* 1 R HSRO_DCE_OUT* 2 R Enable_HSRO_Data 15:3 R not allocated Scaler Channel 0 HSRO Terminal Count Bit Access Contents --- ------ -------- 3:0 R/W Number of Words for High-Speed Readout (MUST be greater than 0 if chip HSRO is enabled) 14:4 R/W not allocated 15 R/W Enable HSRO from this Chip (0: DCE_In* passes directly through to DCE_Out* 1: DCE_Out* is generated by the terminal count comparator) Scaler Channel Gate Control Register Bit Access Contents --- ------ -------- 0 R/W Common Gate Enable ('1': Enable the Common Gate for this Channel) 1 R/W Timing Signal Gate Enable ('1': Enable HQ_TS(1) as the Timing Signal Gate) 2 R/W Individual Control Signal 0 Invert ('1': Invert Individual Control Signal 0) 3 R/W Individual Control Signal 0 Enable ('1': ICS(0) (or NOT ICS(0), depending on the ICS(0) Invert control) is Enabled) 4 R/W Individual Control Signal 1 Invert 5 R/W Individual Control Signal 1 Enable 6 R/W Individual Control Signal 2 Invert 7 R/W Individual Control Signal 2 Enable 8 R/W Individual Control Signal 3 Invert 9 R/W Individual Control Signal 3 Enable 10 R/W Individual Control Signal 4 Invert 11 R/W Individual Control Signal 4 Enable 12 R/W Individual Control Signal 5 Invert 13 R/W Individual Control Signal 5 Enable 14 R/W ICS Gate Invert ('0': ICS Gate = AND of all Enabled ICS '1': ICS Gate = NAND of all Enabled ICS 15 R/W Channel Overall Enable ('0': Scaler Channel disabled '1': Scaler Channel enabled Notes: If Channel Overall Enable is LOW, Scaler Channel Gate is forced LOW. If Channel Overall Enable is HIGH, Scaler Channel Gate is the AND of the selected gate sub-components (Common Gate, Timing Signal Gate, and ICS Gate). ICS Gate is the AND (or NAND) of the enabled Individual Control Signals (any or all of which may be programmably inverted). To OR the selected Individual Control Signals, invert all selected Individual Control Signals and select the NAND ICS Gate processing. To force the Scaler Channel Gate HIGH, set the Channel Overall Enable HIGH but leave all of the individual sub-component Enables and the ICS Gate Invert LOW. Scaler Channel Load Control Register Bit Access Contents --- ------ -------- 0 R/W Common Load Enable ('1': Enable the Common Load) 1 R/W Timing Signal Load Enable ('1': Enable HQ_TS(1) as the Timing Signal Load) 2 R/W Individual Control Signal 0 Invert ('1': Invert Individual Control Signal 0) 3 R/W Individual Control Signal 0 Enable ('1': ICS(0) (or NOT ICS(0), depending on the ICS(0) Invert control) is Enabled) 4 R/W Individual Control Signal 1 Invert 5 R/W Individual Control Signal 1 Enable 6 R/W Individual Control Signal 2 Invert 7 R/W Individual Control Signal 2 Enable 8 R/W Individual Control Signal 3 Invert 9 R/W Individual Control Signal 3 Enable 10 R/W Individual Control Signal 4 Invert 11 R/W Individual Control Signal 4 Enable 12 R/W Individual Control Signal 5 Invert 13 R/W Individual Control Signal 5 Enable 14 R/W ICS Load Invert ('0': ICS Load = AND of all Enabled ICS '1': ICS Load = NAND of all Enabled ICS 15 R/W Channel Overall Load Enable ('0': Scaler Channel Load disabled '1': Scaler Channel Load enabled Notes: If Channel Overall Load Enable is LOW, Scaler Channel Load is forced LOW. If Channel Overall Load Enable is HIGH, Scaler Channel Load is the AND of the selected gate sub-components (Common Load, Timing Signal Load, and ICS Load). ICS Load is the AND (or NAND) of the enabled Individual Control Signals (any or all of which may be programmably inverted). To OR the selected Individual Control Signals, invert all selected Individual Control Signals and select the NAND ICS Load processing. To force the Scaler Channel Load HIGH, set the Channel Overall Enable Load HIGH but leave all of the individual sub-component Enables and the ICS Load Invert LOW. Scaler Channel Tick History Shift Register Control Reg Bit Access Contents --- ------ -------- 2:0 R/W Depth in stage 1 of BXHSR 15:3 R/W unallocated Scaler Channel Gate MUX Control Bit Access Contents --- ------ -------- 0 R/W Concatenate Previous Channel ('0': Scaler Channel Gate is as configured in Scaler Channel Gate Control Register '1': Scaler Channel Gate is previous Channel CEO ANDed with previous Scaler Channel Gate) 15:1 R/W not allocated