List of Individual Scalers
                 ------------------------------


                                           Original Rev.  30-APRIL-1998
                                        Most Recent Rev.  18-APRIL-2003



The purpose of this file is to list all of the scalers that are not
directly associated with a given AOIT, Specific Trigger, or Geographic
Section.  Many of the scalers described here will be implemented on
Gated SM cards.  The description of each scaler should include:
does it need HSRO or electrical outputs, does it have special conditions
or methods for resetting it.

So far this is just a pile of information be we should organize it by
type of scaler or what card it is on or something.



PBS (Per Bunch Scaler)
---

Exposure Group monitoring on a non per bunch bases.  These 8 scalers,
one for each Exposure Groups, are just the per bunch scaler that
is enabled for all bunches.  Besides giving you a sum check on the 159
per bunch scales these "enabled for the whole turn scalers" give you 8
simple numbers to monitor so you can have an overall feel for what is
going on with the exposure groups.  Recall that the per bunch scalers
are 80 per card.  Two cards are used per item.  The first card is
ticks 1:80 and the second card is ticks 81:159 and the final enabled
for all ticks scaler.  Exposure Group monitoring on a non per bunch bases.
Electrical Output = NO, HSRO = NO



AONM (And-Or Network Module)
----

And-Or Fired Diagnostic,   4 Gated Scaler channels for diagnostics of
the And-Or Input Terms.  The gates of these 4 scalers are generated by
the Exposure Group And-Or Modules.  The idea of these 4 scalers is to
allow overlap rate measurement of selected And-Or Network Input Terms.
This can not be done with the scalers on the And-Or cards themselves
because you might be looking for the overlap of And-Or Input Terms
where one is in the lower half and the other is in the upper half.  By
using a Gated SM the final "ANDing" is done right in the Gated SM FPGA.

We will use the FPGA site #4 on both of the And-Or Exposure Group
cards to generate the gate signals to control these diagnostic
scalers.  This AONM FPGA drives MSA_Out 15:12.  The 4 gated scalers
will be on 2 FPGA's on the SM card in slot 19 of M123B.  The layout
is:

And-Or Diagnostic Scaler #0    this is scaler #1 on FPGA #1
  AONM Exp Grp 127:0   MSA_Out_12  ->  MSA_In_6  FPGA #1 per FPGA signal 2
  AONM Exp Grp 255:128 MSA_Out_12  ->  MSA_In_7  FPGA #1 per FPGA signal 3

And-Or Diagnostic Scaler #1    this is scaler #2 on FPGA #1
  AONM Exp Grp 127:0   MSA_Out_13  ->  MSA_In_8  FPGA #1 per FPGA signal 4
  AONM Exp Grp 255:128 MSA_Out_13  ->  MSA_In_9  FPGA #1 per FPGA signal 5

And-Or Diagnostic Scaler #2    this is scaler #1 on FPGA #2
  AONM Exp Grp 127:0   MSA_Out_14  ->  MSA_In_22  FPGA #2 per FPGA signal 2
  AONM Exp Grp 255:128 MSA_Out_14  ->  MSA_In_23  FPGA #2 per FPGA signal 3

And-Or Diagnostic Scaler #3    this is scaler #2 on FPGA #2
  AONM Exp Grp 127:0   MSA_Out_15  ->  MSA_In_24  FPGA #2 per FPGA signal 4
  AONM Exp Grp 255:128 MSA_Out_15  ->  MSA_In_25  FPGA #2 per FPGA signal 5

To make this useful TCC would have to provide an interface to enable a human
to setup the And-Or Diagnostic Scalers.  Electrical Output = NO,   HSRO = NO



FOM++ (Framework Output Module for L1 Qualifier, L1 Strobe, etc)
-----

FOM Diagnostic    The desire here is to be able to study the overlap
in the firing of L1 Specific Triggers, i.e. to study the fraction of
the time that both Spec Trig "A" AND Spec Trig "B" fire at the same
time.  This is done on the FOM++ card at FPGA site #12.  The current
plan for implementing this is just to load the And-Or FPGA (instead of
the FOM FPGA) at this site and then just use its internal scalers.
Thus there would be no external electrical connections and no use of a
Gated Scaler Module to implement this function.  TCC support for
setting up this And-Or FPGA would be necessary to make this facility
useful.  FOM Diagnostic   Electrical Output = NO,  HSRO = NO




TTS (Tick and Turn Scaler -- using a Gated Scaler Card)
---

Current Geographic Section BX Number,  the Current Tick and Turn count sent
to the Geographic Sections via the SCL.  The Tick scaler is reloaded once
per turn.  This Tick & Turn Scaler is reset as part of the SCL Initialization
process.  This is FPGA #15 on the Gated SM card in slot #21 of M123 Bottom.
Electrical Output = YES, MSA_Out_(31:16,7:0) carry the current tick & turn
number to the SCL Hub-End,    HSRO = YES



Geographic Section L1 Trigger Number, This is a Tick and Turn scaler
that operate in the "Framework Time Zone".  This Tick & Turn scaler
provides the SCL Hub-End with the Geo Section BX Number of the BX
whose L1 decision is being advertised in this frame of SCL date.  This
Tick & Turn scaler contains the FIFO to hold the list of Geo Section
L1 Trig Num's, from the L1 Accepts, that must be sent out when the L2
Decisions are advertised.  This Tick & Turn Scaler is reset as part of
the SCL Initialization process.  This is FPGA #16 on the Gated SM card
in slot #21 of M123 Bottom.  Electrical Output = YES,
MSA_Out_(63:48,39:32) carry the L1 Trig Tick & Turn Num to the SCL
Hub-End,  HSRO = YES



Tick & Turn count NOT Reset by SCL Initialize.  This is FPGA # 14 on the
SM card in slot #21 of M123 Bottom.  Electrical Output = NO,  HSRO = YES


Tick & Turn count reset by TRICS at every SCL Init.
This is #13.  The Turn number of this scaler is served by TCC's
Monitoring Server (e.g. to Trigmon) and measures the time since
TCC has last processed an SCL Initialization request.
Right now this happens only upon explicit message request from COOR,
but will eventually happen automatically following a hardware
request from a front-end over its SCL status cable.
Electrical Output = NO,  HSRO = YES


Tick & Turn count reset by TRICS at every LBN Increment.
This is Fpga #12.  The Turn number of this scaler is served by TCC's
Monitoring Server (e.g. to Trigmon) and measures the time since
TCC has last incremented the Luminosity Block Number.
The LBN is incremented by TCC at least once every minute,
and more often to mark certain occurences (e.g. SCL Init, start_run).
Note that the protocol requires that the LBN be incremented
(and thus this scaler be reset) as part of every SCL Initialize.
Electrical Output = NO,  HSRO = YES

Note: There is one spare TTS Fpga (#11) that gets read out.
      The other 10 TTS Fpgas (#1:10) don't readout.




GS (Gated Scaler)
--

Count of the total number of L1 Accepts issued   This is Scaler #0 of
the Gated Scaler FPGA site #1 on the SM card at slot #19 of the M123
bottom crate.   We will use the L1 Accept Strobe as the gate signal
for this scaler.  It will arrive on MSA_IN_4 and is called  "FPGA #1
per FPGA Control Signal 0"    Electrical Output = NO,  HSRO = YES



Count of the number of L2 Accepts that have been issued.  This is the
same as the count of the number of times that we have sent Control
Data to the L3 system.  This is Scaler #0 of the Gated Scaler FPGA
site #2 on the SM card at slot #19 of the M123 bottom crate.  We will
use the Increment_L3_Trans_Num signal as the gate signal for this
scaler.  Inc_L3_Trans_Num is generated by the L2_Helper and comes out
of the L2_Helper as MSA_Out_13 and is then routed to the patch panel
box output connector #8 pins 7,8.  This gate signal is then cabled to
M123B Slot 19 input MSA_In_20 and is called "FPGA #2 per FPGA Control
Signal 0".   For this scaler: Electrical Output = NO,   HSRO = YES



Count of the total number of L2 Decisions that have been issued, i.e.
the number of times that the L2 FW has cycled.  This is Scaler #0 of
the Gated Scaler FPGA site #3 on the SM card at slot #19 of the M123
bottom crate.  We will use the Send_L2_Decision signal from the
L2_Helper as the gate signal for this scaler.  This signal is
generated in the L2_Helper as MSA_Out_11 and is routed to the patch
panel box output connector #8 pins 3,4.  It is then cabled to M123B
Slot 19 input MSA_In_68 and is called "FPGA #3 per FPGA Control Signal 0".
For this scaler: Electrical Output = NO, HSRO = YES



Count of the Number of Ticks Since the Previous L1_Acpt.
This is Scaler #0 of the Gated Scaler FPGA site #4 on the SM card at
slot #19 of the M123 bottom crate.  The gate to this scaler is always
enabled so this scaler always tries to increment.  This is done by
loading $8000 into this scaler's Gate Control Register.  With each
L1_Acpt this scaler is "reset" by Loading the value zero into it.
This re-loading is caused by a copy of L1_Acpt Strobe which enters on
P3 MSA_In_84  where it becomes Individual Control Signal 0 for scaler
FPGA #4.  This scaler's Load Control Register is set to $8008 so that
an asserted Individual Control Signal 0 will cause a Load of this scaler.
For this scaler: Electrical Output = NO, HSRO = YES



L1 Accept Awaiting L2 Decision Scaler.  This scaler counts the number
of outstanding L1 Accepts, i.e. L1 Accepts that are awaiting their L2
Decisions.  This Scaler also includes comparators to to test if the
number of outstanding L1 Accepts is above any one of 4 different count
thresholds.  The output from two of these comparators is currently
connected as input terms to the And-Or Network.  Details of the
cabling to control the L1AL2 Scaler are in the file:
/l1/framework/hardware/cabling/framework_single_signal_notes.txt
The L1AL2 Scaler is located as FPGA #16 on the Gated Scaler Module
card in slot #19 of the M123 bottom crate.  This FPGA drives
electrical outputs MSA_Out_(47:32) and the 4 comparator outputs are on
MSA_Out_(35:32).  HSRO = Yes