***************************** * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * * and * * * * Level 2 Trigger Framework * * * * L1 Awaitng L2 FPGA * * * ***************************** Original: 27-APR-2000 Current: 18-OCT-2000 Introduction ------------ The L1AL2 FPGA keeps track of the number of L1 Accepts which are awaiting L2 Decisions. It is implemented for FPGA 15 or 16 of a Scaler Module. In particular, it is used in M123 Bottom, Slot 19 FPGA 16. It has the following input and output connections: 1. On-Card Bus (including High-Quality Timing Signals) 2. L1 Accept 3. L2 Decision 4. 4 Comparator Outputs Functionality ------------- The L1AL2 FPGA is composed of the following elements: 1. On-Card Bus 2. 5 Bit Outstanding Decision Scaler 3. Programable Comparators 4. Histogram Generator 5. Data Capture and Readout a. HSRO b. Monitor Each element is described below: 1. On-Card Bus Interface This is the standard On-Card Bus Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. 2. 5 Bit Outstanding Decision Scaler This is an up-down counter which goes from 0 to 16. (The counter will be capable of counting to 31, but values above 16 should never be reached during normal running.) It increments with every L1 Accept and decrements with every L2 Decision. The L1 Accept and L2 Decision signals are used both to control whether the counter increments or decrements and as the clock enable; the counter is clocked by the usual Tick Clock. The scaler can be synchronously reset via TCC and P1 TS (15). The scaler should be reset when there is an SCL Initialize, but it is assumed that TCC will take care of this using the one of the standard scaler reset mechanisms. NB For a Logiblox counter the clock enable must be high during a synchoronous reset; the hardware takes this into account. 3. Programable Comparators The output of the Outstanding Decision Scaler is fed to 4 greater-than comparators; the comparison values are set by TCC. The outputs of the comparators are available as MSA Outputs for use as And-Or Input Terms. 4. Histogram Generator The Histogram Generator keeps track of how many Beam Crossings (?) each Scaler value is asserted for. This is done via a decoder with ?? bit scalers on each of the output bits. The clock for these scalers is the usual Tick Clock (?) with the decoder bits acting as the clock enables. The scalers can be synchronously reset via TCC and P1 TS (15). NB For a Logiblox counter the clock enable must be high during a synchoronous reset. Because of the numerous questions remaining regarding the details of the Histogram Generator, it is not yet implemented. 10-May-2000 Jim indicated that a sampling rate of not more than 500 Hz would probably be ok. fall-2000 Jim has agreed to seventeen, 16-bit scalers that increment at 1 kHz 5. Data Capture and Readout a. High Speed Readout The standard HSRO Interface and Beam Crossing History Shift Register are used. The first word provided for HSRO is the same as the Monitor Data word (see below). If a second word is read out, it will be all 0. (At present, only 2 words are provided for HSRO.) Note that the timing is somewhat different in this card because the information being captured is only available some number of ticks after the L1 Accept. In general, if only one time slice is provided, it is the third stage of the BXHSR which is tapped; precisely which time slice is read out is then determined by the latency programmed by TCC. However in the case of this FPGA the information to be captured must be made available as quickly as possible in order to be present before the Capture signal arrives. Thus, the first stage of the BXHSR is tapped in this design. TCC can still control the latency/which time slice is read out, but this modification makes it possible to readout information around the time of the triggered tick. With the current setup (i.e. Capture programmed to come 1 tick after the L1 Accept), a BXHSR latency of 1 captures the first tick for which the scaler incrment associated with the L1 Accept is visible. A BXHSR latency of 0 captures the second tick with the scaler increment, and a BXHSR of 2 captures the last tick before the scaler increment appears. b. Monitor Readout The L1AL2 needs to provide for monitor readout: o the scaler value o the output of each of the comparators o the histogram information The usual capture monitor data mechanism is used. As with the HSRO data, the data is passed through the usual BXHSR before being captured. Note that the second HSRO word (forced to be 0) is not currently provided for monitor readout. Cabling ------- All of the input and output connections at the card level depend on whether the design is used in FPGA 15 or 16. THE Card THE Card MSA In/Out MSA In/Out Signal FPGA 15 FPGA 16 ------ ---------- ---------- L1 Accept 106 (In) 122 (In) L2 Decision 107 (In) 123 (In) Comparator Outputs(3:0) 3:0 (Out) 35:32 (Out) Programming Interface --------------------- The L1AL2 FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Enable Timing Signal Reset 3 R/W Force Scaler Reset 8 R/W Comparison Values (1:0) 9 R/W Comparison Values (3:2) 12 R Monitor Readout 24 R HSRO State 25 R/W HSRO Terminal Count 26 R HSRO Current Count 32 R/W Shift Register Latency The bit allocation in each of these registers is: Chip Control Status Register LSW (Register Address 0) Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 3:15 --- not allocated The Chip Status Register MSW is currently unused. Enable Timing Signal Reset Bit Access Contents --- ------ -------- 0 R/W Enable Timing Signal Reset for Outstanding Decision Scaler 1 R/W Enable Timing Signal Reset for Histogram Scalers (not yet implemented) 15:2 R/W not allocated Force Scaler Reset Bit Access Contents --- ------ -------- 0 R/W Force Reset for Outstanding Decision Scaler 1 R/W Force Reset for Histogram Scalers (not yet implemented) 15:2 R/W not allocated Comparison Values(1:0) Bit Access Contents --- ------ -------- 4:0 R/W Comparison Value 0 7:5 R/W not allocated 12:8 R/W Comparison Value 1 15:13 R/W not allocated Comparison Values(3:2) Bit Access Contents --- ------ -------- 4:0 R/W Comparison Value 3 7:5 R/W not allocated 12:8 R/W Comparison Value 4 15:13 R/W not allocated Monitor Readout Bit Access Contents --- ------ -------- 4:0 R Scaler Value 7:5 R '0' 11:8 R Output of Comparators (3:0) 15:12 R '0' HSRO State Bit Access Contents --- ------ -------- 0 R HSRO_DCE_IN* 1 R HSRO_DCE_OUT* 2 R Enable_HSRO_Data 15:3 R not allocated HSRO Terminal Count Bit Access Contents --- ------ -------- 3:0 R/W Number of Words for High-Speed Readout (MUST be greater than 0 if chip HSRO is enabled) 14:4 R/W not allocated 15 R/W Enable HSRO from this Chip (0: DCE_In* passes directly through to DCE_Out* 1: DCE_Out* is generated by the terminal count comparator) Shift Register Latency Bit Access Contents --- ------ -------- 2:0 R/W Select BXHSR Latency (values 0 to 7 are allowed) 15:3 R/W unused