Progamming the Per-Bunch Scalers -------------------------------- Orig: 25-MAY-2000 Rev: 1-JUN-2000 General Background ------------------ First of all, recall how the Per-Bunch Scalers are organized. There are 159 potential bunches in the accelerator, although not every bunch will be populated. We provide hardware for instrumenting all of these bunches. Additionally, each quantity we scale "per-bunch" we also scale integrated over all 159 bunches, resulting in a need for 160 scaler channels for each per-bunch quantity. We divide this across 2 cards (80 channels per card, 80 / 16 = 5 channels in each MSA FPGA). All "per-bunch" quantities to be scaled must enter the PBS card on a Common Control Signal input. The 32 Common Control Signals are actually bussed to each PBS card in a single crate. There are 2 crates of PBS, one servicing "internal" signals (i.e. signals sourced from the L1 Framework), and one servicing "foreign" signals (typically luminosity information from Rich Partridge). For the internal per-bunch quantities, we perform logic on the CCS inputs which mimics the TDM processing of these same inputs (the details are described below). For the foreign per-bunch quantities, we typically simply select a single input to act as the scaler gate. Additionally, each scaler channel must be programmed by TCC to define which bunches it services. Intuitively, it makes sense to define the channels in terms of tick numbers (which do not, and can not, match to the accelerator "Px" bunch numbers, as the accelerator does not populate every bunch). But even this is not entirely simple to implement. Recall that we scale a number of quantities per-bunch. In M122 Middle, we scale quantities generated by the L1 FW. We probably want to define these channels in terms of L1 FW Tick Numbers. In M122 Top, we scale quantites generated by other systems. We probably want to define these channels in terms of Current Tick Numbers. Furthermore, we can't a priori predict the latency of these input signals with respect to the accelerator, nor can we expect the various input signals to have the same latency. Therefore, we really need to allow for the existence of different comparator programming on each channel, to provide uniform mapping of "Tick 1" to "first channel." The design of the Per-Bunch Scaler is such that, if the comparator is programmed to "1" the scaler channel will increment (or not) depending on the state of the input at the BEGINNING of Current Tick #1 as seen at the SCL Input. Tick Clock _ _ _ _ at MSA FPGA _| |___________| |___________| |___________| |___________ BoT _____________ at SCL HE ________________| |__________________________ Current Tick at SCL HE X 159 X 1 X 2 X 3 PBS Gate ____________ at PBS input ________| |___________________________________ PBS Scaler n X n + 1 Programming information Programming the BSF FPGA is already covered in the "BSF Initialization" document. Programming the MSA FPGA's at initialize time is as follows: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 0x0000: Disables all interrupt generation 2 R/W Enable Timing Signal Reset Reset all scaler channels in the usual way: write 0x001f to this register, then assert P1_TS(15), then write 0x0000 to this register. 3 R/W Force Scaler Reset 0x0000: No scaler channels forced into reset 8 R/W CCS Set 0 Control Register 9 R/W CCS Set 1 Control Register 10 R/W CCS Set 2 Control Register 11 R/W CCS Set 3 Control Register 12 R/W Scaler Gate Combination Control Reg Write 0x0000 to all 5 registers. This disables the gate to all scaler channels. At run-time, need to program this register to select the appropriate Common Control Signal as scaler gate. All MSA FPGA's on a pair of PBS cards will have these registers programmed identically. For the PBS cards in M122 Middle (scaling the internally-generated signals), the overall logic is: Selected Lower E.G. Partial And-Or Fired AND Selected Upper E.G. Partial And-Or Fired AND NOT Selected E.G. L1 Busy AND NOT Skip Next Tick (note: Skip Next Tick may evolve into "OR of all Correlated Global Disables, as more Correlated Global Disables are implemented) To implement this logic: Card Reg Addr Addr Value Comment ---- ---- ----- ------- 20/21 8 0x8001 Lower PAOF for Exp Group 0 (output HIGH if EG0 input HIGH) 9 0x8001 Upper PAOF for Exp Group 0 (output HIGH if EG0 input HIGH) 10 0xc001 L1 Busy Disable Exp Grp 0 (output LOW if EG0 input HIGH) 11 0xc080 Global Disable Exp Grp 0 (output LOW if Skip Next input HIGH) 12 0x0002 Scaler Gate HIGH if above 4 signals HIGH) 18/19 8 0x8002 Exposure Group 1 9 0x8002 10 0xc002 11 0xc080 12 0x0002 16/17 8 0x8004 Exposure Group 2 9 0x8004 10 0xc004 11 0xc080 12 0x0002 14/15 8 0x8008 Exposure Group 3 9 0x8008 10 0xc008 11 0xc080 12 0x0002 12/13 8 0x8010 Exposure Group 4 9 0x8010 10 0xc010 11 0xc080 12 0x0002 10/11 8 0x8020 Exposure Group 5 9 0x8020 10 0xc020 11 0xc080 12 0x0002 8/9 8 0x8040 Exposure Group 6 9 0x8040 10 0xc040 11 0xc080 12 0x0002 6/7 8 0x8080 Exposure Group 7 9 0x8080 10 0xc080 11 0xc080 12 0x0002 16 R/W Scaler Channel 0 Tick Sel Control Reg 20 R/W Scaler Channel 1 Tick Sel Control Reg 24 R/W Scaler Channel 2 Tick Sel Control Reg 28 R/W Scaler Channel 3 Tick Sel Control Reg 32 R/W Scaler Channel 4 Tick Sel Control Reg 0x0000: selects tick 0 (non-existent tick). At run-time, need to program these to select which tick each channel services. See discussion above. Each channel on each MSA FPGA on a pair of PBS cards will have a unique value in this register. The mapping of comparator value to PBS channel will likely vary across per-bunch scaled items. For the M122 Middle PBS (i.e. the ones scaling internally-generated information), the mapping is as follows (Exposure Group #0 shown, but all Exposure Groups programmed identically). Recall that the TDM is presenting the L1 Accept Tick #1 data to the PBS while the L1FW is presenting Current Tick #26 (L1 Accept Tick #159) data to the SCL Hub End. Card Chip PBS Addr Addr Channel Value Comment ---- ---- ------- ----- ------- 21 1 0 (RA 16) 26 L1A Tick #1 21 1 1 (RA 20) 27 L1A Tick #2 21 1 2 (RA 24) 28 L1A Tick #3 21 1 3 (RA 28) 29 L1A Tick #4 21 1 4 (RA 32) 30 L1A Tick #5 21 2 0 (RA 16) 31 L1A Tick #6 . . . 21 16 4 (RA 32) 105 L1A Tick #80 20 1 0 (RA 16) 106 L1A Tick #81 . . . 20 16 3 (RA 28) 25 L1A Tick #159 20 16 4 (RA 32) 256 Integrate all Ticks 13 R/W CCS Input Beam Crossing History SR MUX Control 17 R/W Scaler Channel 0 Beam Crossing History SR MUX Control 21 R/W Scaler Channel 1 Beam Crossing History SR MUX Control 25 R/W Scaler Channel 2 Beam Crossing History SR MUX Control 29 R/W Scaler Channel 3 Beam Crossing History SR MUX Control 33 R/W Scaler Channel 4 Beam Crossing History SR MUX Control 0x0001: BXHSR programming appropriate for "2nd stage" of L1 FW pipeline. Note: for the foreign scalers, the programming of the BXHSR is not crucial, except that all channels on all MSA FPGA's on a pair of PBS cards should receive the same programming. The 0x0001 value is no better or worse than any other value so that is what should be used.