***************************** * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * * and * * * * Level 2 Trigger Framework * * * * Per-Bunch Scaler FPGA * * * ***************************** Original: 29-MAY-1997 Latest: 1-JUN-2000 Introduction ------------ The basic concept of Per-Bunch Scaling is described elsewhere and will not be repeated here. This document concentrates only on the architecture and implementation of the Per-Bunch Scaler FPGA. The Per-Bunch Scaler FPGA is used in all MSA FPGA locations on the Per-Bunch Scaler cards (which are instances of the Scaler Module). Per-Bunch Scalers are used for two separate types of scaling: 1. Exposure Group Per-Bunch Scalers 2. Other Per-Bunch Scalers The only difference between these functions are details of gating the Scaler Channels. This FPGA's Scaler Channel gating logic is flexible enough to accomodate both flavors of gating, as described below. Each Per-Bunch Scaler FPGA has the following input and output connections: 1. On-Card Bus (including High-Quality Timing Signals). 2. 32 Common Control Signals (these are Main Signal Array (MSA) Input Signals). The general idea behind this FPGA is to make a single configuration with a reasonable amount of flexibility, to support known and reasonably forseeable Per-Bunch Scaling needs, without adding unnecessary complexity. Recall that special FPGA configurations, while undesirable, can be used to implement Per-Bunch Scaling functions which are not supported by this FPGA configuration. Operation--General Comments --------------------------- The Per-Bunch Scaler FPGA is composed of the following elements: 1. On-Card Bus Interface 2. Tick Counter 3. Scaler Gate Selection and Processing Logic 4. Five Separate Scaler Channels, each consisting of A. Bypassable Tick Selection Comparator B. 32-bit Resettable Scaler C. Monitor Data Capture and Readout Each element is described below. 1. On-Card Bus Interface This is the standard On-Card Bus Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. 2. Tick Counter This is an 8-bit counter, which counts from 1 to 159 and then starts over at 1. It is built around the Xilinx cc8cle library component. Its clock input is the BX Clock for the SM Card, which is a P1 Timing Signal, distributed to this FPGA via HQ Timing Signal #???. Its synchronous load input is the Once-Per-Turn Reset Marker, also a P1 Timing Signal, distributed to this FPGA via HQ Timing Signal #1. Note that this Reset Marker must be active during the rising edge of the BX Clock for tick #1 of the turn. The table below compares the Tick Counter with the (latched) Common Control Signal inputs in order to illustrate proper programming of the Tick Counter comparator: __ __ __ __ __ Tick Clock ____| |____| |____| |____| |____| |_____ ___ Reset Marker __________| |______________________________ __ __ __ ___ ___ ___ ___ ___ ___ ___ ___ Tick Counter 158__X__159__X___1___X___2___X___3___X___4___ _______ SCL Begin Turn _____________________| |______________ __ __ __ __ ___ ___ ___ ___ ___ ___ ___ SCL Curr Tick 157__X__158__X__159__X___1___X___2___X___3___ _______ TC = 1 Comp _______________| |_____________________ _______ Latched Comp _____________________| |_______________ ___ PBS Input _____________////// \\\\\\_________________ _______ Latched Input _____________________| |_______________ __ __________________________ __ __________ P-B Count __n__________________________X__n+1__________ The output of this counter is the Tick Count, which is fed to all 5 Scaler Channels in this FPGA. Note that all Tick Counters in all Per-Bunch FPGA's (on all Per-Bunch Scaler Modules) are running synchronously, as they all are using the same BX Clock and Once-Per-Turn Reset Marker P1 Timing Signals. The clock enable input is wired HIGH, the asynchronous clear input is wired LOW, and the data inputs are wired to a value of 1 (binary 00000001). The clock enable output and terminal count output are not used. 3. Scaler Gate Selection and Processing Logic The Scaler Gate Selection and Processing Logic converts the 32 Common Control Signals to a single Scaler Gate signal for all 5 Scaler Channels. TCC can control, within certain limits, how the Common Control Signals are combined to make the single Scaler Gate signal. The 32 Common Control Signals are divided into 4 separate sets: Common Control Signals 7:0 (CCS Set 0) Common Control Signals 15:8 (CCS Set 1) Common Control Signals 23:16 (CCS Set 2) Common Control Signals 31:24 (CCS Set 3) Any or all of the CCS Set 0 signals can be ANDed or NANDed together. Any or all of the CCS Set 1 signals can be ANDed or NANDed together. Any or all of the CCS Set 2 signals can be ORed or NORed together. Any or all of the CCS Set 3 signals can be ORed or NORed together. The resulting 4 CCS Set outputs can then be ANDed or NANDed together. This flexibility is known to be sufficient to implement the Exposure Per-Bunch Scalers and most if not all of the scaler gating functions found in the Run I Trigger Framework. Special FPGA configurations (as noted above) can be made to support additional scaler gating, should it prove necessary. CCS Set 0 and 1 signals are latched at the input to the PBS. CCS Set 2 signals are NOT latched at the input to the PBS. CCS Set 3 signals are latched at the input to the PBS, but CCS Set 3 signal 7 receives special processing (latched and unlatched versions are ORed together). This mimics the processing in the TDM. Note that for foreign scaler usage, only CCS Set 0 and 1 signals should be used. This is not a significant limitation, as there are only a maximum of 10 foreign scaler items allowed in a single 20-card crate. The delay through the Gate Selection and Processing Logic is on the order of 3 CLB's. The 32 CCS inputs are captured for Monitor Data readout. 4. Five Separate Scaler Channels All five Scaler Channels on this FPGA are identical, and are composed of the following elements: A. Bypassable Tick Selection Comparator B. 32-bit Scaler C. Monitor Data Capture and Readout 4.A Bypassable Tick Selection Comparator Each Scaler Channel on this FPGA is responsible for scaling only a single tick (but see below). The tick selection is performed by comparing the Tick Count output (from the 8-bit Tick Counter) to a value programmed by TCC, using an 8-bit identity comparator (Xilinx comp8 library component). The output of this comparator is HIGH if the Tick Count matches the programmed value. Each Scaler Channel must also have the ability to scale ALL ticks. This is accomplished by allowing TCC to force the output of this comparator HIGH, by programming a control register. This signal is called the Tick Match signal and is fed to this Scaler Channel's 32-bit Scaler. The delay through the Tick Selection Comparator is about 1.5 CLB's. Refer to the Tick Counter timing diagram above, and note that if the Tick Select Comparator is programmed to "1" then the PBS samples its input at the beginning of Current Tick 1 (as seen at the SCL Hub End input). Recall that the L1 FW presents its data for L1 Accept Tick 1 at Current Tick 27. Moreover, the PBS samples the AONM output for L1 Accept Tick 1 at the beginning of Current Tick 26. Therefore, the "lowest" PBS Channel (corresponding to L1 Accept Tick 1) should receive comparator programming of 26. 4.B 32-bit Resettable Scaler The actual scaling function of each Scaler Channel is performed by a 32-bit scaler (a logiblox cc32re with synchronous reset). All 5 Scaler Channels use the same clock, the BX Clock (also used by the Tick Counter, and described there). Each Scaler Channel uses a separate clock enable signal. For each Channel, the clock enable is the AND of the single Scaler Gate Signal (from the Scaler Gate Selection and Processing Logic) with the Tick Match signal for that specific Channel (from that Channel's Tick Comparator). Each Scaler Channel also uses a separate reset signal. The Scaler Reset can come from a High-Quality Timing Signal or from a VME-visible register. The High-Quality Timing Signal reset must be enabled by TCC, but the register reset can be used to force a scaler reset at any time. The Scaler Reset passes through the Beam Crossing History Shift Register with the same latency as the data which is being scaled. The output of each of these 32-bit Scalers is the Scaler Channel Count. 4.C Monitor Data Capture and Readout The 32-bit Count from each Scaler Channel is available for Monitor Data Readout by TCC (via VME). This is done using the standard Monitor Data Capture and Readout techniques, which are described in detail elsewhere. Conceptually, the 32-bit Count is fed to a 32-bit wide Beam Crossing History Shift Register. The clock for this shift register is again the BX Clock (so note that the first stage of this shift register is already running a tick behind the Count (for simplicity below, assume the Count increments on every tick): __ __ __ __ BX Clock ____| |____| |____| |____| |_____ ___ ___ ___ ___ ___ ___ ___ ___ ___ Count 5___X___6___X___7___X___8___X___9___ ___ ___ ___ ___ ___ ___ ___ ___ ___ BXHSR Stage 1 4___X___5___X___6___X___7___X___8___ __ __ __ __ __ __ __ __ __ BXHSR Stage m 5-m__X__6-m__X__7-m__X__8-m__X__9-m__ Upon the assertion of the Capture Monitor Data signal (which arrives on the card as a P1 Timing signal, and has a private connection from the BSF FPGA to all MSA FPGA's), the appropriate stage of the BXHSR is tapped and fed to 32-bit Monitor Data Holding Register. The Capture Monitor Data signal only enables the transfer of this data, it actually occurs with the rising edge of the BX Clock (while Capture Monitor Data is active). Specifically which stage of the BXHSR is tapped remains to be determined. The latency (delay from Triggered tick to the Capture Monitor/HSRO Data signals) is programmable by TCC (within a limited range, currently the FPGA supports latencies between 3 and 7 ticks). Each 32-bit Monitor Data Holding Register appears as a pair of 16-bit registers visible to TCC via VME. TCC reads the values from these registers via normal VME cycles. Note that new Monitor Data should not be captured until TCC has read all of the previous Monitor Data. Note that, in order to reduce the resources required by this FPGA, some simplifications can be made. Specifically, the BXHSR can be put before the 32-bit Scaler described in 4.C. The BXHSR thus records the clock enable signal for each 32-bit scaler rather than the actual output of the scaler. Programming Interface --------------------- The Per-Bunch Scaler FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Enable Timing Signal Reset 3 R/W Force Scaler Reset 8 R/W CCS Set 0 Mux Control Register 9 R/W CCS Set 1 Mux Control Register 10 R/W CCS Set 2 Mux Control Register 11 R/W CCS Set 3 Mux Control Register 12 R/W Scaler Gate Combination Control Reg 13 R/W CCS Input Beam Crossing History SR MUX Control 14 R CCS Input 15:0 Monitor Register 15 R CCS Input 31:16 Monitor Register 16 R/W Scaler Channel 0 Tick Sel Control Reg 17 R/W Scaler Channel 0 Beam Crossing History SR MUX Control 18 R Scaler Channel 0 Monitor Register LSWord 19 R Scaler Channel 0 Monitor Register MSWord 20 R/W Scaler Channel 1 Tick Sel Control Reg 21 R/W Scaler Channel 1 Beam Crossing History SR MUX Control 22 R Scaler Channel 1 Monitor Register LSWord 23 R Scaler Channel 1 Monitor Register MSWord 24 R/W Scaler Channel 2 Tick Sel Control Reg 25 R/W Scaler Channel 2 Beam Crossing History SR MUX Control 26 R Scaler Channel 2 Monitor Register LSWord 27 R Scaler Channel 2 Monitor Register MSWord 28 R/W Scaler Channel 3 Tick Sel Control Reg 29 R/W Scaler Channel 3 Beam Crossing History SR MUX Control 30 R Scaler Channel 3 Monitor Register LSWord 31 R Scaler Channel 3 Monitor Register MSWord 32 R/W Scaler Channel 4 Tick Sel Control Reg 33 R/W Scaler Channel 4 Beam Crossing History SR MUX Control 34 R Scaler Channel 4 Monitor Register LSWord 35 R Scaler Channel 4 Monitor Register MSWord The bit allocation in each of these registers is: Chip Control Status Register LSW (Register Address 0) Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 3:15 --- not allocated The Chip Status Register MSW is currently unused. Enable Timing Signal Reset Bit Access Contents --- ------ -------- 0 R/W Enable Timing Signal Reset for Channel 0 Scaler 1 R/W Enable Timing Signal Reset for Channel 1 Scaler 2 R/W Enable Timing Signal Reset for Channel 2 Scaler 3 R/W Enable Timing Signal Reset for Channel 3 Scaler 4 R/W Enable Timing Signal Reset for Channel 4 Scaler 15:5 R/W not allocated Force Scaler Reset Bit Access Contents --- ------ -------- 0 R/W Force Reset for Channel 0 Scaler 1 R/W Force Reset for Channel 1 Scaler 2 R/W Force Reset for Channel 2 Scaler 3 R/W Force Reset for Channel 3 Scaler 4 R/W Force Reset for Channel 4 Scaler 15:5 R/W not allocated Common Control Signal Set Mux Control Registers Bit Access Contents --- ------ -------- 7:0 R/W Input Enable 7:0 (For CCS 0/1: CCS Output is AND of all Enabled inputs (or NAND of all Enabled inputs, see Mode below). If no inputs are Enabled for CCS 0/1, then CCS output is HIGH (in AND mode) or LOW (in NAND mode) -- NOTE: CCS Enable has precedence, see below) (For CCS 2/3: CCS Output is OR of all Enabled inputs (or NOR of all Enabled inputs, see Mode below). If no inputs are Enabled for CCS 2/3, then CCS output is LOW (in OR mode) or HIGH (in NOR mode) -- NOTE: CCS Enable has precedence, see below) 13:8 R/W unallocated 14 R/W Mode Select (For CCS 0/1: '0': AND Mode '1': NAND Mode) (For CCS 2/3: '0': OR Mode '1': NOR Mode) 15 R/W CCS Enable ('0': this CCS Set is ignored in the CCS processing regardless of the programming selected above) Scaler Gate Combination Control Register Bit Access Contents --- ------ -------- 0 R/W Output Invert ('0': Output = AND of all selected inputs '1': Output = NAND of all selected inputs) 1 R/W Global Enable ('0': Scaler Gate forced LOW) 15:2 R/W not allocated Notes: To disable all Scaler Channels, set Global Enable LOW To force Scaler Gate HIGH always, disable all 4 CCS Sets and set Global Enable HIGH. Scaler Channel Tick Select Control Registers Bit Access Contents --- ------ -------- 7:0 R/W Tick Select (: Select tick (subordinate to Select All Ticks)) 8 R/W Select All Ticks ('0': select tick specified via Tick Select '1': select all ticks) 15:9 R/W not allocated Scaler Channel Beam Crossing History SR MUX Control CCS Input Beam Crossing History SR MUX Control Bit Access Contents --- ------ -------- 2:0 R/W Depth in stage 1 of BXHSR 15:3 R/W unallocated