***************************** * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * * and * * * * Level 2 Trigger Framework * * * * Scaler Module * * * ***************************** Original: 22-MAY-1997 Latest: 14-AUG-1997 Introduction ------------ The Scaler Module (SM) is the only dedicated scaler card used in the Level 1 and Level 2 Trigger Frameworks. This single species of PCB performs (at least) two separate types of scaler function, depending on which FPGA configuration is loaded: 1. Per-bunch scalers 2. General purpose gated scalers The details of this card's operation in each scaler configuration are provided below in this document. Each Scaler Module has the following input and output connections (in addition to the VME, P1 Timing, and High-Speed Readout interfaces described in THE_CARD.TXT): 1. 32 Common Control Signals, entering on P2/P3 and bussed to all 16 MSA FPGA's. These are differential ECL inputs. 2. 6 Per-FPGA Control Signals for each of the 16 MSA FPGA's, also entering on P2/P3 (6 * 16 = 96 signals of this class). These are differential ECL inputs. 3. 32-bit wide Output Bus from each of 2 pre-selected MSA FPGA's, emerging on P4 (2 * 32 = 64 signals of this class). These are differential ECL outputs. Questions to be resolved ------------------------ 1. What about P5 Global I/O? 2. What about resetting scalers (system-wide concern) Operation: General Comments --------------------------- The Scaler Module PCB is designed to support at least two very different types of scaling functions, depending on which FPGA configuration is loaded into the MSA FPGA's. The features built into this PCB must therefore be a superset of the features required to implement either type of scaler, as well as provide sufficient flexibility to implement as-yet unknown scaling or other triggering functions. Some basic "ground rules" for scalers have been laid down. The fundamental scaler size is 32 bits, which provides unique counts for at least 566 seconds (about 9.5 minutes) at a 132 ns clock rate. If necessary, wider scalers can be built by concatenating two 32-bit scalers within a single FPGA. Our estimate of scaler CLB usage indicates that 5-6 32-bit Scaler Channels, with their associated Monitor and/or High-Speed Readout Buffers, OCB and HSRO Interfaces, control logic, etc. will fit into our standard Xilinx XC4013L FPGA. This translates into 80 or 96 32-bit scalers per SM. Our estimate of High-Speed Readout timing indicates that only 16 of these 32 bit scalers (plus necessary BSF FPGA "headers") could easily be read out to the VRB, assuming the standard one 16-bit word per 132 ns rate of supplying data to the Finisar module from THE Card and 8 us deadtime per L1 Accept. Note that, due to technical details regarding the HSRO Daisy Chain Enable passing, is it fastest to allocate one "HSRO Scaler Channel" to each of the 16 MSA FPGA's, but other arrangements are possible. Operation: Per-Bunch Scaler --------------------------- There are 159 132-ns ticks in one accelerator turn. Therefore there are a maximum of 159 bunches in the accelerator. Even though not every tick will be populated, a Per-bunch Scaler Channel is allocated for every tick. Every quantity to be scaled per-bunch requires 2 SM cards, each with 80 scalers. One SM will scale ticks 1:80, and the other will scale ticks 81:159. Note that there is one "extra" Scaler Channel on this second SM card, it will be used to integrate all ticks. Each MSA FPGA is thus responsible for 80 / 16 = 5 ticks. Per-bunch Scalers are NOT read out via High-Speed Readout, but rather are only available for Monitor Readout via the VME bus. The primary use of Per-bunch Scalers is to scale Exposure. There are 8 Exposure Groups (thus 16 SM cards are required to scale Exposure for all 8 Exposure Groups and all 159 ticks). Within an Exposure Group, the coincidence of 3 signals is required to register Exposure. These signals are: And-Or Input Terms 127:0, Exposure Group And-Or Input Terms 255:128, Exposure Group Geographic Section Front-End (not) Busy, Exposure Group Note that the Geographics Section Front-End Busy for Exposure Group signals must be inverted to produce a signal which is HIGH when Exposure should be counted. This can be done in the Per-Bunch Scaler FPGA. Note that this is a total of 8 * 3 = 24 signals. To simplify cabling, all of these signals will be provided to all 16 Exposure Group Per-bunch Scalers in parallel. Multiplexers within each MSA FPGA, programmable by TCC, are used to select the appropriate set of signals. For testing, the multiplexers can also be programmed by TCC to ignore these input signals, and force the scaler gate either high or low. These signals will be brought on to the card as a subset of the 32 Common Control Signals described above, and thus routed to all MSA FPGA's on the SM. The other 8 Common Control Signals are not used, (but see below). Each MSA FPGA will have, in addition to the 5, 32-bit Scaler Channels, a 8-bit Tick Counter which receives an Tick Increment Clock (with a 132 ns period) and a Beginning-of-Turn Reset Marker (with a 159 * 132 ns period) via HQ Timing Signals. These signals originate as P1 Timing Signals, and pass through the BSF FPGA. The Tick Counters must count from 1 to 159, and reset back to 1 at Beginning-of-Turn Reset Marker, to maintain agreement with the D0 standard for numbering ticks. This is different from most the numbering scheme used in much of the rest of the Framework, which starts with 0. The Tick Counter keeps track of the current tick. Each MSA FPGA has 5, 8-bit comparators, one for each Scaler Channel. These are programmable via TCC to indicate which tick corresponds to each Scaler Channel. During the tick that a Scaler Channel is responsible for, if the 3 selected Exposure Group signals listed above are all active, the Scaler Channel increments at the rising edge of a Scaler Increment Clock (which may be the same signal as the Tick Increment Clock). The Scaler Increment Clock also originates as a P1 Timing Signal, is passed through the BSF FPGA, and delivered as a HQ Timing Signal to the MSA FPGA's. The Tick Comparator can, under TCC control, be bypassed, allowing the Scaler Channel to increment on every tick (if the Exposure Group signals are all active). This is done to allow one Scaler Channel to integrate Exposure across all ticks. In principle, the Tick Counter need not be implemented in every SM MSA FPGA. It would be possible to have either a master Tick Counter for the entire Framework, or a master Tick Counter for each SM card (in the BSF FPGA). We choose to duplicate the Tick Counter in each BSF FPGA primarily to simplify the cabling of the Per-Bunch Scaler crates. Note that, if one Tick Counter gets out of sync with the other Tick Counters, the anomaly will only last for a single turn (as each Tick Counter is reset once per turn). Further, if one Tick Counter misses its Beginning-of-Turn Reset Marker, the anomaly will again only last for a single turn (until the next Beginning-of-Turn Reset Marker). There is no High-Speed Readout of the Per-bunch Scalers, but simply Monitor Readout. A P1 Timing signal carries the Load Monitor Readout Data signal, which is then distributed to the 16 MSA FPGA's via a High-Quality Timing Signal. On the rising edge of this signal, the appropriate information is captured in Monitor Data Readout Buffers for readout via VME Bus. The details of Monitor Data Capture and Readout are recorded elsewhere and not duplicated here. There is no plan to use the 96 Per-FPGA Control Signals in Per-bunch Scaler operation, but this may be another way to have the Tick Counter/Decoder implemented externally. There is also no plan to use the two, 32-bit Output Bus Signals in Per-bunch Scaler operation. Finally, note that the Per-Bunch Scalers are also used to scale quantities other than Exposure Per-Bunch. In this case, the 32 Common Control Signals are used as up to 32 gates which may be ANDed together (in each MSA FPGA) to provide the overall gate signal to all Scaler Channels on an SM. The assignment of Common Control Signals is as follows: Common Usage in Usage in Control Exposure Other Signal Per-Bunch Scalers Per-Bunch Scalers ------- ----------------- ----------------- 0 AOIT 127:0, EG 0 Gate 0 1 AOIT 127:0, EG 1 Gate 1 2 AOIT 127:0, EG 2 Gate 2 3 AOIT 127:0, EG 3 Gate 3 4 AOIT 127:0, EG 4 Gate 4 5 AOIT 127:0, EG 5 Gate 5 6 AOIT 127:0, EG 6 Gate 6 7 AOIT 127:0, EG 7 Gate 7 8 AOIT 255:128, EG 0 Gate 8 9 AOIT 255:128, EG 1 Gate 9 10 AOIT 255:128, EG 2 Gate 10 11 AOIT 255:128, EG 3 Gate 11 12 AOIT 255:128, EG 4 Gate 12 13 AOIT 255:128, EG 5 Gate 13 14 AOIT 255:128, EG 6 Gate 14 15 AOIT 255:128, EG 7 Gate 15 16 FE Bz, EG 0 Gate 16 17 FE Bz, EG 1 Gate 17 18 FE Bz, EG 2 Gate 18 19 FE Bz, EG 3 Gate 19 20 FE Bz, EG 4 Gate 20 21 FE Bz, EG 5 Gate 21 22 FE Bz, EG 6 Gate 22 23 FE Bz, EG 7 Gate 23 24 Spare, EG 0 Gate 24 25 Spare, EG 1 Gate 25 26 Spare, EG 2 Gate 26 27 Spare, EG 3 Gate 27 28 Spare, EG 4 Gate 28 29 Spare, EG 5 Gate 29 30 Spare, EG 6 Gate 30 31 Spare, EG 7 Gate 31 Note that, for simplicity, we will use the same FPGA configuration for both types of Per-Bunch Scalers. See the description of the Per-Bunch Scaler FPGA for more details on this FPGA. Operation: Gated Scaler ----------------------- General purpose Gates Scalers do not perform scaling per-bunch, but instead scale up to 96 separate quantities (up to 6 per MSA FPGA) on a single card. The 32 Common Control Signals are routed to each MSA FPGA, and could be used as up to 32 "gate" inputs common across all Scaler Channels on a given card. Note that these signals are NOT expected to be of sufficient fidelity to be used as clocks. The 6 Per-FPGA Control Signals to each MSA FPGA are expected to be used as individual Scaler Channel "gate" signals, allowing up to 6 separate 32-bit Scaler Channels to be implemented in each MSA FPGA (giving the total of up to 96 Scaler Channels for the entire card). There are two possibilities for allowing multiple gates on each Scaler Channel. If gate signals are to be common across Scaler Channels, any subset of the 32 Common Control signals can be used in conjunction with a single Per-FPGA Control Signal to provide the multiple gates for a single Scaler Channel. If the gate signals are not common across Scaler Channels, any subset of the 6 Per-FPGA Control Signals may be used to provide multiple (up to 6) gates for a single Scaler Channel, at the expense of reducing the total number of Scaler Channels on a card. For example, we could implement three, 2-gate Scaler Channels per MSA FPGA, for a total of 3 * 16 = 48 Scaler Channels per SM card. The clock signal for all Scaler Channels is expected to come from a common Scaler Increment Clock, which originates as a P1 Timing Signal and is delivered to the MSA FPGA's over the HQ Timing Signal lines. However, other clocking techniques may be used. For example, the flexibility of the BSF FPGA may be used to provide different Scaler Increment Clocks to different MSA FPGA's. Or, the Per-FPGA Control Signals are expected to be of sufficient fidelity to be used as clocks. All Scaler Channels are available for Monitor Readout, which operates as described above. Additionally, again as described above, 16 Scaler Channels are available for High-Speed Readout. We know that real-time "electrical format" outputs from some Scaler Channels are required, for example Beam Crossing and L1 Trigger Numbers are given to the SLIM to be sent over the SCL to the Front-Ends. Two different MSA FPGA's are each able to drive a 32-bit scaler value off-card via the P4 front-panel connector. Which particular FPGA's have this ability is as-yet undetermined, but it will be based on routing considerations. It is very likely that MSA FPGA's 13 and 16 will be chosen. Implementation Summary ---------------------- Table of specifics for the species of THE Card Board Species ID MSB: 2 MSA FPGA Signal Mapping The following MSA Inputs go to all MSA FPGA's: 3:0 19:16 35:32 51:48 67:64 83:80 99:96 115:112 Chip Addr MSA Inputs MSA Outputs BG-I/O --------- ---------- ----------- ------ 1 9:4 2 25:20 3 73:68 4 87:84 5 15:10 6 31:26 7 79:74 8 95:90 9 41:36 10 57:52 11 105:100 12 121:116 13 47:42 14 63:58 15 111:106 31:0 16 127:122 63:32 There are NO inter-MSA FPGA connections. ------------------------- CONNECTOR PIN ASSIGNMENTS ------------------------- ---------------------------------------------------------------------- P1: 160-pin E-style DIN connector for P1 VME and Timing ---------------------------------------------------------------------- See THE_CARD.TXT for a description of this connector, which is common to all species of THE Card. ---------------------------------------------------------------------- P2: 160-pin E-style DIN connector for Trigger Framework P2 input bus ---------------------------------------------------------------------- Pin # Signal Description Dir Identifier ----- ------------------ --- ---------- A1 Common Control Signal 0 COM INPUT MSA_In_000 B1 Common Control Signal 0 DIR INPUT MSA_In_000 A2 Common Control Signal 1 COM INPUT MSA_In_001 B2 Common Control Signal 1 DIR INPUT MSA_In_001 A3 Common Control Signal 2 COM INPUT MSA_In_002 B3 Common Control Signal 2 DIR INPUT MSA_In_002 A4 Common Control Signal 3 COM INPUT MSA_In_003 B4 Common Control Signal 3 DIR INPUT MSA_In_003 A5 MSA FPGA 1 Per-FPGA Control Signal 0 COM INPUT MSA_In_004 B5 MSA FPGA 1 Per-FPGA Control Signal 0 DIR INPUT MSA_In_004 A6 MSA FPGA 1 Per-FPGA Control Signal 1 COM INPUT MSA_In_005 B6 MSA FPGA 1 Per-FPGA Control Signal 1 DIR INPUT MSA_In_005 A7 MSA FPGA 1 Per-FPGA Control Signal 2 COM INPUT MSA_In_006 B7 MSA FPGA 1 Per-FPGA Control Signal 2 DIR INPUT MSA_In_006 A8 MSA FPGA 1 Per-FPGA Control Signal 3 COM INPUT MSA_In_007 B8 MSA FPGA 1 Per-FPGA Control Signal 3 DIR INPUT MSA_In_007 A9 MSA FPGA 1 Per-FPGA Control Signal 4 COM INPUT MSA_In_008 B9 MSA FPGA 1 Per-FPGA Control Signal 4 DIR INPUT MSA_In_008 A10 MSA FPGA 1 Per-FPGA Control Signal 5 COM INPUT MSA_In_009 B10 MSA FPGA 1 Per-FPGA Control Signal 5 DIR INPUT MSA_In_009 A11 MSA FPGA 5 Per-FPGA Control Signal 0 COM INPUT MSA_In_010 B11 MSA FPGA 5 Per-FPGA Control Signal 0 DIR INPUT MSA_In_010 A12 MSA FPGA 5 Per-FPGA Control Signal 1 COM INPUT MSA_In_011 B12 MSA FPGA 5 Per-FPGA Control Signal 1 DIR INPUT MSA_In_011 A13 MSA FPGA 5 Per-FPGA Control Signal 2 COM INPUT MSA_In_012 B13 MSA FPGA 5 Per-FPGA Control Signal 2 DIR INPUT MSA_In_012 A14 MSA FPGA 5 Per-FPGA Control Signal 3 COM INPUT MSA_In_013 B14 MSA FPGA 5 Per-FPGA Control Signal 3 DIR INPUT MSA_In_013 A15 MSA FPGA 5 Per-FPGA Control Signal 4 COM INPUT MSA_In_014 B15 MSA FPGA 5 Per-FPGA Control Signal 4 DIR INPUT MSA_In_014 A16 MSA FPGA 5 Per-FPGA Control Signal 5 COM INPUT MSA_In_015 B16 MSA FPGA 5 Per-FPGA Control Signal 5 DIR INPUT MSA_In_015 A17 Common Control Signal 8 COM INPUT MSA_In_016 B17 Common Control Signal 8 DIR INPUT MSA_In_016 A18 Common Control Signal 9 COM INPUT MSA_In_017 B18 Common Control Signal 9 DIR INPUT MSA_In_017 A19 Common Control Signal 10 COM INPUT MSA_In_018 B19 Common Control Signal 10 DIR INPUT MSA_In_018 A20 Common Control Signal 11 COM INPUT MSA_In_019 B20 Common Control Signal 11 DIR INPUT MSA_In_019 A21 MSA FPGA 2 Per-FPGA Control Signal 0 COM INPUT MSA_In_020 B21 MSA FPGA 2 Per-FPGA Control Signal 0 DIR INPUT MSA_In_020 A22 MSA FPGA 2 Per-FPGA Control Signal 1 COM INPUT MSA_In_021 B22 MSA FPGA 2 Per-FPGA Control Signal 1 DIR INPUT MSA_In_021 A23 MSA FPGA 2 Per-FPGA Control Signal 2 COM INPUT MSA_In_022 B23 MSA FPGA 2 Per-FPGA Control Signal 2 DIR INPUT MSA_In_022 A24 MSA FPGA 2 Per-FPGA Control Signal 3 COM INPUT MSA_In_023 B24 MSA FPGA 2 Per-FPGA Control Signal 3 DIR INPUT MSA_In_023 A25 MSA FPGA 2 Per-FPGA Control Signal 4 COM INPUT MSA_In_024 B25 MSA FPGA 2 Per-FPGA Control Signal 4 DIR INPUT MSA_In_024 A26 MSA FPGA 2 Per-FPGA Control Signal 5 COM INPUT MSA_In_025 B26 MSA FPGA 2 Per-FPGA Control Signal 5 DIR INPUT MSA_In_025 A27 MSA FPGA 6 Per-FPGA Control Signal 0 COM INPUT MSA_In_026 B27 MSA FPGA 6 Per-FPGA Control Signal 0 DIR INPUT MSA_In_026 A28 MSA FPGA 6 Per-FPGA Control Signal 1 COM INPUT MSA_In_027 B28 MSA FPGA 6 Per-FPGA Control Signal 1 DIR INPUT MSA_In_027 A29 MSA FPGA 6 Per-FPGA Control Signal 2 COM INPUT MSA_In_028 B29 MSA FPGA 6 Per-FPGA Control Signal 2 DIR INPUT MSA_In_028 A30 MSA FPGA 6 Per-FPGA Control Signal 3 COM INPUT MSA_In_029 B30 MSA FPGA 6 Per-FPGA Control Signal 3 DIR INPUT MSA_In_029 A31 MSA FPGA 6 Per-FPGA Control Signal 4 COM INPUT MSA_In_030 B31 MSA FPGA 6 Per-FPGA Control Signal 4 DIR INPUT MSA_In_030 A32 MSA FPGA 6 Per-FPGA Control Signal 5 COM INPUT MSA_In_031 B32 MSA FPGA 6 Per-FPGA Control Signal 5 DIR INPUT MSA_In_031 C1 GROUND C2 +3.3V UPPER C3 GROUND C4 +3.3V UPPER C5 -2.0V UPPER C6 GROUND C7 +3.3V UPPER C8 GROUND C9 +5.0V UPPER C10 GROUND C11 +3.3V UPPER C12 GROUND C13 +3.3V UPPER C14 GROUND C15 -2.0V UPPER C16 GROUND C17 +3.3V UPPER C18 GROUND C19 +5.0V UPPER C20 +3.3V UPPER C21 GROUND C22 +3.3V UPPER C23 GROUND C24 -2.0V UPPER C25 GROUND C26 +3.3V UPPER C27 GROUND C28 +5.0V UPPER C29 +3.3V UPPER C30 GROUND C31 +3.3V UPPER C32 GROUND D1 Common Control Signal 4 COM INPUT MSA_In_032 E1 Common Control Signal 4 DIR INPUT MSA_In_032 D2 Common Control Signal 5 COM INPUT MSA_In_033 E2 Common Control Signal 5 DIR INPUT MSA_In_033 D3 Common Control Signal 6 COM INPUT MSA_In_034 E3 Common Control Signal 6 DIR INPUT MSA_In_034 D4 Common Control Signal 7 COM INPUT MSA_In_035 E4 Common Control Signal 7 DIR INPUT MSA_In_035 D5 MSA FPGA 9 Per-FPGA Control Signal 0 COM INPUT MSA_In_036 E5 MSA FPGA 9 Per-FPGA Control Signal 0 DIR INPUT MSA_In_036 D6 MSA FPGA 9 Per-FPGA Control Signal 1 COM INPUT MSA_In_037 E6 MSA FPGA 9 Per-FPGA Control Signal 1 DIR INPUT MSA_In_037 D7 MSA FPGA 9 Per-FPGA Control Signal 2 COM INPUT MSA_In_038 E7 MSA FPGA 9 Per-FPGA Control Signal 2 DIR INPUT MSA_In_038 D8 MSA FPGA 9 Per-FPGA Control Signal 3 COM INPUT MSA_In_039 E8 MSA FPGA 9 Per-FPGA Control Signal 3 DIR INPUT MSA_In_039 D9 MSA FPGA 9 Per-FPGA Control Signal 4 COM INPUT MSA_In_040 E9 MSA FPGA 9 Per-FPGA Control Signal 4 DIR INPUT MSA_In_040 D10 MSA FPGA 9 Per-FPGA Control Signal 5 COM INPUT MSA_In_041 E10 MSA FPGA 9 Per-FPGA Control Signal 5 DIR INPUT MSA_In_041 D11 MSA FPGA 13 Per-FPGA Control Signal 0 COM INPUT MSA_In_042 E11 MSA FPGA 13 Per-FPGA Control Signal 0 DIR INPUT MSA_In_042 D12 MSA FPGA 13 Per-FPGA Control Signal 1 COM INPUT MSA_In_043 E12 MSA FPGA 13 Per-FPGA Control Signal 1 DIR INPUT MSA_In_043 D13 MSA FPGA 13 Per-FPGA Control Signal 2 COM INPUT MSA_In_044 E13 MSA FPGA 13 Per-FPGA Control Signal 2 DIR INPUT MSA_In_044 D14 MSA FPGA 13 Per-FPGA Control Signal 3 COM INPUT MSA_In_045 E14 MSA FPGA 13 Per-FPGA Control Signal 3 DIR INPUT MSA_In_045 D15 MSA FPGA 13 Per-FPGA Control Signal 4 COM INPUT MSA_In_046 E15 MSA FPGA 13 Per-FPGA Control Signal 4 DIR INPUT MSA_In_046 D16 MSA FPGA 13 Per-FPGA Control Signal 5 COM INPUT MSA_In_047 E16 MSA FPGA 13 Per-FPGA Control Signal 5 DIR INPUT MSA_In_047 D17 Common Control Signal 12 COM INPUT MSA_In_048 E17 Common Control Signal 12 DIR INPUT MSA_In_048 D18 Common Control Signal 13 COM INPUT MSA_In_049 E18 Common Control Signal 13 DIR INPUT MSA_In_049 D19 Common Control Signal 14 COM INPUT MSA_In_050 E19 Common Control Signal 14 DIR INPUT MSA_In_050 D20 Common Control Signal 15 COM INPUT MSA_In_051 E20 Common Control Signal 15 DIR INPUT MSA_In_051 D21 MSA FPGA 10 Per-FPGA Control Signal 0 COM INPUT MSA_In_052 E21 MSA FPGA 10 Per-FPGA Control Signal 0 DIR INPUT MSA_In_052 D22 MSA FPGA 10 Per-FPGA Control Signal 1 COM INPUT MSA_In_053 E22 MSA FPGA 10 Per-FPGA Control Signal 1 DIR INPUT MSA_In_053 D23 MSA FPGA 10 Per-FPGA Control Signal 2 COM INPUT MSA_In_054 E23 MSA FPGA 10 Per-FPGA Control Signal 2 DIR INPUT MSA_In_054 D24 MSA FPGA 10 Per-FPGA Control Signal 3 COM INPUT MSA_In_055 E24 MSA FPGA 10 Per-FPGA Control Signal 3 DIR INPUT MSA_In_055 D25 MSA FPGA 10 Per-FPGA Control Signal 4 COM INPUT MSA_In_056 E25 MSA FPGA 10 Per-FPGA Control Signal 4 DIR INPUT MSA_In_056 D26 MSA FPGA 10 Per-FPGA Control Signal 5 COM INPUT MSA_In_057 E26 MSA FPGA 10 Per-FPGA Control Signal 5 DIR INPUT MSA_In_057 D27 MSA FPGA 14 Per-FPGA Control Signal 0 COM INPUT MSA_In_058 E27 MSA FPGA 14 Per-FPGA Control Signal 0 DIR INPUT MSA_In_058 D28 MSA FPGA 14 Per-FPGA Control Signal 1 COM INPUT MSA_In_059 E28 MSA FPGA 14 Per-FPGA Control Signal 1 DIR INPUT MSA_In_059 D29 MSA FPGA 14 Per-FPGA Control Signal 2 COM INPUT MSA_In_060 E29 MSA FPGA 14 Per-FPGA Control Signal 2 DIR INPUT MSA_In_060 D30 MSA FPGA 14 Per-FPGA Control Signal 3 COM INPUT MSA_In_061 E30 MSA FPGA 14 Per-FPGA Control Signal 3 DIR INPUT MSA_In_061 D31 MSA FPGA 14 Per-FPGA Control Signal 4 COM INPUT MSA_In_062 E31 MSA FPGA 14 Per-FPGA Control Signal 4 DIR INPUT MSA_In_062 D32 MSA FPGA 14 Per-FPGA Control Signal 5 COM INPUT MSA_In_063 E32 MSA FPGA 14 Per-FPGA Control Signal 5 DIR INPUT MSA_In_063 ---------------------------------------------------------------------- P3: 160-pin E-style DIN connector for Trigger Framework P3 input bus ---------------------------------------------------------------------- Pin # Signal Description Dir Identifier ----- ------------------ --- ---------- A1 Common Control Signal 16 COM INPUT MSA_In_064 B1 Common Control Signal 16 DIR INPUT MSA_In_064 A2 Common Control Signal 17 COM INPUT MSA_In_065 B2 Common Control Signal 17 DIR INPUT MSA_In_065 A3 Common Control Signal 18 COM INPUT MSA_In_066 B3 Common Control Signal 18 DIR INPUT MSA_In_066 A4 Common Control Signal 19 COM INPUT MSA_In_067 B4 Common Control Signal 19 DIR INPUT MSA_In_067 A5 MSA FPGA 3 Per-FPGA Control Signal 0 COM INPUT MSA_In_068 B5 MSA FPGA 3 Per-FPGA Control Signal 0 DIR INPUT MSA_In_068 A6 MSA FPGA 3 Per-FPGA Control Signal 1 COM INPUT MSA_In_069 B6 MSA FPGA 3 Per-FPGA Control Signal 1 DIR INPUT MSA_In_069 A7 MSA FPGA 3 Per-FPGA Control Signal 2 COM INPUT MSA_In_070 B7 MSA FPGA 3 Per-FPGA Control Signal 2 DIR INPUT MSA_In_070 A8 MSA FPGA 3 Per-FPGA Control Signal 3 COM INPUT MSA_In_071 B8 MSA FPGA 3 Per-FPGA Control Signal 3 DIR INPUT MSA_In_071 A9 MSA FPGA 3 Per-FPGA Control Signal 4 COM INPUT MSA_In_072 B9 MSA FPGA 3 Per-FPGA Control Signal 4 DIR INPUT MSA_In_072 A10 MSA FPGA 3 Per-FPGA Control Signal 5 COM INPUT MSA_In_073 B10 MSA FPGA 3 Per-FPGA Control Signal 5 DIR INPUT MSA_In_073 A11 MSA FPGA 7 Per-FPGA Control Signal 0 COM INPUT MSA_In_074 B11 MSA FPGA 7 Per-FPGA Control Signal 0 DIR INPUT MSA_In_074 A12 MSA FPGA 7 Per-FPGA Control Signal 1 COM INPUT MSA_In_075 B12 MSA FPGA 7 Per-FPGA Control Signal 1 DIR INPUT MSA_In_075 A13 MSA FPGA 7 Per-FPGA Control Signal 2 COM INPUT MSA_In_076 B13 MSA FPGA 7 Per-FPGA Control Signal 2 DIR INPUT MSA_In_076 A14 MSA FPGA 7 Per-FPGA Control Signal 3 COM INPUT MSA_In_077 B14 MSA FPGA 7 Per-FPGA Control Signal 3 DIR INPUT MSA_In_077 A15 MSA FPGA 7 Per-FPGA Control Signal 4 COM INPUT MSA_In_078 B15 MSA FPGA 7 Per-FPGA Control Signal 4 DIR INPUT MSA_In_078 A16 MSA FPGA 7 Per-FPGA Control Signal 5 COM INPUT MSA_In_079 B16 MSA FPGA 7 Per-FPGA Control Signal 5 DIR INPUT MSA_In_079 A17 Common Control Signal 24 COM INPUT MSA_In_080 B17 Common Control Signal 24 DIR INPUT MSA_In_080 A18 Common Control Signal 25 COM INPUT MSA_In_081 B18 Common Control Signal 25 DIR INPUT MSA_In_081 A19 Common Control Signal 26 COM INPUT MSA_In_082 B19 Common Control Signal 26 DIR INPUT MSA_In_082 A20 Common Control Signal 27 COM INPUT MSA_In_083 B20 Common Control Signal 27 DIR INPUT MSA_In_083 A21 MSA FPGA 4 Per-FPGA Control Signal 0 COM INPUT MSA_In_084 B21 MSA FPGA 4 Per-FPGA Control Signal 0 DIR INPUT MSA_In_084 A22 MSA FPGA 4 Per-FPGA Control Signal 1 COM INPUT MSA_In_085 B22 MSA FPGA 4 Per-FPGA Control Signal 1 DIR INPUT MSA_In_085 A23 MSA FPGA 4 Per-FPGA Control Signal 2 COM INPUT MSA_In_086 B23 MSA FPGA 4 Per-FPGA Control Signal 2 DIR INPUT MSA_In_086 A24 MSA FPGA 4 Per-FPGA Control Signal 3 COM INPUT MSA_In_087 B24 MSA FPGA 4 Per-FPGA Control Signal 3 DIR INPUT MSA_In_087 A25 MSA FPGA 4 Per-FPGA Control Signal 4 COM INPUT MSA_In_088 B25 MSA FPGA 4 Per-FPGA Control Signal 4 DIR INPUT MSA_In_088 A26 MSA FPGA 4 Per-FPGA Control Signal 5 COM INPUT MSA_In_089 B26 MSA FPGA 4 Per-FPGA Control Signal 5 DIR INPUT MSA_In_089 A27 MSA FPGA 8 Per-FPGA Control Signal 0 COM INPUT MSA_In_090 B27 MSA FPGA 8 Per-FPGA Control Signal 0 DIR INPUT MSA_In_090 A28 MSA FPGA 8 Per-FPGA Control Signal 1 COM INPUT MSA_In_091 B28 MSA FPGA 8 Per-FPGA Control Signal 1 DIR INPUT MSA_In_091 A29 MSA FPGA 8 Per-FPGA Control Signal 2 COM INPUT MSA_In_092 B29 MSA FPGA 8 Per-FPGA Control Signal 2 DIR INPUT MSA_In_092 A30 MSA FPGA 8 Per-FPGA Control Signal 3 COM INPUT MSA_In_093 B30 MSA FPGA 8 Per-FPGA Control Signal 3 DIR INPUT MSA_In_093 A31 MSA FPGA 8 Per-FPGA Control Signal 4 COM INPUT MSA_In_094 B31 MSA FPGA 8 Per-FPGA Control Signal 4 DIR INPUT MSA_In_094 A32 MSA FPGA 8 Per-FPGA Control Signal 5 COM INPUT MSA_In_095 B32 MSA FPGA 8 Per-FPGA Control Signal 5 DIR INPUT MSA_In_095 C1 GROUND C2 +3.3V LOWER C3 GROUND C4 +3.3V LOWER C5 -4.5V LOWER C6 GROUND C7 +3.3V LOWER C8 GROUND C9 +5.0V LOWER C10 GROUND C11 +3.3V LOWER C12 GROUND C13 +3.3V LOWER C14 GROUND C15 -4.5V LOWER C16 GROUND C17 +3.3V LOWER C18 GROUND C19 +5.0V LOWER C20 +3.3V LOWER C21 GROUND C22 +3.3V LOWER C23 GROUND C24 -4.5V LOWER C25 GROUND C26 +3.3V LOWER C27 GROUND C28 +5.0V LOWER C29 +3.3V LOWER C30 GROUND C31 +3.3V LOWER C32 GROUND D1 Common Control Signal 20 COM INPUT MSA_In_096 E1 Common Control Signal 20 DIR INPUT MSA_In_096 D2 Common Control Signal 21 COM INPUT MSA_In_097 E2 Common Control Signal 21 DIR INPUT MSA_In_097 D3 Common Control Signal 22 COM INPUT MSA_In_098 E3 Common Control Signal 22 DIR INPUT MSA_In_098 D4 Common Control Signal 23 COM INPUT MSA_In_099 E4 Common Control Signal 23 DIR INPUT MSA_In_099 D5 MSA FPGA 11 Per-FPGA Control Signal 0 COM INPUT MSA_In_100 E5 MSA FPGA 11 Per-FPGA Control Signal 0 DIR INPUT MSA_In_100 D6 MSA FPGA 11 Per-FPGA Control Signal 1 COM INPUT MSA_In_101 E6 MSA FPGA 11 Per-FPGA Control Signal 1 DIR INPUT MSA_In_101 D7 MSA FPGA 11 Per-FPGA Control Signal 2 COM INPUT MSA_In_102 E7 MSA FPGA 11 Per-FPGA Control Signal 2 DIR INPUT MSA_In_102 D8 MSA FPGA 11 Per-FPGA Control Signal 3 COM INPUT MSA_In_103 E8 MSA FPGA 11 Per-FPGA Control Signal 3 DIR INPUT MSA_In_103 D9 MSA FPGA 11 Per-FPGA Control Signal 4 COM INPUT MSA_In_104 E9 MSA FPGA 11 Per-FPGA Control Signal 4 DIR INPUT MSA_In_104 D10 MSA FPGA 11 Per-FPGA Control Signal 5 COM INPUT MSA_In_105 E10 MSA FPGA 11 Per-FPGA Control Signal 5 DIR INPUT MSA_In_105 D11 MSA FPGA 15 Per-FPGA Control Signal 0 COM INPUT MSA_In_106 E11 MSA FPGA 15 Per-FPGA Control Signal 0 DIR INPUT MSA_In_106 D12 MSA FPGA 15 Per-FPGA Control Signal 1 COM INPUT MSA_In_107 E12 MSA FPGA 15 Per-FPGA Control Signal 1 DIR INPUT MSA_In_107 D13 MSA FPGA 15 Per-FPGA Control Signal 2 COM INPUT MSA_In_108 E13 MSA FPGA 15 Per-FPGA Control Signal 2 DIR INPUT MSA_In_108 D14 MSA FPGA 15 Per-FPGA Control Signal 3 COM INPUT MSA_In_109 E14 MSA FPGA 15 Per-FPGA Control Signal 3 DIR INPUT MSA_In_109 D15 MSA FPGA 15 Per-FPGA Control Signal 4 COM INPUT MSA_In_110 E15 MSA FPGA 15 Per-FPGA Control Signal 4 DIR INPUT MSA_In_110 D16 MSA FPGA 15 Per-FPGA Control Signal 5 COM INPUT MSA_In_111 E16 MSA FPGA 15 Per-FPGA Control Signal 5 DIR INPUT MSA_In_111 D17 Common Control Signal 28 COM INPUT MSA_In_112 E17 Common Control Signal 28 DIR INPUT MSA_In_112 D18 Common Control Signal 29 COM INPUT MSA_In_113 E18 Common Control Signal 29 DIR INPUT MSA_In_113 D19 Common Control Signal 30 COM INPUT MSA_In_114 E19 Common Control Signal 30 DIR INPUT MSA_In_114 D20 Common Control Signal 31 COM INPUT MSA_In_115 E20 Common Control Signal 31 DIR INPUT MSA_In_115 D21 MSA FPGA 12 Per-FPGA Control Signal 0 COM INPUT MSA_In_116 E21 MSA FPGA 12 Per-FPGA Control Signal 0 DIR INPUT MSA_In_116 D22 MSA FPGA 12 Per-FPGA Control Signal 1 COM INPUT MSA_In_117 E22 MSA FPGA 12 Per-FPGA Control Signal 1 DIR INPUT MSA_In_117 D23 MSA FPGA 12 Per-FPGA Control Signal 2 COM INPUT MSA_In_118 E23 MSA FPGA 12 Per-FPGA Control Signal 2 DIR INPUT MSA_In_118 D24 MSA FPGA 12 Per-FPGA Control Signal 3 COM INPUT MSA_In_119 E24 MSA FPGA 12 Per-FPGA Control Signal 3 DIR INPUT MSA_In_119 D25 MSA FPGA 12 Per-FPGA Control Signal 4 COM INPUT MSA_In_120 E25 MSA FPGA 12 Per-FPGA Control Signal 4 DIR INPUT MSA_In_120 D26 MSA FPGA 12 Per-FPGA Control Signal 5 COM INPUT MSA_In_121 E26 MSA FPGA 12 Per-FPGA Control Signal 5 DIR INPUT MSA_In_121 D27 MSA FPGA 16 Per-FPGA Control Signal 0 COM INPUT MSA_In_122 E27 MSA FPGA 16 Per-FPGA Control Signal 0 DIR INPUT MSA_In_122 D28 MSA FPGA 16 Per-FPGA Control Signal 1 COM INPUT MSA_In_123 E28 MSA FPGA 16 Per-FPGA Control Signal 1 DIR INPUT MSA_In_123 D29 MSA FPGA 16 Per-FPGA Control Signal 2 COM INPUT MSA_In_124 E29 MSA FPGA 16 Per-FPGA Control Signal 2 DIR INPUT MSA_In_124 D30 MSA FPGA 16 Per-FPGA Control Signal 3 COM INPUT MSA_In_125 E30 MSA FPGA 16 Per-FPGA Control Signal 3 DIR INPUT MSA_In_125 D31 MSA FPGA 16 Per-FPGA Control Signal 4 COM INPUT MSA_In_126 E31 MSA FPGA 16 Per-FPGA Control Signal 4 DIR INPUT MSA_In_126 D32 MSA FPGA 16 Per-FPGA Control Signal 5 COM INPUT MSA_In_127 E32 MSA FPGA 16 Per-FPGA Control Signal 5 DIR INPUT MSA_In_127 ----------------------------------------------------------------------- P4: 160-pin E-style DIN connector for Trigger Framework P4 output bus ----------------------------------------------------------------------- Pin # Signal Description Dir Identifier ----- ------------------ --- ---------- A1 MSA FPGA 16 Scaler Out Bit 31 DIR OUTPUT MSA_Out_63 B1 MSA FPGA 16 Scaler Out Bit 31 COM OUTPUT MSA_Out_63 A2 MSA FPGA 16 Scaler Out Bit 31 DIR OUTPUT MSA_Out_62 B2 MSA FPGA 16 Scaler Out Bit 30 COM OUTPUT MSA_Out_62 A3 MSA FPGA 16 Scaler Out Bit 30 DIR OUTPUT MSA_Out_61 B3 MSA FPGA 16 Scaler Out Bit 29 COM OUTPUT MSA_Out_61 A4 MSA FPGA 16 Scaler Out Bit 29 DIR OUTPUT MSA_Out_60 B4 MSA FPGA 16 Scaler Out Bit 28 COM OUTPUT MSA_Out_60 A5 MSA FPGA 16 Scaler Out Bit 28 DIR OUTPUT MSA_Out_59 B5 MSA FPGA 16 Scaler Out Bit 27 COM OUTPUT MSA_Out_59 A6 MSA FPGA 16 Scaler Out Bit 27 DIR OUTPUT MSA_Out_58 B6 MSA FPGA 16 Scaler Out Bit 26 COM OUTPUT MSA_Out_58 A7 MSA FPGA 16 Scaler Out Bit 26 DIR OUTPUT MSA_Out_57 B7 MSA FPGA 16 Scaler Out Bit 25 COM OUTPUT MSA_Out_57 A8 MSA FPGA 16 Scaler Out Bit 25 DIR OUTPUT MSA_Out_56 B8 MSA FPGA 16 Scaler Out Bit 24 COM OUTPUT MSA_Out_56 A9 MSA FPGA 16 Scaler Out Bit 24 DIR OUTPUT MSA_Out_55 B9 MSA FPGA 16 Scaler Out Bit 23 COM OUTPUT MSA_Out_55 A10 MSA FPGA 16 Scaler Out Bit 23 DIR OUTPUT MSA_Out_54 B10 MSA FPGA 16 Scaler Out Bit 22 COM OUTPUT MSA_Out_54 A11 MSA FPGA 16 Scaler Out Bit 22 DIR OUTPUT MSA_Out_53 B11 MSA FPGA 16 Scaler Out Bit 21 COM OUTPUT MSA_Out_53 A12 MSA FPGA 16 Scaler Out Bit 21 DIR OUTPUT MSA_Out_52 B12 MSA FPGA 16 Scaler Out Bit 20 COM OUTPUT MSA_Out_52 A13 MSA FPGA 16 Scaler Out Bit 20 DIR OUTPUT MSA_Out_51 B13 MSA FPGA 16 Scaler Out Bit 19 COM OUTPUT MSA_Out_51 A14 MSA FPGA 16 Scaler Out Bit 19 DIR OUTPUT MSA_Out_50 B14 MSA FPGA 16 Scaler Out Bit 18 COM OUTPUT MSA_Out_50 A15 MSA FPGA 16 Scaler Out Bit 18 DIR OUTPUT MSA_Out_49 B15 MSA FPGA 16 Scaler Out Bit 17 COM OUTPUT MSA_Out_49 A16 MSA FPGA 16 Scaler Out Bit 17 DIR OUTPUT MSA_Out_48 B16 MSA FPGA 16 Scaler Out Bit 16 COM OUTPUT MSA_Out_48 A17 MSA FPGA 16 Scaler Out Bit 16 DIR OUTPUT MSA_Out_47 B17 MSA FPGA 16 Scaler Out Bit 15 COM OUTPUT MSA_Out_47 A18 MSA FPGA 16 Scaler Out Bit 15 DIR OUTPUT MSA_Out_46 B18 MSA FPGA 16 Scaler Out Bit 14 COM OUTPUT MSA_Out_46 A19 MSA FPGA 16 Scaler Out Bit 14 DIR OUTPUT MSA_Out_45 B19 MSA FPGA 16 Scaler Out Bit 13 COM OUTPUT MSA_Out_45 A20 MSA FPGA 16 Scaler Out Bit 13 DIR OUTPUT MSA_Out_44 B20 MSA FPGA 16 Scaler Out Bit 12 COM OUTPUT MSA_Out_44 A21 MSA FPGA 16 Scaler Out Bit 12 DIR OUTPUT MSA_Out_43 B21 MSA FPGA 16 Scaler Out Bit 11 COM OUTPUT MSA_Out_43 A22 MSA FPGA 16 Scaler Out Bit 11 DIR OUTPUT MSA_Out_42 B22 MSA FPGA 16 Scaler Out Bit 10 COM OUTPUT MSA_Out_42 A23 MSA FPGA 16 Scaler Out Bit 10 DIR OUTPUT MSA_Out_41 B23 MSA FPGA 16 Scaler Out Bit 9 COM OUTPUT MSA_Out_41 A24 MSA FPGA 16 Scaler Out Bit 9 DIR OUTPUT MSA_Out_40 B24 MSA FPGA 16 Scaler Out Bit 8 COM OUTPUT MSA_Out_40 A25 MSA FPGA 16 Scaler Out Bit 8 DIR OUTPUT MSA_Out_39 B25 MSA FPGA 16 Scaler Out Bit 7 COM OUTPUT MSA_Out_39 A26 MSA FPGA 16 Scaler Out Bit 7 DIR OUTPUT MSA_Out_38 B26 MSA FPGA 16 Scaler Out Bit 6 COM OUTPUT MSA_Out_38 A27 MSA FPGA 16 Scaler Out Bit 6 DIR OUTPUT MSA_Out_37 B27 MSA FPGA 16 Scaler Out Bit 5 COM OUTPUT MSA_Out_37 A28 MSA FPGA 16 Scaler Out Bit 4 DIR OUTPUT MSA_Out_36 B28 MSA FPGA 16 Scaler Out Bit 4 COM OUTPUT MSA_Out_36 A29 MSA FPGA 16 Scaler Out Bit 3 DIR OUTPUT MSA_Out_35 B29 MSA FPGA 16 Scaler Out Bit 3 COM OUTPUT MSA_Out_35 A30 MSA FPGA 16 Scaler Out Bit 2 DIR OUTPUT MSA_Out_34 B30 MSA FPGA 16 Scaler Out Bit 2 COM OUTPUT MSA_Out_34 A31 MSA FPGA 16 Scaler Out Bit 1 DIR OUTPUT MSA_Out_33 B31 MSA FPGA 16 Scaler Out Bit 1 COM OUTPUT MSA_Out_33 A32 MSA FPGA 16 Scaler Out Bit 0 DIR OUTPUT MSA_Out_32 B32 MSA FPGA 16 Scaler Out Bit 0 COM OUTPUT MSA_Out_32 C1 GROUND C2 +5.0V C3 GROUND C4 GROUND C5 GROUND C6 +3.3V C7 GROUND C8 GROUND C9 GROUND C10 -2.0V C11 GROUND C12 GROUND C13 GROUND C14 -4.5V C15 GROUND C16 GROUND C17 GROUND C18 GROUND C19 +5.0V C20 GROUND C21 GROUND C22 GROUND C23 +3.3V C24 GROUND C25 GROUND C26 GROUND C27 -2.0V C28 GROUND C29 GROUND C30 GROUND C31 -4.5V C32 GROUND D1 MSA FPGA 15 Scaler Out Bit 31 DIR OUTPUT MSA_Out_31 E1 MSA FPGA 15 Scaler Out Bit 31 COM OUTPUT MSA_Out_31 D2 MSA FPGA 15 Scaler Out Bit 31 DIR OUTPUT MSA_Out_30 E2 MSA FPGA 15 Scaler Out Bit 30 COM OUTPUT MSA_Out_30 D3 MSA FPGA 15 Scaler Out Bit 30 DIR OUTPUT MSA_Out_29 E3 MSA FPGA 15 Scaler Out Bit 29 COM OUTPUT MSA_Out_29 D4 MSA FPGA 15 Scaler Out Bit 29 DIR OUTPUT MSA_Out_28 E4 MSA FPGA 15 Scaler Out Bit 28 COM OUTPUT MSA_Out_28 D5 MSA FPGA 15 Scaler Out Bit 28 DIR OUTPUT MSA_Out_27 E5 MSA FPGA 15 Scaler Out Bit 27 COM OUTPUT MSA_Out_27 D6 MSA FPGA 15 Scaler Out Bit 27 DIR OUTPUT MSA_Out_26 E6 MSA FPGA 15 Scaler Out Bit 26 COM OUTPUT MSA_Out_26 D7 MSA FPGA 15 Scaler Out Bit 26 DIR OUTPUT MSA_Out_25 E7 MSA FPGA 15 Scaler Out Bit 25 COM OUTPUT MSA_Out_25 D8 MSA FPGA 15 Scaler Out Bit 25 DIR OUTPUT MSA_Out_24 E8 MSA FPGA 15 Scaler Out Bit 24 COM OUTPUT MSA_Out_24 D9 MSA FPGA 15 Scaler Out Bit 24 DIR OUTPUT MSA_Out_23 E9 MSA FPGA 15 Scaler Out Bit 23 COM OUTPUT MSA_Out_23 D10 MSA FPGA 15 Scaler Out Bit 23 DIR OUTPUT MSA_Out_22 E10 MSA FPGA 15 Scaler Out Bit 22 COM OUTPUT MSA_Out_22 D11 MSA FPGA 15 Scaler Out Bit 22 DIR OUTPUT MSA_Out_21 E11 MSA FPGA 15 Scaler Out Bit 21 COM OUTPUT MSA_Out_21 D12 MSA FPGA 15 Scaler Out Bit 21 DIR OUTPUT MSA_Out_20 E12 MSA FPGA 15 Scaler Out Bit 20 COM OUTPUT MSA_Out_20 D13 MSA FPGA 15 Scaler Out Bit 20 DIR OUTPUT MSA_Out_19 E13 MSA FPGA 15 Scaler Out Bit 19 COM OUTPUT MSA_Out_19 D14 MSA FPGA 15 Scaler Out Bit 19 DIR OUTPUT MSA_Out_18 E14 MSA FPGA 15 Scaler Out Bit 18 COM OUTPUT MSA_Out_18 D15 MSA FPGA 15 Scaler Out Bit 18 DIR OUTPUT MSA_Out_17 E15 MSA FPGA 15 Scaler Out Bit 17 COM OUTPUT MSA_Out_17 D16 MSA FPGA 15 Scaler Out Bit 17 DIR OUTPUT MSA_Out_16 E16 MSA FPGA 15 Scaler Out Bit 16 COM OUTPUT MSA_Out_16 D17 MSA FPGA 15 Scaler Out Bit 16 DIR OUTPUT MSA_Out_15 E17 MSA FPGA 15 Scaler Out Bit 15 COM OUTPUT MSA_Out_15 D18 MSA FPGA 15 Scaler Out Bit 15 DIR OUTPUT MSA_Out_14 E18 MSA FPGA 15 Scaler Out Bit 14 COM OUTPUT MSA_Out_14 D19 MSA FPGA 15 Scaler Out Bit 14 DIR OUTPUT MSA_Out_13 E19 MSA FPGA 15 Scaler Out Bit 13 COM OUTPUT MSA_Out_13 D20 MSA FPGA 15 Scaler Out Bit 13 DIR OUTPUT MSA_Out_12 E20 MSA FPGA 15 Scaler Out Bit 12 COM OUTPUT MSA_Out_12 D21 MSA FPGA 15 Scaler Out Bit 12 DIR OUTPUT MSA_Out_11 E21 MSA FPGA 15 Scaler Out Bit 11 COM OUTPUT MSA_Out_11 D22 MSA FPGA 15 Scaler Out Bit 11 DIR OUTPUT MSA_Out_10 E22 MSA FPGA 15 Scaler Out Bit 10 COM OUTPUT MSA_Out_10 D23 MSA FPGA 15 Scaler Out Bit 10 DIR OUTPUT MSA_Out_09 E23 MSA FPGA 15 Scaler Out Bit 9 COM OUTPUT MSA_Out_09 D24 MSA FPGA 15 Scaler Out Bit 9 DIR OUTPUT MSA_Out_08 E24 MSA FPGA 15 Scaler Out Bit 8 COM OUTPUT MSA_Out_08 D25 MSA FPGA 15 Scaler Out Bit 8 DIR OUTPUT MSA_Out_07 E25 MSA FPGA 15 Scaler Out Bit 7 COM OUTPUT MSA_Out_07 D26 MSA FPGA 15 Scaler Out Bit 7 DIR OUTPUT MSA_Out_06 E26 MSA FPGA 15 Scaler Out Bit 6 COM OUTPUT MSA_Out_06 D27 MSA FPGA 15 Scaler Out Bit 6 DIR OUTPUT MSA_Out_05 E27 MSA FPGA 15 Scaler Out Bit 5 COM OUTPUT MSA_Out_05 D28 MSA FPGA 15 Scaler Out Bit 4 DIR OUTPUT MSA_Out_04 E28 MSA FPGA 15 Scaler Out Bit 4 COM OUTPUT MSA_Out_04 D29 MSA FPGA 15 Scaler Out Bit 3 DIR OUTPUT MSA_Out_03 E29 MSA FPGA 15 Scaler Out Bit 3 COM OUTPUT MSA_Out_03 D30 MSA FPGA 15 Scaler Out Bit 2 DIR OUTPUT MSA_Out_02 E30 MSA FPGA 15 Scaler Out Bit 2 COM OUTPUT MSA_Out_02 D31 MSA FPGA 15 Scaler Out Bit 1 DIR OUTPUT MSA_Out_01 E31 MSA FPGA 15 Scaler Out Bit 1 COM OUTPUT MSA_Out_01 D32 MSA FPGA 15 Scaler Out Bit 0 DIR OUTPUT MSA_Out_00 E32 MSA FPGA 15 Scaler Out Bit 0 COM OUTPUT MSA_Out_00 ---------------------------------------------------------------------- P5: 34-pin front-panel connector for "global" signals ---------------------------------------------------------------------- Pin # Signal Description Dir Identifier ----- ------------------ --- ---------- 1 P5 Global I/O Signal 0 DIR BIDIR P5_IO_00 2 P5 Global I/O Signal 0 COM BIDIR P5_IO_00 3 P5 Global I/O Signal 1 DIR BIDIR P5_IO_01 4 P5 Global I/O Signal 1 COM BIDIR P5_IO_01 5 P5 Global I/O Signal 2 DIR BIDIR P5_IO_02 6 P5 Global I/O Signal 2 COM BIDIR P5_IO_02 7 P5 Global I/O Signal 3 DIR BIDIR P5_IO_03 8 P5 Global I/O Signal 3 COM BIDIR P5_IO_03 9 P5 Global I/O Signal 4 DIR BIDIR P5_IO_04 10 P5 Global I/O Signal 4 COM BIDIR P5_IO_04 11 P5 Global I/O Signal 5 DIR BIDIR P5_IO_05 12 P5 Global I/O Signal 5 COM BIDIR P5_IO_05 13 P5 Global I/O Signal 6 DIR BIDIR P5_IO_06 14 P5 Global I/O Signal 6 COM BIDIR P5_IO_06 15 P5 Global I/O Signal 7 DIR BIDIR P5_IO_07 16 P5 Global I/O Signal 7 COM BIDIR P5_IO_07 17 P5 Global I/O Signal 8 DIR BIDIR P5_IO_08 18 P5 Global I/O Signal 8 COM BIDIR P5_IO_08 19 P5 Global I/O Signal 9 DIR BIDIR P5_IO_09 20 P5 Global I/O Signal 9 COM BIDIR P5_IO_09 21 P5 Global I/O Signal 10 DIR BIDIR P5_IO_10 22 P5 Global I/O Signal 10 COM BIDIR P5_IO_10 23 P5 Global I/O Signal 11 DIR BIDIR P5_IO_11 24 P5 Global I/O Signal 11 COM BIDIR P5_IO_11 25 P5 Global I/O Signal 12 DIR BIDIR P5_IO_12 26 P5 Global I/O Signal 12 COM BIDIR P5_IO_12 27 P5 Global I/O Signal 13 DIR BIDIR P5_IO_13 28 P5 Global I/O Signal 13 COM BIDIR P5_IO_13 29 P5 Global I/O Signal 14 DIR BIDIR P5_IO_14 30 P5 Global I/O Signal 14 COM BIDIR P5_IO_14 31 P5 Global I/O Signal 15 DIR BIDIR P5_IO_15 32 P5 Global I/O Signal 15 COM BIDIR P5_IO_15 33 P5 Global I/O Signal 16 DIR BIDIR P5_IO_16 34 P5 Global I/O Signal 16 COM BIDIR P5_IO_16