***************************** * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * * and * * * * Level 2 Trigger Framework * * * * Tick-and-Turn Scaler FPGA * * * ***************************** Original: 14-MAY-1999 Latest: 17-JAN-2002 Introduction ------------ The Tick and Turn Scaler FPGA is used on the Scaler Module PCB to generate the Tick and Turn (Beam Crossing) Numbers: These are delivered to the SCL Hub End, and also available for Monitoring and High-Speed Read Out. Note that although only the Tick and Turn information is provided for monitor readout, a fourth, all '0' word is provided for HSRO. Each Tick and Turn Scaler has the following input and output connections: 1. On-Card Bus (including High-Quality Timing Signals). 2. High-Speed Readout Interface 3. 32 Common Control Signals (these are Main Signal Array (MSA) Input Signals). 4. 6 Unique (per-FPGA) Control Signals (these are also MSA Input Signals). 5. 32 Scaler Output Signals (these are MSA Output Signals). Not all of these connections are required to implement the Tick and Turn Scaling. Functionality ------------- Two different Tick and Turn Numbers are delivered to the SCL Hub End: (1) Front End Time Zone (2) Framework Time Zone Furthermore, the Framework Time Zone Tick and Turn Number has two different meanings, depending on whether the SCL is advertising a L1 Decision or a L2 Decision. The Tick Number is fundamentally 8 bits, ranging from 1 to 159, and indicates 132 ns accelerator "bunches," also termed Ticks. The Turn Number is 32 bits, ranging from 1 to 4,294,967,295, and indicates 21 us accelerator Turns. Note that this 32-bit number rolls over about once per 25 hours. All 32 bits of this number are available for Monitoring and High-Speed Readout. However, only 16 bits of Turn Number are delivered to the SCL Hub End. This 16-bit Turn Number rolls over about once a second. The Front End Time Zone Tick and Turn Number receives somewhat different processing from the Framework Time Zone Tick and Turn Number. I will indicate the Tick and Turn Number with a value pair, (Tick, Turn), in the below examples. Note that the behavior below is defined at the Front Ends. The values sent from the Framework must run "ahead" enough to account for cable and transport delays. This is accomplished by shifting the control signals sent from the Carmen Master Clock earlier in time. This specifically involves the Turn Marker. To reduce the number of timing signals required, in practice the same timing signal is used; when necessary the Turn Marker is passed through a 26 stage shift register in order to delay it. On the first Tick of the first Turn following an SCL Initialize, the Front End Time Zone Tick and Turn Number takes the value (1, 1). It increments once per Tick until the final Tick of the first Turn, when it has the value of (1, 159). On the first Tick of the next Turn, it takes the new value (2, 1), and continues incrementing in this fashion until either the Turn Number rolls over to (0, 1) or the next SCL Initialize. It is undefined (?) until the first Tick of the first Turn following an SCL Initialize. The SCL transports the Front End Time Zone Tick and Turn Number with every frame. For L1 Decisions, the Framework Time Zone Tick and Turn Number runs 26 Ticks behind the Front-End Time Zone Tick and Turn Number. It thus indicates (1, 1) starting with the 27th Tick of the first Turn after an SCL Initialize. On the final Tick of this Turn, it has the value (1, 133). It takes the value (2, 1) on the 27th Tick of the second Turn, and continues incrementing in this fashion until either the Turn Number rolls over to (0, 1) or the next SCL Initialize. It is undefined (?) until the 27th Tick of the first Turn following an SCL Initialize. When the SCL is advertising L1 Decisions, the Framework Time Zone Tick and Turn Number indicates which crossing the L1 Decision applies to. With every L1 Accept, this number is "stamped" on the event in the VRB. When the SCL is advertising L2 Decisions, the meaning of the Framework Time Zone Tick and Turn Number changes. Rather than being just a constant offset from the Front End Time Zone TTN, it instead indicates which L1 Accept this L2 Decision refers to. This FPGA thus requires a FIFO and Mux to store the Tick and Turn Number with every L1 Accept, and deliver it with every L2 Decision. Recall that L2 Decisions are provided IN ORDER, simplifying the task of providing these numbers. This FPGA must therefore have a FIFO, which is used to store the Framework Time Zone Tick and Turn Number with each L1 Accept, and re-present it to the SCL Hub End with every L2 Decision (through a mux). The Tick and Turn Scaler and the FIFO Read and Write Address Counters can be reset in a number of different ways. Register 2 can be used to enable either or both of these to be reset when the P1 Reset Timing Signal is asserted. Register 3 can be used to force either or both of these to reset for as long as a bit is set to "1" in this register. Register 12 can be used to enable the SCL_Initialize signal to reset either or both of these. The TTS has an additional function, that of comparing the current tick to an array of 8 programmable values, and setting output signals indicating whether the current tick matches the selected tick. These outputs are updated with the Tick Clock. They will need to be re-timed with the TRM Clock before being injected into the TRM, to avoid race conditions in that card. Programming Interface --------------------- The TTS FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Enable Timing Signal Reset 3 R/W Force Scaler Reset 8 R/W FIFO Control Status Register 9 R FIFO Error Reporting Register 10 R FIFO Counter Status Register 12 R/W Output Tick & Turn Selection and Control SCL_Init Reset 16 R/W Turn Marker Selection 24 R HSRO State 25 R/W HSRO Terminal Count 26 R HSRO Current Count 32 R/W History Shift Register Control Reg 36 R Monitor Readout of Turn LSB 37 R Monitor Readoutof Turn MSB 38 R Monitor Readout of Tick 40 R/W Tick Select 0 Output Control 41 R/W Tick Select 1 Output Control 42 R/W Tick Select 2 Output Control 43 R/W Tick Select 3 Output Control 44 R/W Tick Select 4 Output Control 45 R/W Tick Select 5 Output Control 46 R/W Tick Select 6 Output Control 47 R/W Tick Select 7 Output Control The bit allocation in each of these registers is: Chip Control Status Register LSW (Register Address 0) Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Chip Interrupt Request ('1': request interrupt) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 3:15 --- not allocated The Chip Status Register MSW is currently unused (Register Address 1) Enable Timing Signal Reset (Register Address 2) Bit Access Contents --- ------ -------- 0 R/W Enable Timing Signal Reset of Scaler 1 R/W Enable Timing Signal Reset of FIFO Read and Write Counters 15:2 R/W not allocated Force Scaler Reset (Register Address 3) Bit Access Contents --- ------ -------- 0 R/W Force Reset of Scaler 1 R/W Force Reset of FIFO Read and Write Counters 15:2 R/W not allocated FIFO Control Status Register (Register Address 8) Bit Access Contents --- ------ -------- 0 R/W Enable "FIFO Full" Error Checking 1 R/W Enable "FIFO Empty" Error Checking 7:2 R/W Unallocated 8 R/W Enable Automatic Error Clearing 9 R/W Manually Clear Errors (Only meaningful when Automatic Error Clearing is disabled. TCC must pulse this bit high and then back low again) 15:10 R/W Unallocated FIFO Error Reporting Register (Register Address 9) Bit Access Contents --- ------ -------- 0 R FIFO Full Error (Latched) 1 R FIFO Empty Error (Latched) 7:2 R Unallocated 8 R FIFO Error Flag (logical OR of bits 1:0) 15:9 R Unallocated FIFO Counter Status Register (Register Address 10) Bit Access Contents --- ------ -------- 4:0 R FIFO DPRAM Write Address (see note below) 7:5 R Unallocated 12:8 R FIFO DPRAM Read Address (see note below) 15:13 R Unallocated FIFO DPRAM Write/Read Addresses do NOT progress in standard binary sequence. They progress in a modified Grey code as follows: 0 0x00 00000 (reset state) 1 0x01 00001 3 0x03 00011 7 0x07 00111 6 0x06 00110 5 0x05 00101 2 0x02 00010 4 0x04 00100 8 0x08 01000 9 0x09 01001 11 0x0b 01011 15 0x0f 01111 14 0x0e 01110 13 0x0d 01101 10 0x0a 01010 12 0x0c 01100 24 0x18 11000 25 0x19 11001 27 0x1b 11011 31 0x1f 11111 30 0x1e 11110 29 0x1d 11101 26 0x1a 11010 28 0x1c 11100 16 0x10 10000 17 0x11 10001 19 0x13 10011 23 0x17 10111 22 0x16 10110 21 0x15 10101 18 0x12 10010 20 0x11 10100 0 0x00 00000 (sequence begins again) Output Tick & Turn Selection and Control SCL_Init Reset (Register Adrs 12) Bit Access Contents --- ------ -------- 0 R/W Select the source of the Tick and Turn numbers 0: Output is always the current Tick and Turn 1: Output comes from a FIFO when a L2 Decision is being advertised 7:1 R/W Unallocated 8 SCL_Init Reset of the Tick and Turn Scaler 0 -> Disable SCL_Init reset of the scaler 1 -> Enable SCL_Init reset of the scaler 9 SCL_Init Reset of FIFO Read and Write Counters 0 -> Disable SCL_Init reset of the FIFO R/W Counters 1 -> Enable SCL_Init reset of the FIFO R/W Counters 15:10 R/W Unallocated Turn Marker Selection (Register Address 16) Bit Access Contents --- ------ -------- 0 R/W Select the delay for the Turn Marker 0: no delay 1: delay the Turn Marker by 26 ticks 15:1 R/W Unallocated HSRO State (Register Address 24) Bit Access Contents --- ------ -------- 0 R HSRO_DCE_IN* 1 R HSRO_DCE_OUT* 2 R Enable HSRO_Data 15:3 R not allocated HSRO Terminal Count (Register Address 25) Bit Access Contents --- ------ -------- 3:0 R/W Number of Words for High-Speed Readout (MUST be greater than 0 if chip HSRO is enabled) 14:4 R/W not allocated 15 R/W Enable HSRO from this Chip (0: DCE_In* passes directly through to DCE_Out* 1: DCE_Out* is generated by the terminal count comparator) History Shift Register Control Reg (Register Address 32) Bit Access Contents --- ------ -------- 2:0 R/W Depth in stage 1 of BXHSR 15:3 R/W unallocated Monitor Readout of Tick (Register Address 38) Bit Access Contents --- ------ -------- 7:0 R Tick 15:8 not allocated Tick Select Output Control (e.g. Register Address 40) Bit Access Contents --- ------ -------- 7:0 R/W Selected Tick (need to calibrate this by knowing the delay before this output signal is set to the TRM, i.e. to select Tick program ? 15:8 R/W not allocated