Tick and Turn Scaler Usage
                    ------------------------------

                                               Original Rev.  7-MAR-2000
                                                Current Rev. 23-MAR-2000


This file describes how the Tick and Turn Scaler FPGA's are actually connected
and used in the Run II Framework.

The  "Current BX Number"  and the  "L1 Trigger BX Number"  Tick and Turn 
Scalers are both located on the same SM THE-Card.  This is in the M123
bottom crate slot 21 and is accessed as: Master 1, Slave 2, Slot 21

The Current BX Number is generated by FPGA Chip 15.  Its electrical outputs
are:
        MSA(7:0):       Tick
        MSA(15:8):      unused
        MSA(31:16):     Turn

The Geo Sect L1 Trigger Number is generated by FPGA Chip 16.  Its electrical
outputs are:

        MSA(39:32)      Tick
        MSA(43:40)      Tick Select signals 3:0 
        MSA(47:44)      unused
        MSA(63:48)      Turn


The 4 Tick Select signals from the Geo Sect L1 Trigger Number Tick and Turn
Scaler are connected to And-Or Network Terms 254 through 251 in the following
way:
     And-Or Term 254       Tick Select Comparator #3
     And-Or Term 253       Tick Select Comparator #2
     And-Or Term 252       Tick Select Comparator #1
     And-Or Term 251       Tick Select Comparator #0

  
Both of the Current BX and the L1 Trigger Number Tick and Turn scalers need 
to receive a copy of the SCL Initialize signal so that the Tick and Turn 
Numbers can start up correctly after and SCL Initialize.  They receiver a 
copy of the SCL Initialize signal via the  MSA_In(1)  input to this SM card.


The Geo Sect L1 Trigger Number Tick and Turn Scaler has a FIFO that stores
the Tick and Turn Number that is used to identify each L1 Accept that is
issued by the L1 FW.  These numbers are needed later when the L2 Decisions are
issued.  The Write Enable for this FIFO is a delayed (by about 30 nsec) copy
of the L1 Fired Strobe signal.  This signal is received by the Tick and Turn
SM card on MSA_In(0).