***************************** * * * Trigger Decision Module * * * * FPGA Description * * * * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * ***************************** Original: 18-MAR-1998 Latest: 16-MAY-2003 Introduction ------------ The basic function of the Trigger Decision Module (TDM) is to combine all of the components of the L1 triggering decision (e.g. Physics And-Or Fired, Exposure Group And-Or Fired, Front-End Busy, Global Disables, etc) to produce the Specific Trigger Fired decisions. This document concentrates on the architecture and implementation of the TDM FPGA. The TDM FPGA is used in all MSA FPGA locations on the TDM cards. Each TDM FPGA has the following input and output connections: 1. On-Card Bus (including High-Quality Timing Signals). 2. 2 Physics Partial And-Or Fired (PAOF) Signals 3. 16 (8 pairs) Exposure Group Partial And-Or Fired Signals 4. 18 DAQ Disable Signals - 8 Exposure Group Front-End Busy Disable Signals - 2 Individual Specific Trigger Disable Signals - 4 Correlated Global Specific Trigger Disable Signals - 4 Decorrelated Global Specific Trigger Disable Signals 5. 3 Output Signals - 1 Specific Trigger Fired Signal - 2 unused 6. Diagnostic Bus Bit Contents --- ---- 0 Beam Crossing Clock 1 Capture High Speed Readout Data 2 Capture Monitor Data 3 Specific Trigger Fired 4 Specific Trigger Fired for the Triggered Tick 5 Specific Trigger Exposed 6 And-Or Fired 7 Exposure Group Enable 8 DAQ Enable Decorrelated 9 DAQ Enable Correlated 10 Prescaler Disable 11 Auto Disable 12 OR of the Individual Specific Trigger Disables (1:0) 13 OR of the Decorrelated Global ST Disables (3:0) 14 OR of the Correlated Global ST Disable (3:0) 15 Front End Busy 7. Mark and Force Pass Flag (on Board Global I/O Note that although all the FPGAs have the diagnostic bus implemented, FPGA #16 is the only one for which the relevant pins are connected to traces on the board. Operation--General Comments --------------------------- The TDM FPGA is composed of the following elements: 1. On-Card Bus Interface 2. High-Speed Readout Interface 3. Triggering Logic 4. Readout Data Logic, consisting of A. Beam Crossing History Shift Register B. Monitor Data Scalers C. High-Speed Data Capture and Readout 5. Mark and Force Pass Generator Each element is described below. 1. On-Card Bus Interface This is the standard On-Card Bus Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. 2. High-Speed Readout Interface This is the standard High-Speed Readout Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. 3. Triggering Logic The TDM uses a P1 Timing Signal to latch all of the "real-time" inputs shown below. These signals are combined as shown below: State Lower | +-----+ +-Scaler >--------+------| | | +-State* One Pair | OR |--+ +-State* | of Spec Program- +-/--O | | +-----+ | +-Scaler Trig mable | 1 +-----+ +-/-| | | +-----+ | Physics Obey--/--+ 1 | AND |-/-+----| | 1 | And-Or 2 | +-----+ +-/-| | 1 | AND |-/-------+---------> Partial +-/--O | | 1 +-----+ +---| | Spec Trig Decision Upper 1 | OR |--+ | +-----+ Fired >--------+------| | | | +-----+ +---------------------+ State | Eight | Pairs of Lower +-----+ +-----+ State | Exposure>-------------/-| | | | | +-State* | Group 8 | OR |-/-| AND |-/-+ | +-State* Partial Program- +-/-O | 8 | | 1 | +-----+ | | Enable mable | 8 +-----+ +-----+ +--| | | +-Scaler . Obey --/--+ | AND |-/-+ | . 16 | +-----+ +-----+ +--| | 1 | | . +-/-O | | | | +-----+ | +-----+ | . Upper 8 | OR |-/-| AND |-/-+ +--| | 1 | . . . >-------------/-| | 8 | | 1 | | AND |-/-+ 8 +-----+ +-----+ | +--| | Spec State | +-----+ Trig | Exposed | Exposure +-------------+ Group No State | Front-End | +-----+ +-----+ +-State | Busy >--------+----/-| | | | | | Disable 8 | AND |-/-| OR |-/-+ Spec Trig | Programmable--/-| | 8 | | 1 | DAQ Enable | Obey 8 +-----+ +-----+ | +-----+ Correlated | +--| | Contribution | Correlated | NOR O-/-+ | Global No State +--| | 1 | | Spec Trig | +-----+ No Scaler | +-----+ +-State* | Disable >--------+----/-| | | | | | 4 | AND |-/-+-+-------+ +-Scaler | No Programmable--/-| | 4 | | +-State Obey 4 +-----+ State | | | +-----+ +-Scaler +-/-| | 1 | 1 | AND |-/-+ Decorrelated +-/-| | Spec Trig Global State | 1 +-----+ DAQ Enable Spec Trig | +-----+ No Scaler | Disable >--------+----/-| | | | 4 | AND |-/-+-+--------+ | Programmable--/-| | 4 | | | Obey 4 +-----+ State | | | | Individual State | | Spec Trig | +-----+ No Scaler | | Disable >--------+----/-| | | | +-Scaler 2 | AND |-/-+-+------+ | +-----+ | Programmable--/-| | 2 | | +-| | +-State* Obey 2 +-----+ State +---| | 1 | +-----| NOR O-/-+ +-------+ | +---| | Spec Trig |Pre- | +-----+ Scaler | | +-| | DAQ Enable |Scaler |------| | | | | | +-----+ Decorrelated |Logic | | AND |-/-+-+----+ | | Contribution +-------+ +--| | 1 | | | | +-----+ State | | Programmable-+ | | Notes:-All States are Obey | | for HSRO (High | | Speed Readout) +-------+ | | |Auto- | +-----+ Scaler | | (*)-States flagged |Disable|------| | | | | with a star (*) |Logic | | AND |-/-+-+------+ | must readout the +-------+ +--| | 1 | | states for current, | +-----+ State | previous, and next Programmable-+ | Beam Crossings Enable Scaler | | | -All scalers are Programmable------------/-+-+--------+ monitoring only COOR Disable 1 | State A single copy of each Specific Trigger Fired signal is buffered and driven off-card as described above. All sources of Disable above are each individually gateable via TCC (as in the Run I FSTD). Very little specific mapping of disables to sources has been done so far. The only known Global Disable is the one used to prevent the Trigger Framework from firing on two successive Beam Crossings; the method used during run I (i.e. using And-Or Terms) cannot be used during Run II because the system is pipelined and the And-Or Terms for the following Beam Crossing are latched before the Trigger Decision for the current crossing has been made. This functionality is implemented using Correlated Global Disable #3 input. TDM Prescaler: This is a description of the January 2003 version of the Run II PreScaler. This is the fully random PreScaler and consists of: a 32 bit Random Number Generator, a 32 bit register to hold the PreScaler Threshold Value a 32 bit Comparator to compare the Random Number to the PreScaler Threshold Value. The Specific Trigger is enabled for a given tick if for that tick the Random Number is equal to or greater than the PreScaler Threshold Value. The 32 bit Random Number Generator consists of 32 separate shift registers. Each shift register is 48 stages long (numbered 1:48), has XOR feedback from stages 20, 21, 47, and 48, and generates 1 bit of the 32 bit wide random number. The shift register output that becomes part of the random number is taken from stage 48 of each shift register. The 32 bit PreScaler Threshold Value is stored in two 16 bit registers. These are at Register Addresses 128 and 129. Register 128 is the least significant 16 bit word of the 32 bit Prescaler Threshold Value and register 129 is the MSWord of the threshold value. List of registers involved with the PreScaler Register Address Type Function -------- ------- ----------------------- 128 R/W PreScaler Comparator Threshold Register bits 15:0 129 R/W PreScaler Comparator Threshold Register bits 31:16 130 R/W Prescaler Control Register (all 16 bits are R/W) bit 0 Normal_Run bit 1 Single_Step bit 4 Load/Shift_Bar 131 R/W Seed bits for Shift Registers that Generate Random Number bits 15:0 132 R/W Seed bits for Shift Registers that Generate Random Number bits 31:16 133 Rd Only Reads back Random Number Generator output bits 15:0 134 Rd Only Reads back Random Number Generator output bits 31:16 Register Address 130 is the Control Register for the Random Number Generator. At this time only 3 bits in this 16 bit register are used. All 16 bits are read/write bits. The assignment of the 3 used bits is the following: Bit Bit Number Value Bit Name Function ------ ----- ----------- -------------------------------------- 0 $0001 Normal_Run Setting a "1" enables the Random Number Generator to shift once every tick and thus produce a new random number once every tick. Setting a "0" stops the Random Number Generator from shifting once every tick. 1 $0002 Single_Step Changing this bit from "0" to "1" enables the Random Number Generator to make a single shift. Changing this bit from "1" to "0" has no effect. Loading a "0" is the safe quiescent state. 4 $0010 Load/Shift_Bar Setting a "0" causes the input to each of the 32 48 bit long shift registers to be the XOR of stages 20, 21, 47, and 48 of that shift register. Setting a "1" causes the input to each of the 32 shift registers to be the contents of the corresponding bit in the 32 bit wide Random Number Generator Seed Register. Register Addresses 131 and 132 make up the Random Number Generator Seed Register. Register address 131 is the least significant 16 bit word of the Seed Register and register address 132 is the MSWord of the Seed Register. The LSBit of register 131 supplies the seed value to the shift register that generates the LSBit of the 32 bit random number. The MSBit of register 132 supplies the seed value to the shift register that generates the MSBit of the 32 bit random number. Supplies the Seed Value to the Shift Register Seed Register Bit that makes bit "N" of the 32 bit Random Number ----------------- ---------------------------------------------- RA = 131 LSBit Supplies seed to the shift register that generates random number bit 0. RA = 131 MSBit Supplies seed to the shift register that generates random number bit 15. RA = 132 LSBit Supplies seed to the shift register that generates random number bit 16. RA = 132 MSBit Supplies seed to the shift register that generates random number bit 32. To load a seed into the 32 bit Random Number Generator do the following steps: Load Register Value Intent ---------------- ----- ------------------------------------- Control Register $0000 Disable the Random Number Generator shift registers from normal once per tick shifting. Control Register $0010 Enable the Seed Register to supply the input to the Random Number Generator shift registers. Seed Reg Adrs 131 $wxyz Load the Seed Register with the first Seed Reg Adrs 132 $klmn value that you want loaded into the shift registers. One bit from the Seed Register goes to each of the 32 shift registers as defined above. Control Register $0012 Single Step the shift registers. Control Register $0010 Return Single Step to quiescent value. Repeat loading the Seed Register and single stepping the shift registers 47 more times so that you have loaded data into all 48 stages of the shift registers. Then Control Register $0000 Disable all shifting of the shift registers. Input to each shift register now comes from the XOR of stages 20, 21 47, and 48 of that shift register. Control Register $0001 Enable normal running of the shift registers, i.e. shift once every 132 nsec tick. There are two 16 bit read only registers that allow you to read the current value of the 32 bit Random Number that is generated by the Random Number Generator. There is no "latching" involved in these read back registers - you just read the current instantanious output of the Random Number Generator. So it basically only makes sense to read from these read back registers when you are single stepping the Random Number Generator. Register Address 133 Reads back output bits 15:0 from the Random Number Generator Register Address 134 Reads back output bits 31:16 from the Random Number Generator TDM Readout HSRO and Monitor: All of the signals marked with "State" above are available for fast optical readout with each L1 Trigger for the Triggered Beam Crossing. This requires pipeline storage to account for the L1 Trigger Framework latency. Additionally, this Data Block information is available for Monitor readout as well. See below for details. All of the signals marked with "Scaler" are scaled and available for monitor readout at any time. These scalers are 32-bit scalers and are included on the TDM. Note that a 32-bit scaler rolls over at most once per 9.4 minutes. See below for details. 4. Readout Data Logic The Readout Data Logic includes A. Beam Crossing History Shift Register B. Monitor Data Scalers C. High-Speed Data Capture and Readout 4.A Beam Crossing History Shift Register The basic principle of the Beam Crossing History Shift Register (BXHSR) is to hold the information to be readout from the time it arrives until the readout signal arrives. The signals of interest from the Triggering Logic are fed to a shift register of an appropriate width and length. The clock for this shift register is again the BX Clock. The stage of the BXHSR which is tapped is programmable via TCC. Currently latencies between 3 and 7 are supported. Note that since the Monitor Data Scalers essentially count as a stage of the BXHSR, any signals going to the scalers should be tapped one stage before signals going to the High-Speed Data Holding Registers. This adjustment is automatically accounted for in the scaler outputs of the BXHSR. 4.B Monitor Data Scalers The Monitor Data Scalers will consist of approximately nine Scaler Channels with the following components: i. 32-bit Resettable Scaler ii. 32-bit Monitor Data Holding Register 4.B.i 32-bit Resettable Scaler The actual scaling function of each Scaler Channel is performed by a 32-bit scaler (a logiblox cc32re with synchronous reset). All Scaler Channels use the same clock, the BX Clock. This is a P1 Timing Signal which is distributed to the FPGA via HQ Timing Signal #0. Each Scaler Channel uses a separate clock enable signal from the Beam Crossing History Shift Register. Each Scaler Channel also uses a separate reset signal. The Scaler Reset can come from a High-Quality Timing Signal or from a VME-visible register. The High-Quality Timing Signal reset must be enabled by TCC, but the register reset can be used to force a scaler reset at any time. The Scaler Reset passes through the Beam Crossing History Shift Register with the same latency as the data which is being scaled. The output from each scaler is the 32-bit Scaler Channel Count. 4.B.ii 32-bit Monitor Data Holding Register Each Scaler Channel has an associated 32-bit Monitor Data Holding Register which receives the Scaler Channel Count. This register can be readout by TCC via VME as a pair of 16-bit registers. All of the Monitor Data Holding Registers are clocked by the BX Clock. The clock enable for the registers is controlled by the Capture Monitor Data signal which arrives on the TDM card as a P1 Timing signal and has a private connection from the BSF FPGA to all MSA FPGAs. Note that the Capture Monitor Data signal only enables the transfer of the data; the actual transfer occurs with the rising edge of the BX Clock. TCC reads these registers via normal VME cycles. Note that new monitor data should not be captured until TCC has read all of the previous monitor data. 4.C High-Speed Data Capture and Readout The states which are available for high-speed readout are passed from the Beam Crossing History Shift Register to a High-Speed Data Holding Register and to a Monitor Data Holding Register. Both of these registers are clocked by the BX Clock. The clock enables are controlled by the Capture High-Speed Readout signal and the Capture Monitor Data Signal respectively. As with the Monitor Data Holding Registers for the scalers, the capture data signals enable the transfer of data, but the transfer actually occurs on the rising edge of the BX Clock. The data from the High-Speed Data Holding Register will be put on the High-Speed Data Bus when the appropriate High-Speed Read Register signal is asserted. The data from the Monitor Data Holding Register can be readout by TCC via VME in the usual way. 5. Mark and Force Pass Generator The Mark and Force Pass Generator is a synchronous down counter that is clocked by the BX_Clk signal. This counter is called the MFP Counter. It changes state only on the positive edge of BX_Clk AND only when its Clock Enable input is asserted. The Clock Enable input to the MFP Counter is asserted when the Specific Trigger Fired signal is asserted OR when bit #31 of the Mark and Force Pass Control Register is asserted. The MFP Counter can perform only two different operations: Load and Decrement. The Load operation takes precedence over the Decrement operation. The 24 bits of data that are loaded into the MFP Counter during a Load operation come from bits 23:0 of the Mark and Force Pass Control Register. There are two situations that will cause a Load operation to take place. If bit #31 of the Mark and Force Pass Control Register is asserted then a Load operation will happen on each positive edge of the BX_Clock. In this way TCC can load the MFP Counter. A Load operation also takes place anytime the MFP Counter is at its "terminal count" and the Specific Trigger Fired signal is asserted. The value of "terminal count" for the MFP Counter is zero. A Decrement operation takes place each time the Specific Trigger Fires. Note that this operation happens on the positive edge of BX_Clk following the BX_Clk that brought the data into the TDM that caused the Specific Trigger to Fire. That is, MFP Counter Decrements one clock after the input latches to the TDM update. The output of the Mark and Force Pass Generator is the MFP_Flag signal. This signal is asserted only when the MFP Counter is at its terminal count AND the Specific Trigger Fired signal is asserted. Notes: If TCC wants the MFP_Flag asserted every other time this Specific Trigger fires then I think it should load the value $000001 into bits 23:0 of the Mark and Force Pass Control Register. If TCC wants the MFP_Flag asserted every time this Specific Trigger fires then I think it should load the value $000000 into bits 23:0 of the Mark and Force Pass Control Register. Programming Interface --------------------- The Trigger Decision Module FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Enable Timing Signal Reset 3 R/W Force Scaler Reset 24 R High-Speed Readout State 25 R/W High-Speed Readout Terminal Count 26 R High-Speed Readout Current Count 32 R/W Tick History Shift Register Control Reg 36 R Monitor States (LSW) 37 R Monitor States (MSW) 40 R Scaler Channel 0: Specific Trigger Fired (LSW) 41 R Scaler Channel 0: Specific Trigger Fired (MSW) 42 R Scaler Channel 1: Specific Trigger Exposed (LSW) 43 R Scaler Channel 1: Specific Trigger Exposed (MSW) 44 R Scaler Channel 2: Physics And-Or Fired (LSW) 45 R Scaler Channel 2: Physics And-Or Fired (MSW) 46 R Scaler Channel 3: DAQ Enable (LSW) 47 R Scaler Channel 3: DAQ Enable (MSW) 48 R Scaler Channel 4: Decorrelated DAQ Enable (LSW) 49 R Scaler Channel 4: Decorrelated DAQ Enable (MSW) 50 R Scaler Channel 5: Correlated DAQ Enable (LSW) 51 R Scaler Channel 5: Correlated DAQ Enable (MSW) 52 R Scaler Channel 6: Prescaler Disable (LSW) 53 R Scaler Channel 6: Prescaler Disable (MSW) 54 R Scaler Channel 7: COOR Disable (LSW) 55 R Scaler Channel 7: COOR Disable (MSW) 56 R Scaler Channel 8: Auto Disable (LSW) 57 R Scaler Channel 8: Auto Disable (MSW) 73:72 R/W Mark and Force Pass Control 80 R/W Exposure Group Partial Enable Selection 81 R/W Front End Busy and Global Disable Selection 82 R/W Individual Disable, Prescaler, Auto Disable Selection PAOF Ignore and EGPE Ignore, and COOR Disable 84 R/W Auto Disable Control 128 R/W PreScaler Comparator Threshold Register bits 15:0 129 R/W PreScaler Comparator Threshold Register bits 31:16 130 R/W Prescaler Control Register (all 16 bits are R/W) bit 0 Normal_Run bit 1 Single_Step bit 4 Load/Shift_Bar 131 R/W Seed bits for the Prescaler Shift Registers that Generate Random Number bits 15:0 132 R/W Seed bits for the Prescaler Shift Registers that Generate Random Number bits 31:16 133 R Reads back the Prescaler Random Number Generator output bits 15:0 134 R Reads back the Prescaler Random Number Generator output bits 31:16 The bit allocation in each of these registers is given below. The Chip Control Status register (Register Address 0 and 1) is currently unused. Enable Timing Signal Reset Register Address = 2 Bit Access Contents --- ------ -------- 0 R/W Enable Timing Signal Reset for Channel 0 Scaler 1 R/W Enable Timing Signal Reset for Channel 1 Scaler 2 R/W Enable Timing Signal Reset for Channel 2 Scaler 3 R/W Enable Timing Signal Reset for Channel 3 Scaler 4 R/W Enable Timing Signal Reset for Channel 4 Scaler 5 R/W Enable Timing Signal Reset for Channel 5 Scaler 6 R/W Enable Timing Signal Reset for Channel 6 Scaler 7 R/W Enable Timing Signal Reset for Channel 7 Scaler 8 R/W Enable Timing Signal Reset for Channel 8 Scaler 15:9 R/W not allocated Force Scaler Reset Register Address = 3 Bit Access Contents --- ------ -------- 0 R/W Force Reset for Channel 0 Scaler 1 R/W Force Reset for Channel 1 Scaler 2 R/W Force Reset for Channel 2 Scaler 3 R/W Force Reset for Channel 3 Scaler 4 R/W Force Reset for Channel 4 Scaler 5 R/W Force Reset for Channel 5 Scaler 6 R/W Force Reset for Channel 6 Scaler 7 R/W Force Reset for Channel 7 Scaler 8 R/W Force Reset for Channel 8 Scaler 15:9 R/W not allocated HSRO State Register Address = 24 Bit Access Contents --- ------ -------- 0 R HSRO_DCE_IN* 1 R HSRO_DCE_OUT* 2 R Enable_HSRO_Data 15:3 R not allocated HSRO Terminal Count Register Address = 25 Bit Access Contents --- ------ -------- 3:0 R/W Number of Words for High-Speed Readout (MUST be greater than 0 if chip HSRO is enabled) 14:4 R/W not allocated 15 R/W Enable HSRO from this Chip (0: DCE_In* passes directly through to DCE_Out* 1: DCE_Out* is generated by the terminal count comparator) Tick History Shift Register Control Reg Register Address = 32 Bit Access Contents --- ------ -------- 2:0 R/W Depth in stage 1 of BXHSR 15:3 R/W unallocated Monitor States LSW Register Address = 36 Bit Access Contents --- ------ -------- 0 R Specific Trigger Fired: Triggered Tick 1 R Specific Trigger Exposed: Previous Tick 2 R Specific Trigger Exposed: Next Tick 3 R And-Or Fired: Previous Tick 4 R And-Or Fired: Next Tick 5 R Gated Partial And-Or Fired Lower Bits: Triggered Tick 6 R Gated Partial And-Or-Fired Upper Bits: Triggered Tick 7 R Selected Exposure Group Enable: Previous Tick 8 R Selected Exposure Group Enable: Next Tick 9 R Exposure Group Partial Enable Lower: Triggered Tick 10 R Exposure Group Partial Enable Upper: Triggered Tick 11 R Decorrelated DAQ Enable: Previous Tick 12 R Decorrelated DAQ Enable: Triggered Tick 13 R Decorrelated DAQ Enable: Next Tick 14 R Correlated DAQ Enable: Triggered Tick 15 R Prescaler Disable: Triggered Tick Monitor States MSW Register Address = 37 Bit Access Contents --- ------ -------- 0 R COOR Disable: Triggered Tick 1 R Auto Disable: Triggered Tick 3:2 R Gated Individual Disables: Triggered Tick 4 R Front End Busy Disable: Triggered Tick 8:5 R Gated Decorrelated Global Disables: Triggered Tick 12:9 R Gated Correlated Global Disables: Triggered Tick 13 R Gated Correlated Global Disable(3): Next Tick (aka Skip Next Tick Disable for the Next Tick) 14 R Mark and Force Pass Flag: Triggered Tick 15 not allocated Mark and Force Pass Control Reg Register Address = 73:72 Bit Access Contents ----- ------ -------- 23:0 R/W This is the 24 bit value that will be loaded into the MFP Counter the next time it does a load operation. 30:24 R/W unused but will readback as written. 31 R/W By asserting this bit TCC can cause the value stored in bits 23:0 of this register to be immediately loaded into the MFP Counter. Exposure Group Partial Enable Selection Register Address = 80 Bit Access Contents --- ------ -------- 7:0 R/W Exposure Group Partial Enable Lower Bits Selection ('1' in any bit position: AND the corresponding Exposure Group Partial Enable input into the Lower Exposure Group Enable. If this mask is all '0' then the Lower Exposure Group Enable will be SET i.e. ENABLED) 15:8 R/W Exposure Group Partial Enable Upper Bits Selection ('1' in any bit position: AND the corresponding Exposure Group Partial Enable input into the Upper Exposure Group Enable. If this mask is all '0' then the Upper Exposure Group Enable will be SET i.e. ENABLED) Note: the overall Exposure Group Enable is the AND of the Upper and Lower Exposure Group Enables. Front End Busy and Global Disable Selection Register Address = 81 Bit Access Contents --- ------ -------- 7:0 R/W Front End Busy Enable ('1' in any bit position: OR the corresponding EG Front-End Busy Disable input into the Front-End Busy Disable. If this mask is all '0' then the Front-End Busy Disable will be CLEARED i.e. NOT DISABLED) 11:8 R/W Correlated Global Specific Trigger Disable Enable ('1' in any bit position: OR the corresponding Correlated Global Disable input into the Correlated Global Disable. If this mask is all '0' then the Correlated Global Disable will be CLEARED i.e. NOT DISABLED) 15:12 R/W Decorrelated Global Specific Trigger Disable Enable ('1' in any bit position: OR the corresponding Decorrelated Global Disable input into the Decorrelated Global Disable. If this mask is all '0' then the Decorrelated Global Disable will be CLEARED i.e. NOT DISABLED) Individual Disable, Prescaler, Auto Disable Register Address = 82 PAOF Ignore and EGPE Ignore, and COOR Disable Bit Access Contents --- ------ -------- 1:0 R/W Obey Individual Specific Trigger Disable 2 R/W Obey Prescaler 3 R/W Obey Auto Disable 4 R/W Obey PAOF Lower 5 R/W Obey PAOF Upper ('1' in any bit position: allow the corresponding input to contribute to the Spec Trig Fired) 6 R/W not allocated 7 R/W not allocated 8 R/W COOR Disable ('1': force the Specific Trigger to not fire note: this bit is SET on emerging from FPGA configuration) 15:9 R/W not allocated Auto Disable Control Register Address = 84 Bit Access Contents --- ------ -------- 0 R/W Auto Disable Reset (TCC writes 1-then-0 to reset the Auto Disable. The 1-to-0 transition clears the Auto Disable Signal and re-enables the logic which allows only one ST to fire before the Auto Disable Signal is automatically re-asserted, thus disabling the ST from firing [assuming that the ST is programmed to obey the Auto Disable] While Reset = 1, the ST Auto Disable Signal is forced to be asserted [disabling the ST from firing, again assuming that the ST is programmed to obey the Auto Disable], even if it was not previously asserted) 1 R Auto Disable Signal ('1': Auto Disable signal is currently asserted. Assuming the ST is programmed to obey Auto Disable, this ST will be disabled from firing while Auto Disable Signal = 1) 15:2 R/W not allocated Prescaler Control Registers Register Address = 128:134 The details of the registers that are used to control the Random Prescaler are presented in the section about the Prescaler which is above. /////////////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ Below here is the description of the old original Run II PreScaler that used either a divide by N counter or a 100 bit circular shift register. For now, 3-MAR-2003, this information will be saved here. Recall the desired characteristics of the Run II Prescaler: - First, ability to uniformly expose a Spec Trig to all bunches, so that the Prescale Disable did not need to be accounted for per-bunch - Second, ability to ensure minimum guaranteed spacing between L1 Accepts on a given Specific Trigger. - Third, ability to prescale by factors other than just 1/n, i.e. allow a 2/3 prescale. This is less important than the other two issues The Run II Prescaler is composed of 2 separate systems: (a) a 32-bit down counter, providing divide-by-N values in the range divide-by-2 to divide-by-(2^32) (corresponding to exposure for one tick per approximately 9.5 minutes). (b) a 100-bit circular shift register, which can be populated with any pattern of 1's and 0's, providing duty-cycle based prescaling in the range of 0% exposure to 100% exposure, in integer percentage steps (e.g. 1%, 2%, etc.) Examine the functionality of each of these modes: First the divide-by-N counter. Note that to divide by "n" the counter must be loaded with "n-1" as the terminal count is 0. Programming the divide-by-n counter with a value of "n-1" causes the ST to be exposed to 1 out of every "n" ticks (or, alternatively, to not be exposed to "n-1" ticks after each exposed tick). For example, if the counter is programmed with 1, and the ST is exposed to turn 1 bunch 1, it will be disabled for turn 1 bunch 2, exposed to turn 1 bunch 3, disabled for turn 1 bunch 4, etc, on through the end of turn 1, where the ST is exposed to bunch 159. The ST will be disabled for turn 2 bunch 1, and exposed to turn 2 tick 2, etc. That it, the ST will be exposed to all of the odd bunches in the odd turns, and the even bunches in the even turns. We see three important features from this example: - the ST is uniformly exposed to all bunches - it will not be exposed to any bunch twice until it has been exposed to all bunches exactly once - it is exposed at a uniform rate, and would fire at that same uniform rate if its And-Or Conditions were always met (and no other Disable stopped the event flow). In fact, if the divide-by-n counter is programmed to divide by any value which is relatively prime to 159 (recall that to divide by n the counter is programmed with n-1, however), the above 3 conditions will be met. Now do another example. Program the divide-by-n counter with 2 to get a prescale ratio of 3 (159 = 53*3). Now starting with exposure to turn 1 bunch 1, the ST is disabled for turn 1 bunches 2-3, exposed to turn 1 bunch 4, disabled for bunches 5-6, on through the end of turn 1 where the ST is exposed to bunch 157 and disabled for bunches 158-159. The ST will again be enabled for turn 2 bunch 1, and disabled for bunches 2-3. In fact, the ST will NEVER be enabled for bunches other than 1, 4, 7, ..., 157. That is: - the ST is NOT uniformly exposed to all bunches, but instead only is exposed to a subset of the bunches. - of the bunches it is exposed to, the exposure is uniform - of the bunches it is exposed to, it will not be exposed to any bunch twice until it has been exposed to all bunches exactly once (but again, note that it will be NEVER be exposed to some bunches). - it is exposed at a uniform rate, and would fire at that same uniform rate if its And-Or Conditions were always met (and no other Disable stopped the event flow) So, using the divide-by-n counter, we can achieve the primary prescaler objective of uniform exposure to all bunches (and also get some additional benefits of rate uniformity) as long as we restrict ourselves to prescale values which are relatively prime to 159. The question here is what to do if COOR specifies 1-of-3, for example. Respond with an error and don't do it, or respond with a warning and do it? Now examine the shift register. By programming a single 1 in the 100-bit shift register, the ST will be exposed to every 100th bunch. This is exactly equivalent to programming the divide-by-n counter to divide by 100 (i.e. program it with 99). It is impossible to distinguish between the two prescalers by external observation. Programming 2 1's maximally separated in the SR is exactly like dividing by 50--again you can't distinguish the two types of prescaler. Programming 2 1's in the shift register, but NOT maximally separated requires further thought. There is no exact equivalent to the counter- only prescaler situation. What happens instead is: - ST has the same average exposure rate (2 out of 100 aka 1 out of 50 bunches) - ST is exposed to all bunches uniformly over the long run - no lock step uniformity of "instantaneous" exposure rate can be guaranteed, rather it will lub-dub along with the SR pattern - one bunch may be exposed twice before all bunches are exposed exactly once...after an integral multiple of 100 turns all bunches are guaranteed to be exposed exactly the same number of times, though. Now, extend the situation to "m" 1's, arbitrarily spaced in the Shift Register. This is more complicated still, but the result ends up being the same as above. That is, using the SR alone can provide any prescale ratio that looks like n/100 while maintaining (over the long run) a uniform exposure to all bunches. That is, the SR doesn't buy us uniformity of bunch exposure (the important thing), it instead buys us prescale ratios other than 1-of-n. It does not provide any reasonable minimum spacing between L1 Accepts. By providing both types of prescaler, and using a mux to select between them, we can produce two very different, but both useful, 128 R/W Divide-by-N Prescaler Load Value (LSW) 129 R/W Divide-by-N Prescaler Load Value (MSW) 130 R/W Circular Shift Register Prescaler Load Pattern (LSW) 131 R/W Circular Shift Register Prescaler Load Pattern 132 R/W Circular Shift Register Prescaler Load Pattern 133 R/W Circular Shift Register Prescaler Load Pattern 134 R/W Circular Shift Register Prescaler Load Pattern 135 R/W Circular Shift Register Prescaler Load Pattern 136 R/W Circular Shift Register Prescaler Load Pattern (MSW) and Shift Register Control Divide-by-N Prescaler Load Value LSW/MSW Register Reg Adrs = 129:128 Bit Access Contents --- ------ -------- 15:0 R/W Divide-by-N Prescaler Load Value LSW/MSW (note: 1 = divide by 2, etc.) Circular Shift Register Prescaler Load Pattern Registers (all except MSW) Bit Access Contents --- ------ -------- 15:0 R/W Circular Shift Register Load Pattern bits 16*n + 15 : 16*n + 0 n = 5:0 Circular Shift Register Prescaler Load Pattern Register (MSW) Bit Access Contents --- ------ -------- 4:0 R/W Circular Shift Register Load Pattern bits 99:96 12:5 R/W (unallocated) 13 R/W Load value into Divide-by-N Counter ('1': Load the Divide-by-N Counter with the value in the Divide-by-N Load Value Registers '0': Allow the Divide-by-N Counter to count down) 14 R/W Load pattern into Circular Shift Register ('1': Load the Shift Register with the pattern in the Circular Shift Register Pattern Regs '0': Allow the Shift Register to shift the pattern) 15 R/W Prescaler Mode Select ('1': Use Circular Shift Register Prescaler '0': Use Divide-by-N Prescaler) /////////////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ Below is just some background information about the possible pseudo random number generators that one can effectively implement in the 4000 series CLB design. This information can be derived from the Xilinx note: www.xilinx.com/xapp/xapp052.pdf For now, 3-MAR-2003, this information will be saved here. Possible Shift Register Lengths Recall that we need 7.576 million values per second. 0.4545 billion values per minute. 27.27 billion values per hour. So if we want a 1 hour cycle time then we need the shift register to be a minimum of 35 bits long. The maximum length that we can reach is 68 bits while maintaining 2 CLB's per shift register. So look at the values 35:68. We would like lots of feedback terms and spread out feedback terms. We can consider using RAM's of 2 different lengths. Shift Register Feedback Length From Features -------- ------------ ----------------------------- 35 35,33 not interesting 36 36,25 not interesting 37 37,5,4,3,2,1 not possible 38 38,6,5,1 2:5,6,7:10,11,12:24,25,26:38,1 SRAM 4,13 39 39,35 not interesting 40 40,38,21,19 not possible 41 41,38 not interesting 42 42,41,20,19 1:9,10,11:19,20,21:30,31,32:41,42 SRAM 9,10 43 43,42,38,37 1:16,17,18:33,34:37,38,39:42,43 SRAM 16,4 44 44,43,18,17 1:8,9,10:17,18,19:30,31,32:43,44 SRAM 8,12 45 45,44,42,41 not possible 46 46,45,26,25 1:12,13,14:25,26,27:35,36,37:45,46 SRAM 12,9 47 47,42 not interesting 48 48,47,21,20 1:10,11:20,21,22:34,35:47,48 SRAM 10,13 49 49,40 not interesting 50 50,49,24,23 1:11,12,13:23,24,25:36,37,38:49,50 SRAM 11,12 51 51,50,36,35 1:10,11,12:21,22:35,36,37:50,51 SRAM 10,14 52 52,49 not interesting 53 53,52,38,37 1:11,12,13:23,24:37,38,39:52,53 SRAM 11,14 54 54,53,18,17 not possible 55 55,31 not interesting 56 56,55,35,34 not possible 57 57,50 not interesting 58 58,39 not interesting 59 59,58,38,37 not possible 60 60,59 not interesting 61 61,60,46,45 1:15,16,17:31,32:45,46,47:60,61 SRAM 15,14 62 62,61,6,5 not possible 63 63,62 not interesting 64 64,63,61,60 not possible 65 65,47 not interesting 66 66,65,57,56 67 67,66,58,57 68 68,59 not interesting 69 69,67,42,40 /////////////////////////////////////\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\