***************************** * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * * Trigger Decision Module * * * ***************************** Original: 31-MAY-1995 Latest: 24-NOV-1998 Introduction ------------ The Trigger Decision Module (TDM) is used in the Level 1 Trigger Framework. It has the following functions: 1) Produce a subset of the Specific Trigger Fired signals based on the corresponding Partial And-Or Fired signals and the various disable/veto signals 2) Provide for Data Block readout several pieces of state information for each Specific Trigger 3) Provide for Monitoring readout several scalers (and all of the state information from the Data Block readout) for each Specific Trigger. There are 8 TDM's in the L1 Trigger Framework. This comes about because each TRM can only service 16 Specific Triggers, while the L1 Trigger Framework uses 128 Specific Triggers. Each TRM has the following connections to the experiment: (1) Real-time inputs Main Signal Array Inputs: - 32 (16 pairs of) Partial Sp. Trg. And-Or Physics Fired signals - 16 (8 pairs of) Partial Sp. Trg. AO Exposure Group Enable signals - 8 Front-End Busy Exposure Group Disable Specific Trigger signals - 32 (16 sets of 2) Individual Sp. Trg. Disable signals - 4 Correlated Global Sp. Trg. Disable signals - 4 Decorrelated Global Sp. Trg. Disable signals - additional spare input signals (see P2/P3 description) P1 Timing signals: - Capture High-Speed Readout Data - Capture Monitor Readout Data - L1 Accept - BX Clock - Per-Turn Marker ? - Scaler Reset ? (2) Real-time output Main Signal Array Outputs: - 16 Specific Trigger Fired signals (to Framework Output Modules) - 32 spare outputs (2 per MSA FPGA) - 16 Diagnostic Bus outputs (all from MSA FPGA 16) (3) Programming information see TDM_FPGA_DESCRIPTION.TXT for details (4) Data Block readout information 19-MAR-1997: definition still in progress see TDM_FPGA_DESCRIPTION.TXT for details (5) Monitoring readout information see TDM_FPGA_DESCRIPTION.TXT for details Operation --------- The operation of the TDM FPGA is described in the file: MSUTRGROOT_II:[HARDWARE.TDM]TDM_FPGA_DESCRIPTION.TXT Refer to that file for details of the operation of the FPGA's on the TDM card. Implementation -------------- The TDM is implemented on THE card. All MSA FPGA's on this card are configured identically. Each FPGA performs the entire functionality (trigger decision, state recording, scalers, etc.) required for a single Specific Trigger. The mapping of Specific Triggers to FPGA's is below: Spec. Trig MSA FPGA MSA Outputs ---------- -------- ----------- 0 1 0, 32, 48 1 5 1, 33, 49 2 9 2, 34, 50 3 13 3, 35, 51 4 2 4, 36, 52 5 6 5, 37, 53 6 10 6, 38, 54 7 14 7, 39, 55 8 3 8, 40, 56 9 7 9, 41, 57 10 11 10, 42, 58 11 15 11, 43, 59 12 4 12, 44, 60 13 8 13, 45, 61 14 12 14, 46, 62 15 16 15, 47, 63, 31:16 The mapping of MSA Inputs to MSA FPGA's is too complex to summarize usefully in tabular form, refer to the P2/P3 connector pinout below. ------------------------- CONNECTOR PIN ASSIGNMENTS ------------------------- The AONM has 8 connectors: P1: 160-pin E-style DIN connector for VME P1 bus P2: 160-pin E-style DIN connector for Trigger Framework P2 input bus P3: 160-pin E-style DIN connector for Trigger Framework P3 input bus P4: 160-pin front-panel connector for card output P5: 34-pin front-panel connectors for "global" output ---------------------------------------------------------------------- P1: 160-pin E-style DIN connector for P1 VME and Timing ---------------------------------------------------------------------- See THE_CARD.TXT for a description of this connector, which is common to all species of THE Card. ---------------------------------------------------------------------- P2: 160-pin E-style DIN connector for Trigger Framework P2 input bus Correct post 3-AUG-1998 view of the TDM Card's P2 connector. ---------------------------------------------------------------------- (note: 0 <= n <= 7) Sepcific Pin # Signal Description Trigger Dir Identifier ----- ------------------ --------- --- ---------- A1 Partial And-Or Fired Lower 16*n + 0 COM INPUT MSA_In_000 B1 Partial And-Or Fired Lower 16*n + 0 DIR INPUT MSA_In_000 A2 Partial And-Or Fired Upper 16*n + 0 COM INPUT MSA_In_001 B2 Partial And-Or Fired Upper 16*n + 0 DIR INPUT MSA_In_001 A3 Specific Trigger Disable 0 16*n + 0 COM INPUT MSA_In_002 B3 Specific Trigger Disable 0 16*n + 0 DIR INPUT MSA_In_002 A4 Specific Trigger Disable 1 16*n + 0 COM INPUT MSA_In_003 B4 Specific Trigger Disable 1 16*n + 0 DIR INPUT MSA_In_003 A5 Partial And-Or Fired Lower 16*n + 2 COM INPUT MSA_In_004 B5 Partial And-Or Fired Lower 16*n + 2 DIR INPUT MSA_In_004 A6 Partial And-Or Fired Upper 16*n + 2 COM INPUT MSA_In_005 B6 Partial And-Or Fired Upper 16*n + 2 DIR INPUT MSA_In_005 A7 Specific Trigger Disable 0 16*n + 2 COM INPUT MSA_In_006 B7 Specific Trigger Disable 0 16*n + 2 DIR INPUT MSA_In_006 A8 Specific Trigger Disable 1 16*n + 2 COM INPUT MSA_In_007 B8 Specific Trigger Disable 1 16*n + 2 DIR INPUT MSA_In_007 A9 Individual Spare 16*n + 0 COM INPUT MSA_In_008 B9 Individual Spare 16*n + 0 DIR INPUT MSA_In_008 A10 Global Spare 0 COM INPUT MSA_In_009 B10 Global Spare 0 DIR INPUT MSA_In_009 A11 Exp. Group Part. Enb. Lower 0 COM INPUT MSA_In_010 B11 Exp. Group Part. Enb. Lower 0 DIR INPUT MSA_In_010 A12 Exp. Group Part. Enb. Lower 2 COM INPUT MSA_In_011 B12 Exp. Group Part. Enb. Lower 2 DIR INPUT MSA_In_011 A13 Individual Spare 16*n + 2 COM INPUT MSA_In_012 B13 Individual Spare 16*n + 2 DIR INPUT MSA_In_012 A14 Unrouted After Terminators 0 COM INPUT MSA_In_013 B14 Unrouted After Terminators 0 DIR INPUT MSA_In_013 A15 Exp. Group Part. Enb. Lower 4 COM INPUT MSA_In_014 B15 Exp. Group Part. Enb. Lower 4 DIR INPUT MSA_In_014 A16 Exp. Group Part. Enb. Lower 6 COM INPUT MSA_In_015 B16 Exp. Group Part. Enb. Lower 6 DIR INPUT MSA_In_015 A17 Partial And-Or Fired Lower 16*n + 4 COM INPUT MSA_In_016 B17 Partial And-Or Fired Lower 16*n + 4 DIR INPUT MSA_In_016 A18 Partial And-Or Fired Upper 16*n + 4 COM INPUT MSA_In_017 B18 Partial And-Or Fired Upper 16*n + 4 DIR INPUT MSA_In_017 A19 Specific Trigger Disable 0 16*n + 4 COM INPUT MSA_In_018 B19 Specific Trigger Disable 0 16*n + 4 DIR INPUT MSA_In_018 A20 Specific Trigger Disable 1 16*n + 4 COM INPUT MSA_In_019 B20 Specific Trigger Disable 1 16*n + 4 DIR INPUT MSA_In_019 A21 Partial And-Or Fired Lower 16*n + 6 COM INPUT MSA_In_020 B21 Partial And-Or Fired Lower 16*n + 6 DIR INPUT MSA_In_020 A22 Partial And-Or Fired Upper 16*n + 6 COM INPUT MSA_In_021 B22 Partial And-Or Fired Upper 16*n + 6 DIR INPUT MSA_In_021 A23 Specific Trigger Disable 0 16*n + 6 COM INPUT MSA_In_022 B23 Specific Trigger Disable 0 16*n + 6 DIR INPUT MSA_In_022 A24 Specific Trigger Disable 1 16*n + 6 COM INPUT MSA_In_023 B24 Specific Trigger Disable 1 16*n + 6 DIR INPUT MSA_In_023 A25 Individual Spare 16*n + 4 COM INPUT MSA_In_024 B25 Individual Spare 16*n + 4 DIR INPUT MSA_In_024 A26 Global Spare 1 COM INPUT MSA_In_025 B26 Global Spare 1 DIR INPUT MSA_In_025 A27 Exp. Group Part. Enb. Upper 0 COM INPUT MSA_In_026 B27 Exp. Group Part. Enb. Upper 0 DIR INPUT MSA_In_026 A28 Exp. Group Part. Enb. Upper 2 COM INPUT MSA_In_027 B28 Exp. Group Part. Enb. Upper 2 DIR INPUT MSA_In_027 A29 Individual Spare 16*n + 6 COM INPUT MSA_In_028 B29 Individual Spare 16*n + 6 DIR INPUT MSA_In_028 A30 Unrouted After Terminators 1 COM INPUT MSA_In_029 B30 Unrouted After Terminators 1 DIR INPUT MSA_In_029 A31 Exp. Group Part. Enb. Upper 4 COM INPUT MSA_In_030 B31 Exp. Group Part. Enb. Upper 4 DIR INPUT MSA_In_030 A32 Exp. Group Part. Enb. Upper 6 COM INPUT MSA_In_031 B32 Exp. Group Part. Enb. Upper 6 DIR INPUT MSA_In_031 C1 GROUND C2 +3.3V UPPER C3 GROUND C4 +3.3V UPPER C5 -2.0V UPPER C6 GROUND C7 +3.3V UPPER C8 GROUND C9 +5.0V UPPER C10 GROUND C11 +3.3V UPPER C12 GROUND C13 +3.3V UPPER C14 GROUND C15 -2.0V UPPER C16 GROUND C17 +3.3V UPPER C18 GROUND C19 +5.0V UPPER C20 +3.3V UPPER C21 GROUND C22 +3.3V UPPER C23 GROUND C24 -2.0V UPPER C25 GROUND C26 +3.3V UPPER C27 GROUND C28 +5.0V UPPER C29 +3.3V UPPER C30 GROUND C31 +3.3V UPPER C32 GROUND D1 Partial And-Or Fired Lower 16*n + 1 COM INPUT MSA_In_032 E1 Partial And-Or Fired Lower 16*n + 1 DIR INPUT MSA_In_032 D2 Partial And-Or Fired Upper 16*n + 1 COM INPUT MSA_In_033 E2 Partial And-Or Fired Upper 16*n + 1 DIR INPUT MSA_In_033 D3 Specific Trigger Disable 0 16*n + 1 COM INPUT MSA_In_034 E3 Specific Trigger Disable 0 16*n + 1 DIR INPUT MSA_In_034 D4 Specific Trigger Disable 1 16*n + 1 COM INPUT MSA_In_035 E4 Specific Trigger Disable 1 16*n + 1 DIR INPUT MSA_In_035 D5 Partial And-Or Fired Lower 16*n + 3 COM INPUT MSA_In_036 E5 Partial And-Or Fired Lower 16*n + 3 DIR INPUT MSA_In_036 D6 Partial And-Or Fired Upper 16*n + 3 COM INPUT MSA_In_037 E6 Partial And-Or Fired Upper 16*n + 3 DIR INPUT MSA_In_037 D7 Specific Trigger Disable 0 16*n + 3 COM INPUT MSA_In_038 E7 Specific Trigger Disable 0 16*n + 3 DIR INPUT MSA_In_038 D8 Specific Trigger Disable 1 16*n + 3 COM INPUT MSA_In_039 E8 Specific Trigger Disable 1 16*n + 3 DIR INPUT MSA_In_039 D9 Individual Spare 16*n + 1 COM INPUT MSA_In_040 E9 Individual Spare 16*n + 1 DIR INPUT MSA_In_040 D10 Global Spare 4 COM INPUT MSA_In_041 E10 Global Spare 4 DIR INPUT MSA_In_041 D11 Exp. Group Part. Enb. Lower 1 COM INPUT MSA_In_042 E11 Exp. Group Part. Enb. Lower 1 DIR INPUT MSA_In_042 D12 Exp. Group Part. Enb. Lower 3 COM INPUT MSA_In_043 E12 Exp. Group Part. Enb. Lower 3 DIR INPUT MSA_In_043 D13 Individual Spare 16*n + 3 COM INPUT MSA_In_044 E13 Individual Spare 16*n + 3 DIR INPUT MSA_In_044 D14 Unrouted After Terminators 2 COM INPUT MSA_In_045 E14 Unrouted After Terminators 2 DIR INPUT MSA_In_045 D15 Exp. Group Part. Enb. Lower 5 COM INPUT MSA_In_046 E15 Exp. Group Part. Enb. Lower 5 DIR INPUT MSA_In_046 D16 Exp. Group Part. Enb. Lower 7 COM INPUT MSA_In_047 E16 Exp. Group Part. Enb. Lower 7 DIR INPUT MSA_In_047 D17 Partial And-Or Fired Lower 16*n + 5 COM INPUT MSA_In_048 E17 Partial And-Or Fired Lower 16*n + 5 DIR INPUT MSA_In_048 D18 Partial And-Or Fired Upper 16*n + 5 COM INPUT MSA_In_049 E18 Partial And-Or Fired Upper 16*n + 5 DIR INPUT MSA_In_049 D19 Specific Trigger Disable 0 16*n + 5 COM INPUT MSA_In_050 E19 Specific Trigger Disable 0 16*n + 5 DIR INPUT MSA_In_050 D20 Specific Trigger Disable 1 16*n + 5 COM INPUT MSA_In_051 E20 Specific Trigger Disable 1 16*n + 5 DIR INPUT MSA_In_051 D21 Partial And-Or Fired Lower 16*n + 7 COM INPUT MSA_In_052 E21 Partial And-Or Fired Lower 16*n + 7 DIR INPUT MSA_In_052 D22 Partial And-Or Fired Upper 16*n + 7 COM INPUT MSA_In_053 E22 Partial And-Or Fired Upper 16*n + 7 DIR INPUT MSA_In_053 D23 Specific Trigger Disable 0 16*n + 7 COM INPUT MSA_In_054 E23 Specific Trigger Disable 0 16*n + 7 DIR INPUT MSA_In_054 D24 Specific Trigger Disable 1 16*n + 7 COM INPUT MSA_In_055 E24 Specific Trigger Disable 1 16*n + 7 DIR INPUT MSA_In_055 D25 Individual Spare 16*n + 5 COM INPUT MSA_In_056 E25 Individual Spare 16*n + 5 DIR INPUT MSA_In_056 D26 Global Spare 5 COM INPUT MSA_In_057 E26 Global Spare 5 DIR INPUT MSA_In_057 D27 Exp. Group Part. Enb. Upper 1 COM INPUT MSA_In_058 E27 Exp. Group Part. Enb. Upper 1 DIR INPUT MSA_In_058 D28 Exp. Group Part. Enb. Upper 3 COM INPUT MSA_In_059 E28 Exp. Group Part. Enb. Upper 3 DIR INPUT MSA_In_059 D29 Individual Spare 16*n + 7 COM INPUT MSA_In_060 E29 Individual Spare 16*n + 7 DIR INPUT MSA_In_060 D30 Unrouted After Terminators 3 COM INPUT MSA_In_061 E30 Unrouted After Terminators 3 DIR INPUT MSA_In_061 D31 Exp. Group Part. Enb. Upper 5 COM INPUT MSA_In_062 E31 Exp. Group Part. Enb. Upper 5 DIR INPUT MSA_In_062 D32 Exp. Group Part. Enb. Upper 7 COM INPUT MSA_In_063 E32 Exp. Group Part. Enb. Upper 7 DIR INPUT MSA_In_063 ---------------------------------------------------------------------- P3: 160-pin E-style DIN connector for Trigger Framework P3 input bus Correct post 3-AUG-1998 view of the TDM Card's P3 connector. ---------------------------------------------------------------------- (note: 0 <= n <= 7) Specific Pin # Signal Description Trigger Dir Identifier ----- ------------------ --------- --- ---------- A1 Partial And-Or Fired Lower 16*n + 8 COM INPUT MSA_In_064 B1 Partial And-Or Fired Lower 16*n + 8 DIR INPUT MSA_In_064 A2 Partial And-Or Fired Upper 16*n + 8 COM INPUT MSA_In_065 B2 Partial And-Or Fired Upper 16*n + 8 DIR INPUT MSA_In_065 A3 Specific Trigger Disable 0 16*n + 8 COM INPUT MSA_In_066 B3 Specific Trigger Disable 0 16*n + 8 DIR INPUT MSA_In_066 A4 Specific Trigger Disable 1 16*n + 8 COM INPUT MSA_In_067 B4 Specific Trigger Disable 1 16*n + 8 DIR INPUT MSA_In_067 A5 Partial And-Or Fired Lower 16*n + 10 COM INPUT MSA_In_068 B5 Partial And-Or Fired Lower 16*n + 10 DIR INPUT MSA_In_068 A6 Partial And-Or Fired Upper 16*n + 10 COM INPUT MSA_In_069 B6 Partial And-Or Fired Upper 16*n + 10 DIR INPUT MSA_In_069 A7 Specific Trigger Disable 0 16*n + 10 COM INPUT MSA_In_070 B7 Specific Trigger Disable 0 16*n + 10 DIR INPUT MSA_In_070 A8 Specific Trigger Disable 1 16*n + 10 COM INPUT MSA_In_071 B8 Specific Trigger Disable 1 16*n + 10 DIR INPUT MSA_In_071 A9 Individual Spare 16*n + 8 COM INPUT MSA_In_072 B9 Individual Spare 16*n + 8 DIR INPUT MSA_In_072 A10 Global Spare 2 COM INPUT MSA_In_073 B10 Global Spare 2 DIR INPUT MSA_In_073 A11 Exp. Group Front End Busy Dis. 0 COM INPUT MSA_In_074 B11 Exp. Group Front End Busy Dis. 0 DIR INPUT MSA_In_074 A12 Exp. Group Front End Busy Dis. 2 COM INPUT MSA_In_075 B12 Exp. Group Front End Busy Dis. 2 DIR INPUT MSA_In_075 A13 Individual Spare 16*n + 10 COM INPUT MSA_In_076 B13 Individual Spare 16*n + 10 DIR INPUT MSA_In_076 A14 Unrouted After Terminators 4 COM INPUT MSA_In_077 B14 Unrouted After Terminators 4 DIR INPUT MSA_In_077 A15 Exp. Group Front End Busy Dis. 4 COM INPUT MSA_In_078 B15 Exp. Group Front End Busy Dis. 4 DIR INPUT MSA_In_078 A16 Exp. Group Front End Busy Dis. 6 COM INPUT MSA_In_079 B16 Exp. Group Front End Busy Dis. 6 DIR INPUT MSA_In_079 A17 Partial And-Or Fired Lower 16*n + 12 COM INPUT MSA_In_080 B17 Partial And-Or Fired Lower 16*n + 12 DIR INPUT MSA_In_080 A18 Partial And-Or Fired Upper 16*n + 12 COM INPUT MSA_In_081 B18 Partial And-Or Fired Upper 16*n + 12 DIR INPUT MSA_In_081 A19 Specific Trigger Disable 0 16*n + 12 COM INPUT MSA_In_082 B19 Specific Trigger Disable 0 16*n + 12 DIR INPUT MSA_In_082 A20 Specific Trigger Disable 1 16*n + 12 COM INPUT MSA_In_083 B20 Specific Trigger Disable 1 16*n + 12 DIR INPUT MSA_In_083 A21 Partial And-Or Fired Lower 16*n + 14 COM INPUT MSA_In_084 B21 Partial And-Or Fired Lower 16*n + 14 DIR INPUT MSA_In_084 A22 Partial And-Or Fired Upper 16*n + 14 COM INPUT MSA_In_085 B22 Partial And-Or Fired Upper 16*n + 14 DIR INPUT MSA_In_085 A23 Specific Trigger Disable 0 16*n + 14 COM INPUT MSA_In_086 B23 Specific Trigger Disable 0 16*n + 14 DIR INPUT MSA_In_086 A24 Specific Trigger Disable 1 16*n + 14 COM INPUT MSA_In_087 B24 Specific Trigger Disable 1 16*n + 14 DIR INPUT MSA_In_087 A25 Individual Spare 16*n + 12 COM INPUT MSA_In_088 B25 Individual Spare 16*n + 12 DIR INPUT MSA_In_088 A26 Global Spare 3 COM INPUT MSA_In_089 B26 Global Spare 3 DIR INPUT MSA_In_089 A27 De-Correlated Global Disable 0 COM INPUT MSA_In_090 B27 De-Correlated Global Disable 0 DIR INPUT MSA_In_090 A28 De-Correlated Global Disable 2 COM INPUT MSA_In_091 B28 De-Correlated Global Disable 2 DIR INPUT MSA_In_091 A29 Individual Spare 16*n + 14 COM INPUT MSA_In_092 B29 Individual Spare 16*n + 14 DIR INPUT MSA_In_092 A30 Unrouted After Terminators 5 COM INPUT MSA_In_093 B30 Unrouted After Terminators 5 DIR INPUT MSA_In_093 A31 Correlated Global Disable 0 COM INPUT MSA_In_094 B31 Correlated Global Disable 0 DIR INPUT MSA_In_094 A32 Correlated Global Disable 2 COM INPUT MSA_In_095 B32 Correlated Global Disable 2 DIR INPUT MSA_In_095 C1 GROUND C2 +3.3V LOWER C3 GROUND C4 +3.3V LOWER C5 -4.5V LOWER C6 GROUND C7 +3.3V LOWER C8 GROUND C9 +5.0V LOWER C10 GROUND C11 +3.3V LOWER C12 GROUND C13 +3.3V LOWER C14 GROUND C15 -4.5V LOWER C16 GROUND C17 +3.3V LOWER C18 GROUND C19 +5.0V LOWER C20 +3.3V LOWER C21 GROUND C22 +3.3V LOWER C23 GROUND C24 -4.5V LOWER C25 GROUND C26 +3.3V LOWER C27 GROUND C28 +5.0V LOWER C29 +3.3V LOWER C30 GROUND C31 +3.3V LOWER C32 GROUND D1 Partial And-Or Fired Lower 16*n + 9 COM INPUT MSA_In_096 E1 Partial And-Or Fired Lower 16*n + 9 DIR INPUT MSA_In_096 D2 Partial And-Or Fired Upper 16*n + 9 COM INPUT MSA_In_097 E2 Partial And-Or Fired Upper 16*n + 9 DIR INPUT MSA_In_097 D3 Specific Trigger Disable 0 16*n + 9 COM INPUT MSA_In_098 E3 Specific Trigger Disable 0 16*n + 9 DIR INPUT MSA_In_098 D4 Specific Trigger Disable 1 16*n + 9 COM INPUT MSA_In_099 E4 Specific Trigger Disable 1 16*n + 9 DIR INPUT MSA_In_099 D5 Partial And-Or Fired Lower 16*n + 11 COM INPUT MSA_In_100 E5 Partial And-Or Fired Lower 16*n + 11 DIR INPUT MSA_In_100 D6 Partial And-Or Fired Upper 16*n + 11 COM INPUT MSA_In_101 E6 Partial And-Or Fired Upper 16*n + 11 DIR INPUT MSA_In_101 D7 Specific Trigger Disable 0 16*n + 11 COM INPUT MSA_In_102 E7 Specific Trigger Disable 0 16*n + 11 DIR INPUT MSA_In_102 D8 Specific Trigger Disable 1 16*n + 11 COM INPUT MSA_In_103 E8 Specific Trigger Disable 1 16*n + 11 DIR INPUT MSA_In_103 D9 Individual Spare 16*n + 9 COM INPUT MSA_In_104 E9 Individual Spare 16*n + 9 DIR INPUT MSA_In_104 D10 Global Spare 6 COM INPUT MSA_In_105 E10 Global Spare 6 DIR INPUT MSA_In_105 D11 Exp. Group Front End Busy Dis. 1 COM INPUT MSA_In_106 E11 Exp. Group Front End Busy Dis. 1 DIR INPUT MSA_In_106 D12 Exp. Group Front End Busy Dis. 3 COM INPUT MSA_In_107 E12 Exp. Group Front End Busy Dis. 3 DIR INPUT MSA_In_107 D13 Individual Spare 16*n + 11 COM INPUT MSA_In_108 E13 Individual Spare 16*n + 11 DIR INPUT MSA_In_108 D14 Unrouted After Terminators 6 COM INPUT MSA_In_109 E14 Unrouted After Terminators 6 DIR INPUT MSA_In_109 D15 Exp. Group Front End Busy Dis. 5 COM INPUT MSA_In_110 E15 Exp. Group Front End Busy Dis. 5 DIR INPUT MSA_In_110 D16 Exp. Group Front End Busy Dis. 7 COM INPUT MSA_In_111 E16 Exp. Group Front End Busy Dis. 7 DIR INPUT MSA_In_111 D17 Partial And-Or Fired Lower 16*n + 13 COM INPUT MSA_In_112 E17 Partial And-Or Fired Lower 16*n + 13 DIR INPUT MSA_In_112 D18 Partial And-Or Fired Upper 16*n + 13 COM INPUT MSA_In_113 E18 Partial And-Or Fired Upper 16*n + 13 DIR INPUT MSA_In_113 D19 Specific Trigger Disable 0 16*n + 13 COM INPUT MSA_In_114 E19 Specific Trigger Disable 0 16*n + 13 DIR INPUT MSA_In_114 D20 Specific Trigger Disable 1 16*n + 13 COM INPUT MSA_In_115 E20 Specific Trigger Disable 1 16*n + 13 DIR INPUT MSA_In_115 D21 Partial And-Or Fired Lower 16*n + 15 COM INPUT MSA_In_116 E21 Partial And-Or Fired Lower 16*n + 15 DIR INPUT MSA_In_116 D22 Partial And-Or Fired Upper 16*n + 15 COM INPUT MSA_In_117 E22 Partial And-Or Fired Upper 16*n + 15 DIR INPUT MSA_In_117 D23 Specific Trigger Disable 0 16*n + 15 COM INPUT MSA_In_118 E23 Specific Trigger Disable 0 16*n + 15 DIR INPUT MSA_In_118 D24 Specific Trigger Disable 0 16*n + 15 COM INPUT MSA_In_119 E24 Specific Trigger Disable 0 16*n + 15 DIR INPUT MSA_In_119 D25 Individual Spare 16*n + 13 COM INPUT MSA_In_120 E25 Individual Spare 16*n + 13 DIR INPUT MSA_In_120 D26 Global Spare 7 COM INPUT MSA_In_121 E26 Global Spare 7 DIR INPUT MSA_In_121 D27 De-Correlated Global Disable 1 COM INPUT MSA_In_122 E27 De-Correlated Global Disable 1 DIR INPUT MSA_In_122 D28 De-Correlated Global Disable 3 COM INPUT MSA_In_123 E28 De-Correlated Global Disable 3 DIR INPUT MSA_In_123 D29 Individual Spare 16*n + 15 COM INPUT MSA_In_124 E29 Individual Spare 16*n + 15 DIR INPUT MSA_In_124 D30 Unrouted After Terminators 7 COM INPUT MSA_In_125 E30 Unrouted After Terminators 7 DIR INPUT MSA_In_125 D31 Correlated Global Disable 1 COM INPUT MSA_In_126 E31 Correlated Global Disable 1 DIR INPUT MSA_In_126 D32 Correlated Global Disable 3 COM INPUT MSA_In_127 E32 Correlated Global Disable 3 DIR INPUT MSA_In_127 ----------------------------------------------------------------------- P4: 160-pin E-style DIN connector for Trigger Framework P4 output bus ----------------------------------------------------------------------- Pin # Signal Description Dir Identifier ----- ------------------ --- ---------- A1 Individual Spare 1 16*n + 15 DIR OUTPUT MSA_Out_63 B1 Individual Spare 1 16*n + 15 COM OUTPUT MSA_Out_63 A2 Individual Spare 1 16*n + 14 DIR OUTPUT MSA_Out_62 B2 Individual Spare 1 16*n + 14 COM OUTPUT MSA_Out_62 A3 Individual Spare 1 16*n + 13 DIR OUTPUT MSA_Out_61 B3 Individual Spare 1 16*n + 13 COM OUTPUT MSA_Out_61 A4 Individual Spare 1 16*n + 12 DIR OUTPUT MSA_Out_60 B4 Individual Spare 1 16*n + 12 COM OUTPUT MSA_Out_60 A5 Individual Spare 1 16*n + 11 DIR OUTPUT MSA_Out_59 B5 Individual Spare 1 16*n + 11 COM OUTPUT MSA_Out_59 A6 Individual Spare 1 16*n + 10 DIR OUTPUT MSA_Out_58 B6 Individual Spare 1 16*n + 10 COM OUTPUT MSA_Out_58 A7 Individual Spare 1 16*n + 9 DIR OUTPUT MSA_Out_57 B7 Individual Spare 1 16*n + 9 COM OUTPUT MSA_Out_57 A8 Individual Spare 1 16*n + 8 DIR OUTPUT MSA_Out_56 B8 Individual Spare 1 16*n + 8 COM OUTPUT MSA_Out_56 A9 Individual Spare 1 16*n + 7 DIR OUTPUT MSA_Out_55 B9 Individual Spare 1 16*n + 7 COM OUTPUT MSA_Out_55 A10 Individual Spare 1 16*n + 6 DIR OUTPUT MSA_Out_54 B10 Individual Spare 1 16*n + 6 COM OUTPUT MSA_Out_54 A11 Individual Spare 1 16*n + 5 DIR OUTPUT MSA_Out_53 B11 Individual Spare 1 16*n + 5 COM OUTPUT MSA_Out_53 A12 Individual Spare 1 16*n + 4 DIR OUTPUT MSA_Out_52 B12 Individual Spare 1 16*n + 4 COM OUTPUT MSA_Out_52 A13 Individual Spare 1 16*n + 3 DIR OUTPUT MSA_Out_51 B13 Individual Spare 1 16*n + 3 COM OUTPUT MSA_Out_51 A14 Individual Spare 1 16*n + 2 DIR OUTPUT MSA_Out_50 B14 Individual Spare 1 16*n + 2 COM OUTPUT MSA_Out_50 A15 Individual Spare 1 16*n + 1 DIR OUTPUT MSA_Out_49 B15 Individual Spare 1 16*n + 1 COM OUTPUT MSA_Out_49 A16 Individual Spare 1 16*n + 0 DIR OUTPUT MSA_Out_48 B16 Individual Spare 1 16*n + 0 COM OUTPUT MSA_Out_48 A17 Individual Spare 0 16*n + 15 DIR OUTPUT MSA_Out_47 B17 Individual Spare 0 16*n + 15 COM OUTPUT MSA_Out_47 A18 Individual Spare 0 16*n + 14 DIR OUTPUT MSA_Out_46 B18 Individual Spare 0 16*n + 14 COM OUTPUT MSA_Out_46 A19 Individual Spare 0 16*n + 13 DIR OUTPUT MSA_Out_45 B19 Individual Spare 0 16*n + 13 COM OUTPUT MSA_Out_45 A20 Individual Spare 0 16*n + 12 DIR OUTPUT MSA_Out_44 B20 Individual Spare 0 16*n + 12 COM OUTPUT MSA_Out_44 A21 Individual Spare 0 16*n + 11 DIR OUTPUT MSA_Out_43 B21 Individual Spare 0 16*n + 11 COM OUTPUT MSA_Out_43 A22 Individual Spare 0 16*n + 10 DIR OUTPUT MSA_Out_42 B22 Individual Spare 0 16*n + 10 COM OUTPUT MSA_Out_42 A23 Individual Spare 0 16*n + 9 DIR OUTPUT MSA_Out_41 B23 Individual Spare 0 16*n + 9 COM OUTPUT MSA_Out_41 A24 Individual Spare 0 16*n + 8 DIR OUTPUT MSA_Out_40 B24 Individual Spare 0 16*n + 8 COM OUTPUT MSA_Out_40 A25 Individual Spare 0 16*n + 7 DIR OUTPUT MSA_Out_39 B25 Individual Spare 0 16*n + 7 COM OUTPUT MSA_Out_39 A26 Individual Spare 0 16*n + 6 DIR OUTPUT MSA_Out_38 B26 Individual Spare 0 16*n + 6 COM OUTPUT MSA_Out_38 A27 Individual Spare 0 16*n + 5 DIR OUTPUT MSA_Out_37 B27 Individual Spare 0 16*n + 5 COM OUTPUT MSA_Out_37 A28 Individual Spare 0 16*n + 4 DIR OUTPUT MSA_Out_36 B28 Individual Spare 0 16*n + 4 COM OUTPUT MSA_Out_36 A29 Individual Spare 0 16*n + 3 DIR OUTPUT MSA_Out_35 B29 Individual Spare 0 16*n + 3 COM OUTPUT MSA_Out_35 A30 Individual Spare 0 16*n + 2 DIR OUTPUT MSA_Out_34 B30 Individual Spare 0 16*n + 2 COM OUTPUT MSA_Out_34 A31 Individual Spare 0 16*n + 1 DIR OUTPUT MSA_Out_33 B31 Individual Spare 0 16*n + 1 COM OUTPUT MSA_Out_33 A32 Individual Spare 0 16*n + 0 DIR OUTPUT MSA_Out_32 B32 Individual Spare 0 16*n + 0 COM OUTPUT MSA_Out_32 C1 GROUND C2 +5.0 V C3 GROUND C4 GROUND C5 GROUND C6 +3.3 V C7 GROUND C8 GROUND C9 GROUND C10 -2.0 V C11 GROUND C12 GROUND C13 GROUND C14 -4.5 V C15 GROUND C16 GROUND C17 GROUND C18 GROUND C19 +5.0 V C20 GROUND C21 GROUND C22 GROUND C23 +3.3 V C24 GROUND C25 GROUND C26 GROUND C27 -2.0 V C28 GROUND C29 GROUND C30 GROUND C31 -4.5 V C32 GROUND D1 FPGA 16 Diagnostic Bus Term 15 DIR OUTPUT MSA_Out_31 E1 FPGA 16 Diagnostic Bus Term 15 COM OUTPUT MSA_Out_31 D2 FPGA 16 Diagnostic Bus Term 14 DIR OUTPUT MSA_Out_30 E2 FPGA 16 Diagnostic Bus Term 14 COM OUTPUT MSA_Out_30 D3 FPGA 16 Diagnostic Bus Term 13 DIR OUTPUT MSA_Out_29 E3 FPGA 16 Diagnostic Bus Term 13 COM OUTPUT MSA_Out_29 D4 FPGA 16 Diagnostic Bus Term 12 DIR OUTPUT MSA_Out_28 E4 FPGA 16 Diagnostic Bus Term 12 COM OUTPUT MSA_Out_28 D5 FPGA 16 Diagnostic Bus Term 11 DIR OUTPUT MSA_Out_27 E5 FPGA 16 Diagnostic Bus Term 11 COM OUTPUT MSA_Out_27 D6 FPGA 16 Diagnostic Bus Term 10 DIR OUTPUT MSA_Out_26 E6 FPGA 16 Diagnostic Bus Term 10 COM OUTPUT MSA_Out_26 D7 FPGA 16 Diagnostic Bus Term 9 DIR OUTPUT MSA_Out_25 E7 FPGA 16 Diagnostic Bus Term 9 COM OUTPUT MSA_Out_25 D8 FPGA 16 Diagnostic Bus Term 8 DIR OUTPUT MSA_Out_24 E8 FPGA 16 Diagnostic Bus Term 8 COM OUTPUT MSA_Out_24 D9 FPGA 16 Diagnostic Bus Term 7 DIR OUTPUT MSA_Out_23 E9 FPGA 16 Diagnostic Bus Term 7 COM OUTPUT MSA_Out_23 D10 FPGA 16 Diagnostic Bus Term 6 DIR OUTPUT MSA_Out_22 E10 FPGA 16 Diagnostic Bus Term 6 COM OUTPUT MSA_Out_22 D11 FPGA 16 Diagnostic Bus Term 5 DIR OUTPUT MSA_Out_21 E11 FPGA 16 Diagnostic Bus Term 5 COM OUTPUT MSA_Out_21 D12 FPGA 16 Diagnostic Bus Term 4 DIR OUTPUT MSA_Out_20 E12 FPGA 16 Diagnostic Bus Term 4 COM OUTPUT MSA_Out_20 D13 FPGA 16 Diagnostic Bus Term 3 DIR OUTPUT MSA_Out_19 E13 FPGA 16 Diagnostic Bus Term 3 COM OUTPUT MSA_Out_19 D14 FPGA 16 Diagnostic Bus Term 2 DIR OUTPUT MSA_Out_18 E14 FPGA 16 Diagnostic Bus Term 2 COM OUTPUT MSA_Out_18 D15 FPGA 16 Diagnostic Bus Term 1 DIR OUTPUT MSA_Out_17 E15 FPGA 16 Diagnostic Bus Term 1 COM OUTPUT MSA_Out_17 D16 FPGA 16 Diagnostic Bus Term 0 DIR OUTPUT MSA_Out_16 E16 FPGA 16 Diagnostic Bus Term 0 COM OUTPUT MSA_Out_16 D17 Specific Trigger Fired Term 16*n + 15 DIR OUTPUT MSA_Out_15 E17 Specific Trigger Fired Term 16*n + 15 COM OUTPUT MSA_Out_15 D18 Specific Trigger Fired Term 16*n + 14 DIR OUTPUT MSA_Out_14 E18 Specific Trigger Fired Term 16*n + 14 COM OUTPUT MSA_Out_14 D19 Specific Trigger Fired Term 16*n + 13 DIR OUTPUT MSA_Out_13 E19 Specific Trigger Fired Term 16*n + 13 COM OUTPUT MSA_Out_13 D20 Specific Trigger Fired Term 16*n + 12 DIR OUTPUT MSA_Out_12 E20 Specific Trigger Fired Term 16*n + 12 COM OUTPUT MSA_Out_12 D21 Specific Trigger Fired Term 16*n + 11 DIR OUTPUT MSA_Out_11 E21 Specific Trigger Fired Term 16*n + 11 COM OUTPUT MSA_Out_11 D22 Specific Trigger Fired Term 16*n + 10 DIR OUTPUT MSA_Out_10 E22 Specific Trigger Fired Term 16*n + 10 COM OUTPUT MSA_Out_10 D23 Specific Trigger Fired Term 16*n + 9 DIR OUTPUT MSA_Out_09 E23 Specific Trigger Fired Term 16*n + 9 COM OUTPUT MSA_Out_09 D24 Specific Trigger Fired Term 16*n + 8 DIR OUTPUT MSA_Out_08 E24 Specific Trigger Fired Term 16*n + 8 COM OUTPUT MSA_Out_08 D25 Specific Trigger Fired Term 16*n + 7 DIR OUTPUT MSA_Out_07 E25 Specific Trigger Fired Term 16*n + 7 COM OUTPUT MSA_Out_07 D26 Specific Trigger Fired Term 16*n + 6 DIR OUTPUT MSA_Out_06 E26 Specific Trigger Fired Term 16*n + 6 COM OUTPUT MSA_Out_06 D27 Specific Trigger Fired Term 16*n + 5 DIR OUTPUT MSA_Out_05 E27 Specific Trigger Fired Term 16*n + 5 COM OUTPUT MSA_Out_05 D28 Specific Trigger Fired Term 16*n + 4 DIR OUTPUT MSA_Out_04 E28 Specific Trigger Fired Term 16*n + 4 COM OUTPUT MSA_Out_04 D29 Specific Trigger Fired Term 16*n + 3 DIR OUTPUT MSA_Out_03 E29 Specific Trigger Fired Term 16*n + 3 COM OUTPUT MSA_Out_03 D30 Specific Trigger Fired Term 16*n + 2 DIR OUTPUT MSA_Out_02 E30 Specific Trigger Fired Term 16*n + 2 COM OUTPUT MSA_Out_02 D31 Specific Trigger Fired Term 16*n + 1 DIR OUTPUT MSA_Out_01 E31 Specific Trigger Fired Term 16*n + 1 COM OUTPUT MSA_Out_01 D32 Specific Trigger Fired Term 16*n + 0 DIR OUTPUT MSA_Out_00 E32 Specific Trigger Fired Term 16*n + 0 COM OUTPUT MSA_Out_00 ---------------------------------------------------------------------- P5: 34-pin front-panel connector for "global" signals ---------------------------------------------------------------------- 16 of the 17 signals from the BSF FPGA terminating in vias on THE-CARD have each been routed to individual FPGAs for ????????? Pin # Signal Description Dir Identifier ----- ------------------ --- ---------- 1 P5 Global I/O Signal 0 DIR BIDIR P5_IO_000 2 P5 Global I/O Signal 0 COM BIDIR P5_IO_000 3 P5 Global I/O Signal 1 DIR BIDIR P5_IO_010 4 P5 Global I/O Signal 1 COM BIDIR P5_IO_011 5 P5 Global I/O Signal 2 DIR BIDIR P5_IO_021 6 P5 Global I/O Signal 2 COM BIDIR P5_IO_022 7 P5 Global I/O Signal 3 DIR BIDIR P5_IO_032 8 P5 Global I/O Signal 3 COM BIDIR P5_IO_033 9 P5 Global I/O Signal 4 DIR BIDIR P5_IO_043 10 P5 Global I/O Signal 4 COM BIDIR P5_IO_044 11 P5 Global I/O Signal 5 DIR BIDIR P5_IO_054 12 P5 Global I/O Signal 5 COM BIDIR P5_IO_055 13 P5 Global I/O Signal 6 DIR BIDIR P5_IO_065 14 P5 Global I/O Signal 6 COM BIDIR P5_IO_066 15 P5 Global I/O Signal 7 DIR BIDIR P5_IO_076 16 P5 Global I/O Signal 7 COM BIDIR P5_IO_077 17 P5 Global I/O Signal 8 DIR BIDIR P5_IO_087 18 P5 Global I/O Signal 8 COM BIDIR P5_IO_088 19 P5 Global I/O Signal 9 DIR BIDIR P5_IO_098 20 P5 Global I/O Signal 9 COM BIDIR P5_IO_099 21 P5 Global I/O Signal 10 DIR BIDIR P5_IO_109 22 P5 Global I/O Signal 10 COM BIDIR P5_IO_100 23 P5 Global I/O Signal 11 DIR BIDIR P5_IO_110 24 P5 Global I/O Signal 11 COM BIDIR P5_IO_111 25 P5 Global I/O Signal 12 DIR BIDIR P5_IO_121 26 P5 Global I/O Signal 12 COM BIDIR P5_IO_122 27 P5 Global I/O Signal 13 DIR BIDIR P5_IO_132 28 P5 Global I/O Signal 13 COM BIDIR P5_IO_133 29 P5 Global I/O Signal 14 DIR BIDIR P5_IO_143 30 P5 Global I/O Signal 14 COM BIDIR P5_IO_144 31 P5 Global I/O Signal 15 DIR BIDIR P5_IO_154 32 P5 Global I/O Signal 15 COM BIDIR P5_IO_155 33 P5 Global I/O Signal 16 DIR BIDIR P5_IO_165 34 P5 Global I/O Signal 16 COM BIDIR P5_IO_166 34 UNUSED P5_IO_16