FPGA Common Registers 19-NOV-1998 --------------------- Reg Add Description ---- ----------- 0 Chip CSR LSW (all FPGA's) Similar but not identical on all FPGA's. Some bits not writable on all FPGA's. 1 Chip CSR MSW (all FPGA's) Present but totally unused on all FPGA's. All bits read/writable on all FPGA's. 2 Scaler Timing Signal Reset Enable Reg (AONM, FOM, GS, PBS, TRM, TDM, FOM++ FPGA's) All 16 bits R/W on the above FPGA's, but the number of meaningful bits varies. On the BSF FPGA's, this register is used for a different function, but it should be moved as the BSF FPGA's will require a Scaler Timing Signal Reset Enable Register. On the Miguel and Helper FPGA's, this register is "unused" in the sense that it is present, but no bits are meaningful. 3 Scaler Force Reset Register (AONM, FOM, GS, PBS, TRM, FOM++ TDM FPGA's) All 16 bits R/W on the above FPGA's, but the number of meaningful bits varies. On any FPGA, the number of meaningful bits in registers 2 and 3 are the same. On the BSF FPGA's, this register is unused now, but it is required and will be added at this location. On the Miguel and Helper FPGA's, this register is "unused" in the sense that it is present, but no bits are meaningful. 24 HSRO State \ (AONM, FOM, Miguel, FOM++, 25 HSRO Terminal Count | GS, TDM, TRM FPGA's) 26 HSRO Current Count / These registers are identical on all of the FPGA's which have them (all FPGA's with HSRO). See any of the above FPGA description text files for bit usage. The BSF has other registers specified at these addresses (but not yet implemented). They should be moved, see above. The PBS and Helper FPGA's have other registers specified at these addresses. They can be moved if desired. 32 Tick History Shift Reg Latency Control Reg (AONM, FOM, Miguel, FOM++ TDM, TRM FPGA's) This register exists on all FPGA's which have only 1 Tick History Shift Reg Latency Control Register (all FPGA's with Monitor Readout or HSRO *except* the PBS and GS which have indepent control for each channel. The BSF has a different register at this address, but it should be moved, see above. The PBS has a different register at this address, which can be moved if desired. The GS and Helper FPGA's have no registers at this address. 36 Monitor Readback of HSRO States LSW (AONM, FOM, TDM, TRM, FOM++ FPGA's) All 16 bits are read only. The meaning of the bits varies across each FPGA. The BSF has a different register at this address, but it should be moved, see above. The Helper and Miguel FPGA's have different registers at this address, which can be moved if desired. The GS and PBS FPGA's have no registers at this address. 37 Monitor Readback of HSRO States MSW (TDM) All 16 bits are read only. The BSF does not use this address, but it conceivably might. The Miguel has a different register at this address. The AONM, FOM, GS, PBS, TRM, and Helper FPGA's have no registers at this address, but they could conceivably grow them. Other commonalities ------------------- The AONM and FOM have identical programming interfaces. The FOM++ is a superset of the AONM/FOM. The GS and PBS FPGA's have some commonality in how the Common Control Signals are programmed. The GS and PBS have multiple copies of the Tick History Shift Reg Latency Control Register, which look like the corresponding single register in the other FPGA's. The AONM FPGA has the following VME-visible registers: (FOM FPGA is identical) Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Enable Timing Signal Reset 3 R/W Force Scaler Reset 8 R/W Lookup Programming Address Register 16 R/W AOIT(15:0), Channel(3:0) Programming information 17 R/W AOIT(31:16), Channel(3:0) Programming information 18 R/W AOIT(47:32), Channel(3:0) Programming information 19 R/W AOIT(63:48), Channel(3:0) Programming information 20 R/W AOIT(79:64), Channel(3:0) Programming information 21 R/W AOIT(95:80), Channel(3:0) Programming information 22 R/W AOIT(111:96), Channel(3:0) Programming information 23 R/W AOIT(127:111), Channel(3:0) Programming information 24 R HSRO State 25 R/W HSRO Terminal Count 26 R HSRO Current Count 32 R/W Tick History Shift Register Control Reg 36 R Monitor Readout copy of HSRO States 40 R Channel 0 Scaler Monitor Register LSWord 41 R Channel 0 Scaler Monitor Register MSWord 42 R Channel 1 Scaler Monitor Register LSWord 43 R Channel 1 Scaler Monitor Register MSWord 44 R Channel 2 Scaler Monitor Register LSWord 45 R Channel 2 Scaler Monitor Register MSWord 46 R Channel 3 Scaler Monitor Register LSWord 47 R Channel 3 Scaler Monitor Register MSWord The FOM++ FPGA has the following VME-visible registers: (not necessarily final) Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Enable Timing Signal Reset 3 R/W Force Scaler Reset 8 R/W Lookup Programming Address Register 16 R/W AOIT(15:0), Channel(3:0) Programming information 17 R/W AOIT(31:16), Channel(3:0) Programming information 18 R/W AOIT(47:32), Channel(3:0) Programming information 19 R/W AOIT(63:48), Channel(3:0) Programming information 20 R/W AOIT(79:64), Channel(3:0) Programming information 21 R/W AOIT(95:80), Channel(3:0) Programming information 22 R/W AOIT(111:96), Channel(3:0) Programming information 23 R/W AOIT(127:111), Channel(3:0) Programming information 24 R HSRO State 25 R/W HSRO Terminal Count 26 R HSRO Current Count 32 R/W Tick History Shift Register Control Reg 36 R Monitor Readout copy of HSRO States 40 R Channel 0 Scaler Monitor Register LSWord 41 R Channel 0 Scaler Monitor Register MSWord 42 R Channel 1 Scaler Monitor Register LSWord 43 R Channel 1 Scaler Monitor Register MSWord 44 R Channel 2 Scaler Monitor Register LSWord 45 R Channel 2 Scaler Monitor Register MSWord 46 R Channel 3 Scaler Monitor Register LSWord 47 R Channel 3 Scaler Monitor Register MSWord 48 R/W Output Control Register The Board Support Function FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W P5 Global I/O Dir/OE Control 8 R/W G-Link Control % 16 R/W Timing Signal Selection Control * 24 R Header: High-Speed Readout State * 25 R/W Header: High-Speed Readout Terminal Count * 26 R Header: High-Speed Readout Current Count * 27 R Trailer: High-Speed Readout State * 28 R/W Trailer: High-Speed Readout Terminal Count * 29 R Trailer: High-Speed Readout Current Count 32 R/W DAV* Selection 33 R/W DAV* Counter Control 34 R/W HSRO Data Selection 35 R/W HSRO Data Register 36 R/W DCE* Control % Not implemented in AONM BSF * Not presently implemented in any BSF The Helper Function FPGA has the following VME-visible registers: Reg Register Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 8 R/W Transport HSRO Data Control (Normal Mode) 9 R/W Capture HSRO Data Control (Normal Mode) 10 R/W Capture Monitor Data Control (Normal Mode) 11 R/W Front End Error Control (Normal Mode) 15 R/W Select Mode 16 R/W Timing Signal Control Status 0 (Test Mode) 17 R/W Timing Signal Control Status 1 (Test Mode) 18 R/W Timing Signal Control Status 2 (Test Mode) 20 R/W Transport HSRO Data Start Comparator (Test Mode) 21 R/W Transport HSRO Data Stop Comparator (Test Mode) 22 R/W Capture HSRO Data Start Comparator (Test Mode) 23 R/W Capture HSRO Data Stop Comparator (Test Mode) 24 R/W Capture Monitor Data Start Comparator (Test Mode) 25 R/W Capture Monitor Data Stop Comparator (Test Mode) 26 R/W Maginot Line Start Comparator (Test Mode) 27 R/W Maginot Line Stop Comparator (Test Mode) 36 R Timing Signal Status Readback Register (Test Mode) 136 R/W Scaler Reset The Miguel FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 16 R/W Input Term Selection 24 R HSRO State 25 R/W HSRO Terminal Count 26 R HSRO Current Count 32 R/W Shift Register Latency 33 R Triggered Tick Input Term (15:0) 34 R Triggered Tick Input Term (31:16) 35 R Previous Tick Input Term (15:0) 36 R Previous Tick Input Term (31:16) 37 R Previous-1 Tick Input Term (15:0) 38 R Previous-1 Tick Input Term (31:16) 39 R Previous-2 Tick Input Term (15:0) 40 R Previous-2 Tick Input Term (31:16) The Gated Scaler FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Enable Timing Signal Reset 3 R/W Force Scaler Reset 8 R/W Common Gate: CCS Set 0 Mux Control Register 9 R/W Common Gate: CCS Set 1 Mux Control Register 10 R/W Common Gate: CCS Set 2 Mux Control Register 11 R/W Common Gate: CCS Set 3 Mux Control Register 12 R/W Common Gate: Combination Logic Control Register 16 R/W Common Load: CCS Set 0 Mux Control Register 17 R/W Common Load: CCS Set 1 Mux Control Register 18 R/W Common Load: CCS Set 2 Mux Control Register 19 R/W Common Load: CCS Set 3 Mux Control Register 20 R/W Common Load: Combination Logic Control Register 24 R Scaler Channel 0: HSRO State 25 R/W Scaler Channel 0: HSRO Terminal Count 26 R Scaler Channel 0: HSRO Current Count 128 R/W Scaler Channel 0: Load Value LSWord 129 R/W Scaler Channel 0: Load Value MSWord 130 R/W Scaler Channel 0: Gate Control Register 131 R/W Scaler Channel 0: Load Control Register 132 R/W Scaler Channel 0: Beam Crossing History SR MUX Control 133 R Scaler Channel 0: Monitor Register LSWord 134 R Scaler Channel 0: Monitor Register MSWord 136 R/W Scaler Channel 1: Load Value LSWord 137 R/W Scaler Channel 1: Load Value MSWord 138 R/W Scaler Channel 1: Gate Control Register 139 R/W Scaler Channel 1: Load Control Register 140 R/W Scaler Channel 1: Beam Crossing History SR MUX Control 141 R Scaler Channel 1: Monitor Register LSWord 142 R Scaler Channel 1: Monitor Register MSWord 143 R/W Scaler Channel 1: Scaler Gate MUX Control 144 R/W Scaler Channel 2: Load Value LSWord 145 R/W Scaler Channel 2: Load Value MSWord 146 R/W Scaler Channel 2: Gate Control Register 147 R/W Scaler Channel 2: Load Control Register 148 R/W Scaler Channel 2: Beam Crossing History SR MUX Control 149 R Scaler Channel 2: Monitor Register LSWord 150 R Scaler Channel 2: Monitor Register MSWord 151 R/W Scaler Channel 2: Scaler Gate MUX Control 152 R/W Scaler Channel 3: Load Value LSWord 153 R/W Scaler Channel 3: Load Value MSWord 154 R/W Scaler Channel 3: Gate Control Register 155 R/W Scaler Channel 3: Load Control Register 156 R/W Scaler Channel 3: Beam Crossing History SR MUX Control 157 R Scaler Channel 3: Monitor Register LSWord 158 R Scaler Channel 3: Monitor Register MSWord 159 R/W Scaler Channel 3: Scaler Gate MUX Control The Per-Bunch Scaler FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Enable Timing Signal Reset 3 R/W Force Scaler Reset 8 R/W CCS Set 0 Mux Control Register 9 R/W CCS Set 1 Mux Control Register 10 R/W CCS Set 2 Mux Control Register 11 R/W CCS Set 3 Mux Control Register 12 R/W Scaler Gate Combination Control Reg 16 R/W Scaler Channel 0 Tick Sel Control Reg 17 R/W Scaler Channel 0 Beam Crossing History SR MUX Control 18 R Scaler Channel 0 Monitor Register LSWord 19 R Scaler Channel 0 Monitor Register MSWord 20 R/W Scaler Channel 1 Tick Sel Control Reg 21 R/W Scaler Channel 1 Beam Crossing History SR MUX Control 22 R Scaler Channel 1 Monitor Register LSWord 23 R Scaler Channel 1 Monitor Register MSWord 24 R/W Scaler Channel 2 Tick Sel Control Reg 25 R/W Scaler Channel 2 Beam Crossing History SR MUX Control 26 R Scaler Channel 2 Monitor Register LSWord 27 R Scaler Channel 2 Monitor Register MSWord 28 R/W Scaler Channel 3 Tick Sel Control Reg 29 R/W Scaler Channel 3 Beam Crossing History SR MUX Control 30 R Scaler Channel 3 Monitor Register LSWord 31 R Scaler Channel 3 Monitor Register MSWord 32 R/W Scaler Channel 4 Tick Sel Control Reg 33 R/W Scaler Channel 4 Beam Crossing History SR MUX Control 34 R Scaler Channel 4 Monitor Register LSWord 35 R Scaler Channel 4 Monitor Register MSWord The Trigger Decision Module FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Enable Timing Signal Reset 3 R/W Force Scaler Reset 24 R High-Speed Readout State 25 R/W High-Speed Readout Terminal Count 26 R High-Speed Readout Current Count 32 R/W Tick History Shift Register Control Reg 36 R Monitor States (LSW) 37 R Monitor States (MSW) 40 R Scaler Channel 0: Specific Trigger Fired (LSW) 41 R Scaler Channel 0: Specific Trigger Fired (MSW) 42 R Scaler Channel 1: Specific Trigger Exposed (LSW) 43 R Scaler Channel 1: Specific Trigger Exposed (MSW) 44 R Scaler Channel 2: Physics And-Or Fired (LSW) 45 R Scaler Channel 2: Physics And-Or Fired (MSW) 46 R Scaler Channel 3: DAQ Enable (LSW) 47 R Scaler Channel 3: DAQ Enable (MSW) 48 R Scaler Channel 4: Decorrelated DAQ Enable (LSW) 49 R Scaler Channel 4: Decorrelated DAQ Enable (MSW) 50 R Scaler Channel 5: Correlated DAQ Enable (LSW) 51 R Scaler Channel 5: Correlated DAQ Enable (MSW) 52 R Scaler Channel 6: Prescaler Disable (LSW) 53 R Scaler Channel 6: Prescaler Disable (MSW) 54 R Scaler Channel 7: COOR Disable (LSW) 55 R Scaler Channel 7: COOR Disable (MSW) 56 R Scaler Channel 8: Auto Disable (LSW) 57 R Scaler Channel 8: Auto Disable (MSW) 80 R/W Exposure Group Partial Enable Selection 81 R/W Front End Busy and Global Disable Selection 82 R/W Individual Disable, Prescaler, Auto Disable Selection 83 R/W COOR Disable 84 R/W Auto Disable Control The TRM FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Scaler Timing Signal Reset Enable Register 3 R/W Scaler Force Reset Register 8 R/W FIFO Control Status Register 9 R FIFO Error Reporting Register 10 R FIFO Counter Status Register 12 R/W Test Data Register A 13 R/W Test Data Register B 16 R/W Output Term Source Selection Register 24 R HSRO State 25 R/W HSRO Terminal Count 26 R HSRO Current Count 32 R/W Tick History Shift Register Control Reg 36 R Monitor Readout copy of HSRO States 40 R Output Term 0 Scaler Monitor Register (LSW) 41 R Output Term 0 Scaler Monitor Register (MSW) 42 R Output Term 1 Scaler Monitor Register (LSW) 43 R Output Term 1 Scaler Monitor Register (MSW) 44 R Output Term 2 Scaler Monitor Register (LSW) 45 R Output Term 2 Scaler Monitor Register (MSW) 46 R Output Term 3 Scaler Monitor Register (LSW) 47 R Output Term 3 Scaler Monitor Register (MSW)