Elements common to all FPGA's for THE Card
              ------------------------------------------

                                                        21-AUG-1996 


All FPGA designs for THE Card (except the VME Interface FPGA, which is
necessarily somewhat different, due both to its configuration method 
and status as "master" of the On-Card Bus) must share some common
elements.  These elements are:

    - On-Card Bus Interface
    - Configuration Interface
    - JTAG Interface
    - High-Speed Readout Interface

This file describes the functionality required of each common element,
and also details the implementation (e.g. FPGA resources, pins required)
of each of these elements.


On-Card Bus Interface
---------------------

The On-Card Bus is specified in THE_CARD_VME_INTERFACE.TXT.  

The On-Card Bus Interface has been made as an MSU FPGA Library
component.  Additionally, the template preference file specifies pin 
assignments to be used for place and route.

Internally, all FPGA's have a separate Read_Data and Write_Data bus.  
These busses are distributed on horizontal longlines within the FPGA,
and use internal pullup resistors to define the levels on these busses
when the FPGA is not being read from or written to respectively.

The OCB Interface makes decoded versions of the Register Address
signals, gated by the Wakeup and Write and Write Strobe condition (for
Write_Register) or the Wakeup and Read condition (for Read_Register).
All 512 register addresses are decoded in the OCB Interface library
component--the NeoCAD place and route software will optimize out any
unused decoders.  An undecoded version of the Register Address signals, 
gated only by the Wakeup condition, is also available.  


Configuration Interface
-----------------------

The mechanics of FPGA configuration are described in the file
THE_CARD_VME_INTERFACE.TXT (and will be expanded either there or
in a new file soon).  

A "startup" component, from the Xilinx XC4000 XACT_LIB, is required 
to allow OCB control of the FPGA's internal Global Tri-State net (i.e.
to disable this FPGA from driving its outputs active until allowed to
do so by the VME Interface FPGA).  Only the "GTS" pin on this 
component needs to be connected.  Controlling the FPGA's outputs in
this manner avoids the need for interconnecting all FPGA DONE or INIT*
lines, or other "output enable" synchronizing mechanisms described in
Xilinx documentation.  Note that there is no OCB control of the Global
Set/Reset net of the FPGA's.  


JTAG Interface
--------------

The mechanics of JTAG boundary scan are yet to be described.

A "bscan" component,  from the Xilinx XC4000 XACT_LIB, is required to
allow boundary scan.  the TDI, TMS, TCK, and TDO pins of this component
must be hooked up to the TDI, TMS, TCK, and TDO pad symbols (also from
XACT_LIB) respectively.


High-Speed Readout Interface
----------------------------

The mechanics of the High-Speed Readout are yet to be described.

The HSRO Interface is (will be) an MSU FPGA Library component.


Template preference file
------------------------