FPGA Pins that are involved with Configuration
       ------------------------------------------------


TO the Target FPGA
==----------------

             Fixed
               or
 Pin Name     UCF    Function during configuration after configuration
----------   -----   -------------------------------------------------

Lower 8 of    ucf    only the lower byte of the 16 bit on card data bus
the 16 bit           is used
 data bus            D7=P123    D6=P129    D5=P141    D4=P148
                     D3=P152    D2=P159    D1=P173    D0=P177


Program *     fxd    aka Configure Chip   must go low then hi to begin the
                     configuration process.  Individual lines from VME IF
                     to each FPGA.  pin 122


OCB           ucf    from VME IF to all FPGA's in parallel   pin 183
Write         fxd    This is also write strobe during configuration.
Strobe *


OCB           ucf    from VME IF individual lines to each FPGA.  pin 142
Chip          fxd    This is  CS0*  during configuration.
Select *


FPGA Output   ucf    pin 187
Enable *      fxd    This is  CS1  during configuration.




FROM the Target FPGA
====----------------

             Fixed
               or
 Pin Name     UCF    Function during configuration after configuration
----------   -----   -------------------------------------------------

LDC           fxd    Low During Configure.  Goes only to a via.   pin 68


HDC           fxd    High During Configure.  One configured used as the
              ucf    Daisy Chain Enable output.  pin 64.


Done          fxd    aka Chip ConfigurED.   Individual lines back to VME
                     interface.   pin 120


Error         fxd    Open drain.  All 17 tied together.  Pulls low if there is
                     an error during configuration.  If it is low then a chip
                     will not be able to configure properly.   Can be read
                     in the VME IF chip.   pin 89


RdyBusy       fxd    During configuration process it says when it is OK
              ucf    to ingest the next byte.  After configuration this is
                     the "Chip Status" back to the VME interface.  These
                     are individual lines back to the VME IF.   Pin 174