FPGA Designs needed for Run II ------------------------------ Original: 10-APR-1995 Latest: 22-SEP-1995 Introduction ------------ This file attempts to enumerate the different FPGA designs (not types of FPGA devices) which will be required for the Run II Frameworks. This list will almost certainly be wrong, but we need to start thinking about this topic for the following reasons: 1. There will probably be a nontrivial number of FPGA designs required. Each design will be somewhat complex (similar in complexity to some old L1 Framework cards). 2. With careful thought, some FPGA designs may serve similar functions on multiple cards. Possibly some FPGA designs will differ only in pinout or some other detail. 3. We need to understand which design entry method is appropriate for each FPGA The FPGA designs are grouped by system (L1 vs. L2) and card, because these categories are well-defined and provide some way to organize the list. Note though that even these categories (especially card) are still subject to change. The current categories are: I. Level 1 Trigger Framework (total # of FPGA designs = 10 to 13) A. Term Receiver Module B. And-Or Network Module C. Trigger Decision Module D. L1 Framework Output Module E. Error Map Module (also used in L2) F. Scaler Module - Fast Readout (also used in L2) G. Scaler Module - Monitor Readout (also used in L2) H. Support Functions Module (also used in L2) II. Level 2 Trigger Framework (total # of FPGA designs = 2 to 7) A. L2 Processor Receiver/Derandomizer B. L2 Processing Done C. L2 Decision Confirm/Veto D. L2 Geo Sect Accept/Reject E. L2 Controller Card List of FPGA Designs -------------------- I. Level 1 Trigger Framework ----------------------------- I-A. Term Receiver Module: Input: 64 AOIT's Output: 64 AOIT's (de-skewed, correct Bx) Readout: 64 AOIT states (approp. Bx) (DB) some scalers/states (M) There is only one FPGA design required for this card. See Term_Receiver_Module_Description.Txt for details. I-B. And-Or Network Module Input: 128 de-skewed AOIT's, clock Output: 64 Spec Trig AndOr (2nd stage) Fired Readout: none (?) There is only one FPGA design required for this card. See And_Or_Network_Module_Description.Txt for details. I-C. Trigger Decision Module Input: 2 Phy/AOF * 16 ST = 32 2 BC/AOF * 16 ST = 32 1 FEBz * 16 ST = 16 48 "other" clock(s) Output: 16 Spec Trig Fired to FOM 16 Spec Trig Fired to DBR Scaler 16 Spec Trig Live to DBR Scaler Readout: several states and counts (M) There is only one FPGA design required for this card. See Trigger_Decision_Module_Description.Txt for details. I-D. L1 Framework Output Module Input: 64 Specific Trigger Fired clock Output: 64 Geo Sect L1 Accept/Reject to SLIM and MR Scaler 1 Spec Trig Fired Strobe Readout: state Geo Sect Accepts (DB) There is only one FPGA design required for this card. This FPGA is a derivative of the And-Or Network Module FPGA. See Framework_Output_Module_Description.Txt for details. I-E. Error Map Module Input: 128 Geo Sect w/L1 Error signals clock Output: 1 "Stop L1 Accepts" signal Readout: mask of Geo Sect errors (M) No detailed partitioning of this module has yet been done. It seems likely that only one or two FPGA designs will be required. They should be synthesizable. I-F. Scaler Module - Fast Readout Input: 16 gates 16 clocks Output: none Readout: 16 counts (DB) No detailed partitioning of this module has yet been done. It seems likely that only one or two FPGA designs will be required. A possible division has 16 "do-everything" FPGA's, one per channel. Another option has 8 "two-channel" scalers with 8 "two-channel" pipeline/readout chips. They may be synthesizable. I-G. Scaler Module - Monitor Readout Input: 64 gates 64 clocks Output: none Readout: 64 counts (M) No detailed partitioning of this module has yet been done. Again, only one or two FPGA designs should suffice. They should be synthesizable. I-H. Support Functions Module No detailed design of this module has been done. It is unclear how many different FPGA designs would be required for this module. Let's call it between 1 and 4. They may be synthesizable. II. Level 2 Trigger Framework ----------------------------- II-A. L2 Processor Receiver Input: 1 Done * 6 Proc = 6 1 Answer * 6 Proc = 6 16bit T.N * 6 Proc = 96 16bit Current Trig Number clock Output: 1 Curr Done * 6 Proc = 6 1 Curr Ans * 6 Proc = 6 Readout: 1 Curr Done * 6 Proc = 6 (DB) 1 Curr Ans * 6 Proc = 6 (DB) No believable detailed partitioning of this module has been done yet. But looking at the relative simplicity of this module (it looks input bound not logic bound) it would seem that only one FPGA design (a "do-everything" chip) would be required. Two or three of these chips might do the job (2 or 3 Processors served per chip). Can we think of something to do with the rest of the chips on the card? These FPGA's are probably synthesizable. II-B. L2 Processor Done Input: 64 Curr Done 64 Spec Trig Fired clock(s) Output: Global Done 64 L2 In Progress Readout: none This card appears similar to (or identical with) the L1 And-Or Network Module. At first glance, both make a programmable AND of 128 inputs to produce 64 outputs. Just think of the "L2 Proc Done" and the "Spec Trig Fired" signals as "And-Or Input Terms." Let's pretend that no new FPGA designs are required for this card in the best case, and that two are required in the worst case. II-C. L2 Confirm/Veto Input: 64 Curr Answer 64 Spec Trig Fired Global Done Output: 1 Decision Accept (Reject) 64 ST Confirmed (Vetoed) Readout: 64 ST Confirmed (Vetoed) (DB) Again these cards appear similar to the And-Or Network Module (unless I am fooling myself). Let's pretend that we don't need to make new FPGA's for these cards in the best case, and that two are required in the worst case. II-D. L2 Geo Sect Accept/Reject Why isn't this the same as the L1 FOM? If we had separate Accept and Reject cards, then wouldn't each one be identical to the L1 FOM? If not, then we may be able to borrow the L1 FOM FPGA design, which in turn may be based on the L1 AONM FPGA. II-E. L2 Controller Card Input: 16-bit L1 Trigger Number 64-bit Spec Trig Fired strobe Output: 64-bit ST Fired time-muxed with 16-bit L1 Trig Number Readout: 16-bit L1 Trig Number (DB) No detailed partitioning done but let's say that 2 FPGA designs are required. They are very likely synthesizable.