THE-Card Customizations
                    ---------------------------

                                                  Original Rev.  7-MAR-2000
                                                   Current Rev. 31-JAN-2002


This files describes the customizations that are needed to various THE-Cards
in the L1 and L2 Trigger Frameworks.  Most of this is installing resistor
packs near the P5 Global I/O connector but there are also some white wires.


FOM++

  The FOM++ needs 4 white wires to allow it to ingest the 4 "Hardware L1 
  Qualifiers" that it receives via its P5 connector.  These wires get the
  Hardware L1 Qualifiers from the BSF FPGA into the MSA FPGA's that generate
  L1 Qualifiers - L3 Transfer Number.  See the document l1/framework/hardware/
  aonm/special_functions_fom.txt  for a description of this.

  The white wires are:

   BSF P4   (via J26) to MSA 1 and 5 P157 (RA8 via)
   BSF P238 (via J27) to MSA 2 and 6 P157 (RA8 via)
   BSF P237 (via J28) to MSA 3 and 7 P157 (RA8 via)
   BSF P236 (via J29) to MSA 4 and 8 P157 (RA8 via)

   The FOM++ also needs 110 ohm 6-pin non-bussed termination resistors
   installed in sites:

           R146, R147, R148, R149, R150, R151



L2 TRM's

   We need to get the  FIFO Not Empty  signal from some of the TRM's cards
   that feed data to the L2 Framework.  We need the FIFO Not Empty signal
   from one of the  L2 Global Answer  TRM's and from the  L1 Auxiliary Data
   TRM.  As things have been installed we are using the  L2 Global Answer
   63:0  to get the FIFO Not Empty signal from the L2 Global TRM's.

   The white wire is:

       VME P187 (via J201)  to  BSF P65 (BG_IO(0))

   The via for VME FPGA pin 187, i.e. via J201, is located near the pin 180 - 
   pin 181 corner of the VME FPGA and it is the center via in the array of 
   5 via's labeled "I/O Via's".  This via for pin 187 is a small via.

   The via that connects to BSF FPGA pin 65 is located near the pin 61 -
   pin 120 edge of MSA FPGA #5.  It is the via nearest the BSF FPGA in an
   array of 16 via's.  It is labeled "BG-IO(0)".  It is a small via.

   The  FIFO Not Empty  signal is sent out through  P5_IO(16).  To make this
   work we need to supply pull down current by installing 56-ohm 6-pin bussed
   resistors networks in sites:

           R154, R155


   For both  L1 Specific Trigger Fired TRM's  we need to install terminator 
   resistors for P5_IO(0).  For these 2 TRM's, P5_IO(0) is used to receive
   the  L2 Capture Monitor Data  signal that comes from the L2 FW Helper.
   Install 110-ohm 6-pin non-bussed termination resistors in sites:

           R146, R147


 
TDM's

   The eight TDM's need to send their "Mark and Pass PreScaler Outputs" to
   the FOM++ where these signals are combined to become a L1 Qualifier. 
   The Mark and Pass PreScaler Outputs are sent off of the TDM's via their
   P5_IO(16) output.  To provide pull down current for these outputs we
   need to install on the TDM cards 56-ohm 6-pin bussed pulldown resistors
   in sites:

        R154, R155



FM D_Latch in M123 Bottom

   The FM-Latch in slot 20 of M123 Bottom receives its  L2 Capture Monitor
   Data signal via its P5_IO(0).  The L2 Capture Monitor Data signal comes
   from the L2 FW Helper and arrives on a gray twisted pair cable as a
   single signal connection.  We need to terminate this input to the FM-Latch
   for it to properly receive the L2 Capture Monitor Data signal.  
   So, install 110-ohm 6-pin non-bussed termination resistors in sites:

        R146, R147