"THE" Card -------------------------------------------------- Original Rev. 27-JUN-1995 Most Recent Rev. 31-OCT-1996 The purpose of this document is to describe "THE" Card and in particular to describe the features of THE Card that are common to all instances of THE Card. These common features are generally associated with the perimeter of THE Card but may also include some of the features in the Main Signal Array of 16 FPGA's. This array of 16 FPGA's provides the principal signal processing structure on THE Card and it is also the area that shows the most change between different versions of THE Card. In general all of the high speed signal processing that is preformed on THE Card once every 132 nsec period is performed by the logic in the array of 16 FPGA's. The other sections of THE Card, e.g. the VME Interface and the I/O connections, just support this array of 16 FPGA's. This description of THE Card is divided into the following sections: 1. The VME Interface 2. The P1 Timing Signal Inputs, Processing, and Distribution 3. The Main Signal Processing Array of 16 FPGA's 4. The Main Signal Array Inputs 5. The Main Signal Array Outputs 6. The Board Global Signal I/O Connections and Processing 7. Monitor Data capture and readout 8. The High Speed Readout Section 9. The Board Support Functions FPGA (BSF FPGA) 10. The JTAG Scan Path 11. Block diagram of THE Card 12. Detailed listing of P1, P2, P3, P4, P5 connector pin assignments 13. Notes about FPGA IOB usage/configuration All instances of THE Card are built with the 9U by 400mm Eurocard physical format (14.437" tall by 15.748" front to back). All instances use P1,P2, and P3 rear connectors. These are 5 row DIN connectors (ERNI standard part number 013167). THE Card is provided with the following supply voltages: +5V, +3.3V, -2V, -4.5V. The intent is that the bulk of THE Card's logic will operate from +3.3V while the +5V, -2V, and -4.5V are used just for I/O receivers and drivers and other special functions. THE Card is designed to operate in the D0 Run II Level 1/Level 2 Trigger Backplanes, which are custom-built backplanes installed in standard 9U Eurocard (VME) card files. All instances of THE Card use a VME interface to provide the connection back to the Trigger Control Computer. This VME interface is used by the Trigger Control Computer to configure, program, and monitor THE Cards. The VME interface does not provide the event by event data block readout path. The event readout path (frequently referred to as the high speed readout) is optical and utilizes the same components as are used in the event readout for the Silicon Vertex Detector and the Central Fiber Tracker. Not all instances of THE Card will have this high speed readout installed. 1. VME Interface ---------------- The VME Interface on THE Card is implemented with an FPGA and TTL MSI receivers and drivers for connecting to the VME Bus itself. The VME Interface needs to perform the following functions on THE Card: 1. Load configurations into the other 17 FPGA's on THE Card. 2. Provide the readout path for the Monitor Data from THE Card, 3. Provide the path by which THE Card can interrupt the Trigger Control Computer. 4. Provide various board level functions, e.g. Board-Level Registers to control and monitor the configuration status and operation of the other 17 FPGA's. The intent is to have all instances of THE Card use the same configuration for the FPGA in their VME interface. The FPGA in the VME interface is configured from a serial EPROM. This allows the VME interface to be operational shortly after the card receives power. Using the same VME interface in all instances of THE Card is important both to minimize the designing effort spent on this section of THE Card an also to help make all versions of THE Card appear unform to the Trigger Control Computer. Because we have limited the scope of the functions that the VME interface must be able to perform; THE Card's VME interface is implemented as a D16 A24 slave only with simple interrupt capability. A full detailed description of the VME Interface is presented in the file: The_Card_VME_Interface.Txt. 2. The P1 Timing Signal Inputs, Processing, and Distribution ------------------------------------------------------------ All instances of THE Card will typically require a number of timing signals in order to carry out their functions in a coordinated manner with the rest of the Trigger Framework. Because of the high speed operation of the Trigger Framework, these timing signals must be accurately generated and distributed to the various crates in the Trigger Framework and once received in a crate carefully distributed to all of THE Cards in the crate. Once on a given THE Card this careful processing and distribution must continue down to the FPGA's in the array of 16 Main Signal Processing FPGA's. Even once inside these FPGA's special handling continues through the use of denticated routing resources for these clock signals. On THE Card, 16 timing signals are received in differential ECL format on a portion of the 5 row P1 connector. These signals, called the P1 Timing Signals, are received with National 100325 ECL to TTL translator integrated circuits and routed to the Board Support Functions FPGA. The routing of these signals on THE Card circuit board receives special care to maintain the integrity of these signals. Once the 16 P1 Timing Signals are inside the Board Support Functions FPGA some of them may receive processing before being sent down to the array of 16 Main Signal Processing FPGA's. Examples of the type of processing that these timing signals will frequently receive inside the BSF FPGA include: 1. Selecting which P1 Timing Signals will be used by the Main Signal Processing FPGA's and making enough copies of these selected timing signals to send them to all the Main Signal Processing FPGA's that need them. 2. Deriving new timing signals to send the the Main Signal Processing FPGA's by making combinations of the P1 Timing Signals or by digitally delaying or stretching a timing signal. 3. Re-Synchronizing timing signals sent to the Main Signal Processing FPGA's by updating their state only at a point in time defined by one of the P1 Timing Signals. 4. Providing the logic necessary to allow the Trigger Framework when it is in a test mode to both: process a single event and then hold its state to allow diagnostic work, and to "microstep" through the processing of a single event to allow diagnostic work at each microstep. The P1 Timing Signals as received on THE Card are named P1_TS_00 through P1_TS_15. The first of these, P1_TS_00, is the 53.104 MHz clock. The next 7 signals, P1_TS_01 through P1_TS_07 are each continuously running pulse trains that are high for 3 ticks of 18.8 nsec and low for 4 ticks of 18.8 nsec. P1_TS_01 has a positive edge at the beginning of each 132 nsec beam crossing period. The other 6 similar timing signals, P1_TS_02 through P1_TS_07 each have their positive edge start one 18.8 nsec tick later in the 132 nsec beam crossing period. Timing signal P1_TS_08 marks each 132 nsec beam crossing period during which the L1 Trigger Framework is to begin the processing to form a new Level 1 Trigger Decision. Note that this IS different from the 132 nsec periods during which the beam crossings actually occur and is also different from the 132 nsec periods during which the Level 1 Framework will send out L1 Trigger Decisions. Timing signal P1_TS_09 indicates to all of THE Cards in the Trigger Frameworks that they should capture Monitor Data. Timing signal P1_TS_10 indicates to all of THE Cards in the Trigger Frameworks that they should capture Monitor Data when the next L1 Accept occurs. Timing signal P1_TS_11 Timing signal P1_TS_15 The timing signals as sent to the Array of 16 Main Signal Processing FPGA's (i.e. after processing in the Board Support Functions FPGA) are called the High Quality Array Timing Signals. These are described in some detail later in this document. 3. The Main Signal Processing Array of 16 FPGA's ------------------------------------------------ This array of 16 FPGA's provides the logic resources that are used by each version of THE Card to perform its designed functions. The principal differences between different versions of THE Card lie in the configuration of these 16 FPGA's and in the circuit board wiring between them and the Array Main Signal Inputs and Outputs. The intent is to have all instances of THE Card use the same type of FPGA in the Main Signal Processing Array. Although in some cases this may lead to underutilization of the logic resources the big advantages are that the printed circuit board layout remains more constant, we can gain skill by specializing in implementing logic in one type of FPGA, and different versions of THE Card are not limited as to what functions they can perform because they used smaller FPGA's. In the following section we list all of the signals and busses that are connected to the Main Signal Processing Array: 1. The Main Signal Array Inputs come onto THE Card via the P2 and P3 connectors. There are 128 Main Signal Array Inputs which are labeled MSA_In_000 through MSA_In_127. These signals are the event to event dynamic inputs signals that the Main Signal Processing Array works on. Different versions of THE Card will need to have different routings of these input signals into the Main Processing Array. The intent is that all versions of THE Card will share exactly the same routing in the section of THE Card that contains the differential line receives, the line terminators, and series terminators for these signals. But, different version of THE Card may vary in the routing that carries these signals from their series terminator resistors into the Main Signal Processing Array itself. 2. The Main Signal Array Outputs exit THE Card via the front panel 5 row DIN connector P4. There are 64 Main Signal Array Outputs which are labeled MSA_Out_00 through MSA_Out_63. These signals are the event to event dynamic output signals from the Main Signal Processing Array. Different versions of THE Card will need to have different routings of these output signals from the Main Signal Processing Array to the output drivers. The intent is that all versions of THE Card will share exactly the same routing in the section of THE Card that contains the drivers for the 64 Main Array Output signals but that different version of THE Card may vary in the routing that carries these output signals from the Main Array Signal Processing FPGA's to these output drives. 3. The On_Card_Bus visits each of the 16 FPGA's in the Main Signal Processing Array (and the Board Support Function FPGA). The On-Card_Bus originates in the VME Interface FPGA and is used for a number of functions including: loading the FPGA's with their configurations, loading and reading registers in the FPGA's to setup the Framework for a run, and reading Monitor Data from registers in the FPGA's. The On_Card_Bus includes 16 data lines, 8 address lines, direction and strobe control lines, an FPGA output enable signal, and radial FPGA "chip select," chip status, configure chip, and chip configured signals. The chip status and chip configured signals carry information from each FPGA to the VME Interface, while all other signals carry information from the VME Interface to each FPGA. The On_Card_Bus is described fully in the file: THE_Card_VME_Interface.TXT 4. The High Quality Array Timing Signals originate in the Board Support Functions FPGA and 4 of them connect to each FPGA in the Main Signal Processing Array. The intent is to keep the arrangement of the High Quality Array Timing Signal distribution constant on all versions of THE Card. This arrangement has a total of 16 High Quality Array Timing Signals originating in the BSF FPGA with 4 of these signals connected to each of the 4 FPGA's in each column in the array. Each of the columns receives a different set of 4 High Quality Array Timing Signals from the Board Support Functions FPGA. 5. The Main Signal Processing Array FPGA's can also send or receive signals via the Board Global Signal Array lines. These lines connect FPGA's in the Main Signal Processing Array with the Board Support Functions FPGA. The use and routing of these lines is likely to vary quite a bit from one version of THE Card to the next. Some of these lines may be radial from the BSF FPGA to the individual array FPGA's and other lines could be some kind of bus or open drain pull cord. Often these lines will be used to send or receive signals from the front panel Board Global I/O Signal connector, P5. 6. Some versions of THE Card include a High Speed Readout to an SAR module. Only the versions of THE Card that need to contribute information to the Framework Data Block include the High Speed Readout. The FPGA's in the Main Signal Processing Array deliver their data to the High Speed Readout over dedicated bused lines. To control how fast these lines need to cycle and to control how many FPGA's drive a bus, there may be more than one bus feeding the High Speed Readout section. Except for power and ground there are no other connections to the FPGA's in the Main Signal Processing Array. 4. The Main Signal Array Inputs ------------------------------- The principal source of signals that the Main Signal Processing Array FPGA's work on come from the Main Array Signal Inputs on the P2 and P3 connectors. There are 128 of these inputs and they are labeled MSA_In_000 through MSA_In_127. These signals are received as differential ECL pairs on THE Card. These signals may be optionally terminated on THE Card. After being received and converted into 5V TTL levels these signals pass through series terminator resistors before being routed into the Main Signal Processing Array. These series terminators are used for 2 reasons. They control the overshoot and bounce of these signals as they travel through the Main Signal Processing Array and they limit the current that could flow from the 5V TTL high voltage level output into a 3.3V CMOS input. The routing of these signals into the Main Signal Processing array will vary from one version of THE Card to the next. On some versions of THE Card some of the Main Array Signal Inputs will need to be routed to all 16 of the Main Signal Processing Array FPGA's. On other versions of THE Card a given Main Signal Array Input will only connect to one of the FPGA's. In any case the intent is to limit the differences in this signal routing to the traces between the series terminator resistors and the FPGA signal input pins. The P2 and P3 connectors that receive this signals are 5 row DIN connectors. These 5 rows are labeled A through E. As viewed from the rear of the VME crate, row A of a connector is to the right and row E is to the left. Pin #1 is at the top of the connector and pin #32 is at the bottom. Row C of both P2 and P3 is used for power and ground signals. The arrangement of the Main Array Signal Inputs on these two connectors is shown in the following table. In all cases the non-inverted signal of a differential pair is received by a pin in rows B or E and the inverted half of the signal is received by a pin in row A or D. MSA_In_000 : MSA_In_031 received on P2 rows A,B pins 1:32 MSA_In_032 : MSA_In_063 received on P2 rows D,E pins 1:32 MSA_In_064 : MSA_In_095 received on P3 rows A,B pins 1:32 MSA_In_096 : MSA_In_127 received on P3 rows D,E pins 1:32 5. The Main Signal Array Outputs -------------------------------- The principal output signals from the Main Signal Processing Array are routed through TTL to differential ECL drivers and then to a 5 row DIN connector on the front panel. There are 64 of these Main Signal Array Outputs which are labeled MSA_Out_00 through MSA_Out_63. These are the signals that carry the output results from the processing that has taken place in Main Signal Processing Array. The intent is to keep the routing of the section of the circuit board that contains the output driver chips, their pull down resistors, and their connections to the output connector constant from one version of THE Card to the next. The routing of output signals from the FPGA's in the Main Signal Processing Array to the output drives will vary from one version of THE Card to the next. A single On Card Bus signal, called Main Signal ECL Output Enable, is used to enable/disable these ECL outputs. The state of the Main Signal ECL Output Enable signal is controllable from a register in the VME interface FPGA. The Main Array Output Signals are driven off card using National 100324 TTL to differential ECL drivers. Recall that when a 100324 is "disabled" the differential ECL outputs are actually forced to a valid differential ECL '0.' The 5 row DIN connector that is used on the front panel for the Main Array Output Signals is exactly the same type of connector that THE Card uses for connection to the P1, P2, and P3 backplanes, i.e. ERNI part number 013-167. But because this connector is effectively "turned upside down" when it is mounted along the front edge of THE Card; when viewing this connector from the front of THE Card, pin number 1 of this connector will be at the bottom and pin number 32 at the top. Row A will be on the viewer's left and row E on the viewer's right. The orientation of the connector pins of the front panel Main Array Output Signal connector is show in the following sketch. +---------+ | THE | | Card | | | THE Card front panel | Front | viewed from the front. | Panel | | | | +-----+ | | | 32 | | | | | | Orientation of the connector | |ABCDE| | pins on the front panel Main | | | | Array Output Signal connector. | | 1 | | | +-----+ | | | +---------+ The Main Array Output Signals are arranged on these connector pins so that the output signals appear in the normal rational order. This order is: signals of less significance at the top, more significant signals at the bottom, less significant cable to the right and more significant cable to the left. The inverted and non-inverted sides of a differential signal are carried in the normal way that results in rows A and D of this front panel connector carrying the non-inverted half of a signal and rows B and E carrying the inverted half of the signal. Thus, when viewing the front panel from the front, the Main Array Output Signals appear as shown below: +---------+ | THE | | Card | | | THE Card front panel | Front | viewed from the front. | Panel | | | | +-----+ | | |32 00| | | | | | | | MSA | | Arrangement of the front panel | | Out | | Main Array Output Signals. | | | | | |63 31| | | +-----+ | | | +---------+ To summarize the arrangement of the signals on the Main Array Output Signal front panel connector: MSA_Out_00 is on Front panel connector pin 32, D is non-inv, E is inv MSA_Out_31 is on Front panel connector pin 1, D is non-inv, E is inv MSA_Out_32 is on Front panel connector pin 32, A is non-inv, B is inv MSA_Out_63 is on Front panel connector pin 1, A is non-inv, B is inv 6. The Board Global Signal I/O Connections and Processing --------------------------------------------------------- For a number of the functions performed by THE Card it will be essential to have some board level input and/or output connections other than those provided by the Main Signal Array Input and Output connectors. These additional board level (i.e. globally available for use where needed on THE Card) I/O connection will be provided by a front panel 34 pin connector. These Global I/O Signals are differential ECL pairs just like the Main Array Signals. There are 17 Board Global I/O signals which are named P5_Glb_00 through P5_Glb_16. Each of these signals is capable of being either an input to or an output from THE Card. Provision is made on THE Card circuit board for installing terminators or pull down resistors on these signals. Note that EITHER terminators (for inputs) or pull-down resistors (for outputs), but NOT both, should be installed for each signal. That is, each signal is not truly bidirectional, but rather must be configured either as a dedicated input or dedicated output. As shown in the sketch below, both the P5 Global I/O Signals themselves and the output driver enable and direction control signals will be routed to the Board Support Functions FPGA. As with the other I/O sections on THE Card, the intent is to keep the circuit board routing in the vicinity of these drivers, receivers, I/O connector, and the connections to the BSF FPGA constant across all versions of THE Card. As with the P1_TS_%% signals, the only on-card resource with direct access to the P5_Glb_%% signals is the BSF FPGA. When one of these signals is used as an input, the BSF FPGA may combine it with any other signals available within itself to generate a signal which may be distributed on THE Card. Conversely, the BSF may combine any signals it has available to create a P5_Glb_%% output signal. The Board Global Signal array lines (described in the Main Signal Array section) may be used by the BSF FPGA to either collect signals from or distribute signals to the Main Signal Array FPGA's. The configuration in the BSF FPGA and the routing of the Board Global Signal Array lines may change from one version of THE Card to the next. The Global I/O connector uses 100398 bidirectional TTL/ECL converters. As a result, direction and output enable control is not available on a per-signal basis, but instead a per-package (4 signal) basis. The exception is P5_Glb_16, which is on its own package. The terminators and pull-down resistors are also installed on a per-package (4 signal) basis. When these packages have their outputs disabled, regardless of the selected direction, the TTL side becomes tri-stated and the ECL side becomes cut-off. .----------. .-------------. On Card | | | | Use of the Front <>-----| |----<>----| Board | Board Global Panel | | | Support | I/O Signals <>-----| E T |----<>----| Functions | P5 | C T | | FPGA |-------<> Global <>-----| L L |----<>----| | I/O | | | | via e.g. the Signal <>-----| |----<>----| processes | Board Global Connector | | | P5_IO and | Signal Array | OE DIR | | maps to | Lines `----------' | Board | | | Direction | Global | | `-------<-----| Signals | | Output Enable | | `------------<-----| | `-------------' The pinout of the 34 pin Board Global I/O Signal Connector is the following: Odd numbered pins carry the non-inverted signal of a differential pair. The next higher even numbered pin carries the inverted signal of the pair. Signal P5_Glb_00 is on pins number 1 and 2, P5_Glb_16 is on pins number 33 and 34. 7. Monitor Data Capture and Readout ----------------------------------- The event readout and monitor readout for the Run II Frameworks will differ in a number of ways from the Run I setup. The Run II Framework Data Block will be smaller than it was in Run I. In Run II, the Trigger Control Computer (TCC) will not depend on a Data Block Spy in order to get its monitor data. In the Run II Frameworks, TCC will access all of its Monitor Data via VME reads to THE Cards. The design of THE Card provides for two types of readout: the High Speed readout of event data into the SAR and the readout of Monitor Data into the TCC. A rule used in the design of all of the FPGA's used in THE Card is: Any data that is readout into the event Data Block via the High Speed readout path also needs to be available for readout via the Monitor Data read path. This does not mean that the Monitor Data path needs to be able to keep up with the High Speed readout path; it just means that on selected events the data that is readout via the High Speed path needs to be captured so that it can be accessed by TCC via the Monitor Data path. We do not want to be restricted to only being able to obtain Monitor Data when events are flowing, so there is also a mechanism for capturing Monitor Data during any 132 nsec period randomly selected by TCC. Monitor Data is not restricted to just being a copy of what is readout in the High Speed event path. Many items will be available via Monitor Data readout only. But, any item that is available via High Speed readout has to be available via Monitor Data Readout. The Monitor Data readout path works in the following way. Via one of two methods, TCC causes the Monitor Data readout path to "capture" fresh Monitor Data. Once the Monitor Data path has completed this capture operation then this set of Monitor Data is available for TCC to read via VME read cycles. This set of Monitor Data will remain visible by reading THE Cards until the Monitor Data path is told to capture a new set of Monitor Data. A given piece of Monitor Data may be read via VME cycles multiple times if desired. In the design of the various FPGA's used in THE Card it is assumed that appropriate history FIFO buffering will be placed in front of the registers that actually capture the Monitor Data so that all Monitor Data is contemporary (or is shifted from contemporary in an appropriate way). As mentioned above, TCC has two ways to stimulate the Monitor Data path to capture a new set of Monitor Data. 1. The first method is for TCC to issue an instruction that will immediately cause the Monitor Data path to capture new information. Once TCC issues this instruction, then during the next available complete 132 nsec period, the Monitor Data path will capture new data. 2. The second method is for TCC to issue an instruction that during the next available 132 nsec period, that contains an L1 Accept, the Monitor Data path is to capture new information. In this case TCC is informed as soon as the L1 Accept and the capture operation have taken place. These two methods of capturing Monitor Data are indicated in the drawing below. Most likely a P1 Timing Signal will be used to cause the first type of Monitor Data capture operation. A separate P1 Timing Signal together with a signal from the High Speed readout section on THE Card will be used to initiate the second type of Monitor Data capture operation. +------------+ | | High Speed +---------->| High Speed |-----> Readout Data | | Readout | | | | Data | +------------+ Source >-----+ A | | +------------+ | | Monitor | +---------->| Data |----------------------> | Readout | +------------+ | VME Access to +---------------+ the Captured | Monitor Data | +------------+ | Data | Monitor | | Source >---------------->| Data |----------------------> B | Readout | | +------------+ | | | +---------------+ Capture TCC Initiated | Clock P1 Timing Signal for +------+ | Immediate Capture >---------------| | | of Monitor Data | OR |---+ +---| | | +------+ TCC Initiated | P1 Timing Signal to +---------------+ Enable Capture of | Monitor Data on the >-------+ +-------+ | next L1 Accept +------| | | | AND |----+ Signal from High +------| | Speed Readout >-------+ +-------+ Indicating an L1 Accept As shown in the sketch above, Data source A, provides its data to both the L1 event Data Block readout and to the Monitor Data path, while Data source B feeds only the Monitor Data path. In the real implementation the system will be considerably more complicated to guarantee that it captures data from a complete 132 nsec period independent of when TCC request new Monitor Data and independent of when the L1 Accept occurs. 8. The High Speed Readout Section --------------------------------- Some version of THE Card will have a High Speed Readout section for sending event data to a SAR module. This High Speed Readout section will operate at the full 10 kHz L1 Accept rate. The buffers that hold events that are awaiting their L2 decisions are in the SAR modules. Dedicated busses will be used to bring event data out of the Main Signal Processing Array and feed it to the High Speed Readout Section. In order to feed the High Speed Readout, logic in the Main Signal Processing Array will have to provide the following functions: 1. A history FIFO buffer so that event data from the proper 132 nsec period is saved for event readout when there is an L1 Accept. 2. A capture register so that the data from the proper slice of the history FIFO can be pulled out and saved until it is actually passed to the High Speed Readout. 3. A data selection engine which, when there is an L1 Accept, will move in the proper sequence all of the event data that has been captured in the Main Signal Processing Array, to the High Speed Readout. There is a limit to how much event data one can deliver to a port on the SAR. The hard limit is the size of a buffer slot on the SAR which is 2.4k bytes. A softer limit is the transfer time required to move the event data from THE Card into an SAR port. If this is to be held to 7 usec (which is thought to match the Silicon Vertex readout performance) then the maximum event size that can be transferred is about 7 usec x 850 Mbits/sec or 745 bytes or 186 longwords. However, in order to move this much data per event through the High Speed Readout, the FPGA's in the Main Signal Processing Array would have to deliver a new 16 bit quantity to the High Speed Readout once every 18.8 nsec. This would be very hard to do over the relatively long bus type traces that will connect the Main Signal Processing Array to the High Speed Readout. Having multiple FPGA's that need to drive this bus will also slow thing down. But fortunately most of THE Cards that need to provide event data to the Data Block have much less then 745 bytes. Thus, they can delivery their data more slowly from the Main Signal Processing Array to the High Speed Readout section. THE Cards with the most data will be the scaler cards that need to readout to the Data Block. Even if these cards have 64 scalers of 32 bit length this is only 256 bytes of event data. Transporting 16 bits at a time one could have 55 nsec between transfers and still deliver all the data in 7 usec. 9. The Board Support Functions FPGA (BSF FPGA) ----------------------------------------------- The Board Support Function FPGA provides the logic to perform the following functions: 1. As described above, the BSF FPGA processes the P1 Timing Lines to generate the High Quality Array Timing Lines. 2. As described above, the BSF FPGA controls the direction of the P5 Global IO lines and processes these signals in a fashion customized to the particular species of THE Card. These processed I/O signals are typically distributed via the Board Global Signal Array lines. 3. The BSF FPGA provides the logic to facilitate the High Speed Readout function. Principally this logic transports the event data out of the Main Signal Processing Array and delivers it to the High Speed Readout in the proper order. We may also use the BSF FPGA to provide other specialized functions that are unique to a given instance of THE Card. It could also be used to drive front panel LED's if these are made part of THE Card. The Board Support Function FPGA also receives the following On Card Bus signals: 16 data lines, 9 address lines, direction and strobe control lines, an FPGA output enable signal, and radial FPGA chip select, chip status, configure chip, and chip configured signals. 10. The JTAG Scan Path ---------------------- THE Card will have a single JTAG Scan Path. This JTAG Scan Path will be used primarily for diagnosing problems which may appear during normal running of THE Card. It is not intended that use of JTAG is required for any of the normal functioning of THE Card, and in fact the non-trivial software which is required to support JTAG will most likely be developed relatively late in the project. Each THE Card has a Texas Instruments 74ACT8990 JTAG Scan Path Controller chip which may be accessed via VME. The JTAG Scan Path will include the following targets: - all 16 Main Signal Array FPGA's - the Board Support Function FPGA It will NOT include the VME Interface FPGA. This is simply because one cannot reliably diagnose a misfunctioning VME Interface FPGA via VME accesses. In addition to VME accesses of the 74ACT8990's internal registers, 3 connections between this chip and the Board Condition Status Register of THE Card are provided: - JTAG_Controller_Enable: this signal, driven by the VMEIF, enables/ disables all output and bi-directional pins on the 74ACT8990. - JTAG_Test_Logic_Activate: this signal, driven by the VMEIF, instructs the 74ACT8990 to take all devices in its Scan Path into or out of the Test-Logic-Reset state. This signal is subordinate to the JTAG_Controller_Enable signal. - JTAG_RDY*: this signal, driven by the 74ACT8990, indicates that it is ready to be written to or read from via VME. By using the JTAG_Controller_Enable and JTAG_Test_Logic_Activate signals, the Scan Path circuitry on THE Card can easily be put into a known benign state. This functionality is necessary until the serious JTAG support software is available. The 74ACT8990 is only available as a 5V part. This is the only 5V CMOS part on THE Card, and there are compatibility issues between this part and the other 5V TTL and 3V CMOS components on THE Card. We use 3V CMOS logic parts from IDT to solve these problems. The 3V/5V compatibility matrix is below: Xilinx IDT Load: 5V TTL 5V CMOS 3V CMOS 3V CMOS ------ ------- ------- ------- Source: 5V TTL YES NO (1) YES (2) YES 5V CMOS YES YES NO (3) YES 3V CMOS YES NO (1) YES YES (Xilinx or IDT) Notes: (1) data is unreliable but no damage occurs to load (2) if 5V TTL Voh <= 3.7 V (3) Xilinx inputs can be damaged in this configuration 11. Block Diagram of THE Card ---------------------------- Rear Connectors Front Panel --------------- ----------- P1 Timing Signals >-----------------------------------+ | P1 +-----------+ +---------------+ P5 | VME | | Board Support |<>----------<> Global >-----| Interface |---------+ | Function FPGA | I/O VME | FPGA | | +---------------+ Signals Bus +-----------+ | | ^ 17 | Hi v Configuration Data | Quality | Board Global Monitor Data | Array | I/O Signal Trigger Setup Data | Timing | Array Lines ^ | ^ V V V P4 P2 & P3 +------------------------+ Main Main |\ | PROGRAMMABLE LOGIC | |\ Array Array >----| >--------| 16 chips with |--------| >----> Signal Signal |/ | 192 I/O's and 1000 | |/ Output Inputs | CLB's each | 64 128 +------------------------+ | | V +----------------+ Event | High Speed |-------------------> Readout | Readout Driver | to the +----------------+ SAR 12. Detailed listing of P1, P2, P3, P4, P5 connector pin assignments -------------------------------------------------------------------- ========================= P1 Rear Panel Connector ========================= Pins Signal Function ------------------------------------------------------------------- Pin Row Row Row Row Row Number A B C D E ------ ----------- ----------- ----------- ----------- ----------- 1 TS_00_Inv TS_00_NonInv GND TS_08_Inv TS_08_NonInv 2 GND GND GND GND GND 3 TS_01_Inv TS_01_NonInv GND TS_09_Inv TS_09_NonInv 4 TS_02_Inv TS_02_NonInv GND TS_10_Inv TS_10_NonInv 5 TS_03_Inv TS_03_NonInv GND TS_11_Inv TS_11_NonInv 6 TS_04_Inv TS_04_NonInv GND TS_12_Inv TS_12_NonInv 7 TS_05_Inv TS_05_NonInv GND TS_13_Inv TS_13_NonInv 8 TS_06_Inv TS_06_NonInv GND TS_14_Inv TS_14_NonInv 9 TS_07_Inv TS_07_NonInv GND TS_15_Inv TS_15_NonInv 10 GND GND GND GND GND 11 Data_00 BBSY* Data_08 Data_01 BCLR* 12 Data_09 Data_02 GND ACFAIL* GND 13 Data_10 Data_03 BG0IN* Data_11 Data_04 14 BG0OUT* Data_12 Data_05 BG1IN* Data_13 15 Data_06 BG1OUT* Data_14 Data_07 BG2IN* 16 Data_15 BG2OUT* SYSCLK BG3IN* SYSFAIL* 17 BG3OUT* BERR* GND DS1* GND 18 BR0* GND SYSRESET* GND DS0* 19 BR1* LWORD* GND WRITE* GND 20 BR2* GND AM5 BR3* Adrs_23 21 GND DTACK* GND AM0 Adrs_22 22 AM1 GND AS* GND Adrs_21 23 AM2 Adrs_20 AM3 Adrs_19 IACK* 24 Adrs_18 IACKIN* SERCLK Adrs_17 IACKOUT* 25 SERDAT* Adrs_16 AM4 Adrs_15 Adrs_07 26 IRQ7* Adrs_14 Adrs_06 IRQ6* Adrs_13 27 Adrs_05 IRQ5* Adrs_12 Adrs_04 IRQ4* 28 Adrs_11 Adrs_03 IRQ3* Adrs_10 Adrs_02 29 IRQ2* Adrs_09 Adrs_01 IRQ1* Adrs_08 30 GND GND GND GND GND 31 -2V -12V +5V STDBY +12V -4.5V 32 -2V +5V +5V +5V -4.5V ------ ----------- ----------- ----------- ----------- ----------- Pin A B C D E Number Row Row Row Row Row ========================= P2 Rear Panel Connector ========================= Pins Signal Function --------------------------------------------------------------------- Pin Row Row Row Row Row Num A B C D E --- ------------ ------------- ------- ------------ ------------- 1 MSA_In_000_I MSA_In_000_NI GROUND MSA_In_032_I MSA_In_032_NI 2 MSA_In_001_I MSA_In_001_NI +3.3V U MSA_In_033_I MSA_In_033_NI 3 MSA_In_002_I MSA_In_002_NI GROUND MSA_In_034_I MSA_In_034_NI 4 MSA_In_003_I MSA_In_003_NI +3.3V U MSA_In_035_I MSA_In_035_NI 5 MSA_In_004_I MSA_In_004_NI -2.0V U MSA_In_036_I MSA_In_036_NI 6 MSA_In_005_I MSA_In_005_NI GROUND MSA_In_037_I MSA_In_037_NI 7 MSA_In_006_I MSA_In_006_NI +3.3V U MSA_In_038_I MSA_In_038_NI 8 MSA_In_007_I MSA_In_007_NI GROUND MSA_In_039_I MSA_In_039_NI 9 MSA_In_008_I MSA_In_008_NI +5.0V U MSA_In_040_I MSA_In_040_NI 10 MSA_In_009_I MSA_In_009_NI GROUND MSA_In_041_I MSA_In_041_NI 11 MSA_In_010_I MSA_In_010_NI +3.3V U MSA_In_042_I MSA_In_042_NI 12 MSA_In_011_I MSA_In_011_NI GROUND MSA_In_043_I MSA_In_043_NI 13 MSA_In_012_I MSA_In_012_NI +3.3V U MSA_In_044_I MSA_In_044_NI 14 MSA_In_013_I MSA_In_013_NI GROUND MSA_In_045_I MSA_In_045_NI 15 MSA_In_014_I MSA_In_014_NI -2.0V U MSA_In_046_I MSA_In_046_NI 16 MSA_In_015_I MSA_In_015_NI GROUND MSA_In_047_I MSA_In_047_NI 17 MSA_In_016_I MSA_In_016_NI +3.3V U MSA_In_048_I MSA_In_048_NI 18 MSA_In_017_I MSA_In_017_NI GROUND MSA_In_049_I MSA_In_049_NI 19 MSA_In_018_I MSA_In_018_NI +5.0V U MSA_In_050_I MSA_In_050_NI 20 MSA_In_019_I MSA_In_019_NI +3.3V U MSA_In_051_I MSA_In_051_NI 21 MSA_In_020_I MSA_In_020_NI GROUND MSA_In_052_I MSA_In_052_NI 22 MSA_In_021_I MSA_In_021_NI +3.3V U MSA_In_053_I MSA_In_053_NI 23 MSA_In_022_I MSA_In_022_NI GROUND MSA_In_054_I MSA_In_054_NI 24 MSA_In_023_I MSA_In_023_NI -2.0V U MSA_In_055_I MSA_In_055_NI 25 MSA_In_024_I MSA_In_024_NI GROUND MSA_In_056_I MSA_In_056_NI 26 MSA_In_025_I MSA_In_025_NI +3.3V U MSA_In_057_I MSA_In_057_NI 27 MSA_In_026_I MSA_In_026_NI GROUND MSA_In_058_I MSA_In_058_NI 28 MSA_In_027_I MSA_In_027_NI +5.0V U MSA_In_059_I MSA_In_059_NI 29 MSA_In_028_I MSA_In_028_NI +3.3V U MSA_In_060_I MSA_In_060_NI 30 MSA_In_029_I MSA_In_029_NI GROUND MSA_In_061_I MSA_In_061_NI 31 MSA_In_030_I MSA_In_030_NI +3.3V U MSA_In_062_I MSA_In_062_NI 32 MSA_In_031_I MSA_In_031_NI GROUND MSA_In_063_I MSA_In_063_NI --- ------------ ------------- ------- ------------ ------------- Pin A B C D E Num Row Row Row Row Row ========================= P3 Rear Panel Connector ========================= Pins Signal Function --------------------------------------------------------------------- Pin Row Row Row Row Row Num A B C D E --- ------------ ------------- ------- ------------ ------------- 1 MSA_In_064_I MSA_In_064_NI GROUND MSA_In_096_I MSA_In_096_NI 2 MSA_In_065_I MSA_In_065_NI +3.3V L MSA_In_097_I MSA_In_097_NI 3 MSA_In_066_I MSA_In_066_NI GROUND MSA_In_098_I MSA_In_098_NI 4 MSA_In_067_I MSA_In_067_NI +3.3V L MSA_In_099_I MSA_In_099_NI 5 MSA_In_068_I MSA_In_068_NI -4.5V L MSA_In_100_I MSA_In_100_NI 6 MSA_In_069_I MSA_In_069_NI GROUND MSA_In_101_I MSA_In_101_NI 7 MSA_In_070_I MSA_In_070_NI +3.3V L MSA_In_102_I MSA_In_102_NI 8 MSA_In_071_I MSA_In_071_NI GROUND MSA_In_103_I MSA_In_103_NI 9 MSA_In_072_I MSA_In_072_NI +5.0V L MSA_In_104_I MSA_In_104_NI 10 MSA_In_073_I MSA_In_073_NI GROUND MSA_In_105_I MSA_In_105_NI 11 MSA_In_074_I MSA_In_074_NI +3.3V L MSA_In_106_I MSA_In_106_NI 12 MSA_In_075_I MSA_In_075_NI GROUND MSA_In_107_I MSA_In_107_NI 13 MSA_In_076_I MSA_In_076_NI +3.3V L MSA_In_108_I MSA_In_108_NI 14 MSA_In_077_I MSA_In_077_NI GROUND MSA_In_109_I MSA_In_109_NI 15 MSA_In_078_I MSA_In_078_NI -4.5V L MSA_In_110_I MSA_In_110_NI 16 MSA_In_079_I MSA_In_079_NI GROUND MSA_In_111_I MSA_In_111_NI 17 MSA_In_080_I MSA_In_080_NI +3.3V L MSA_In_112_I MSA_In_112_NI 18 MSA_In_081_I MSA_In_081_NI GROUND MSA_In_113_I MSA_In_113_NI 19 MSA_In_082_I MSA_In_082_NI +5.0V L MSA_In_114_I MSA_In_114_NI 20 MSA_In_083_I MSA_In_083_NI +3.3V L MSA_In_115_I MSA_In_115_NI 21 MSA_In_084_I MSA_In_084_NI GROUND MSA_In_116_I MSA_In_116_NI 22 MSA_In_085_I MSA_In_085_NI +3.3V L MSA_In_117_I MSA_In_117_NI 23 MSA_In_086_I MSA_In_086_NI GROUND MSA_In_118_I MSA_In_118_NI 24 MSA_In_087_I MSA_In_087_NI -4.5V L MSA_In_119_I MSA_In_119_NI 25 MSA_In_088_I MSA_In_088_NI GROUND MSA_In_120_I MSA_In_120_NI 26 MSA_In_089_I MSA_In_089_NI +3.3V L MSA_In_121_I MSA_In_121_NI 27 MSA_In_090_I MSA_In_090_NI GROUND MSA_In_122_I MSA_In_122_NI 28 MSA_In_091_I MSA_In_091_NI +5.0V L MSA_In_123_I MSA_In_123_NI 29 MSA_In_092_I MSA_In_092_NI +3.3V L MSA_In_124_I MSA_In_124_NI 30 MSA_In_093_I MSA_In_093_NI GROUND MSA_In_125_I MSA_In_125_NI 31 MSA_In_094_I MSA_In_094_NI +3.3V L MSA_In_126_I MSA_In_126_NI 32 MSA_In_095_I MSA_In_095_NI GROUND MSA_In_127_I MSA_In_127_NI --- ------------ ------------- ------- ------------ ------------- Pin A B C D E Num Row Row Row Row Row ========================== P4 Front Panel Connector ========================== Pins Signal Function --------------------------------------------------------------------- Pin Row Row Row Row Row Num A B C D E --- ------------- ------------ ------- ------------- ------------ 1 MSA_Out_63_NI MSA_Out_63_I GROUND MSA_Out_31_NI MSA_Out_31_I 2 MSA_Out_62_NI MSA_Out_62_I +5.0 V MSA_Out_30_NI MSA_Out_30_I 3 MSA_Out_61_NI MSA_Out_61_I GROUND MSA_Out_29_NI MSA_Out_29_I 4 MSA_Out_60_NI MSA_Out_60_I GROUND MSA_Out_28_NI MSA_Out_28_I 5 MSA_Out_59_NI MSA_Out_59_I GROUND MSA_Out_27_NI MSA_Out_27_I 6 MSA_Out_58_NI MSA_Out_58_I +3.3 V MSA_Out_26_NI MSA_Out_26_I 7 MSA_Out_57_NI MSA_Out_57_I GROUND MSA_Out_25_NI MSA_Out_25_I 8 MSA_Out_56_NI MSA_Out_56_I GROUND MSA_Out_24_NI MSA_Out_24_I 9 MSA_Out_55_NI MSA_Out_55_I GROUND MSA_Out_23_NI MSA_Out_23_I 10 MSA_Out_54_NI MSA_Out_54_I -2.0 V MSA_Out_22_NI MSA_Out_22_I 11 MSA_Out_53_NI MSA_Out_53_I GROUND MSA_Out_21_NI MSA_Out_21_I 12 MSA_Out_52_NI MSA_Out_52_I GROUND MSA_Out_20_NI MSA_Out_20_I 13 MSA_Out_51_NI MSA_Out_51_I GROUND MSA_Out_19_NI MSA_Out_19_I 14 MSA_Out_50_NI MSA_Out_50_I -4.5 V MSA_Out_18_NI MSA_Out_18_I 15 MSA_Out_49_NI MSA_Out_49_I GROUND MSA_Out_17_NI MSA_Out_17_I 16 MSA_Out_48_NI MSA_Out_48_I GROUND MSA_Out_16_NI MSA_Out_16_I 17 MSA_Out_47_NI MSA_Out_47_I GROUND MSA_Out_15_NI MSA_Out_15_I 18 MSA_Out_46_NI MSA_Out_46_I GROUND MSA_Out_14_NI MSA_Out_14_I 19 MSA_Out_45_NI MSA_Out_45_I +5.0 V MSA_Out_13_NI MSA_Out_13_I 20 MSA_Out_44_NI MSA_Out_44_I GROUND MSA_Out_12_NI MSA_Out_12_I 21 MSA_Out_43_NI MSA_Out_43_I GROUND MSA_Out_11_NI MSA_Out_11_I 22 MSA_Out_42_NI MSA_Out_42_I GROUND MSA_Out_10_NI MSA_Out_10_I 23 MSA_Out_41_NI MSA_Out_41_I +3.3 V MSA_Out_09_NI MSA_Out_09_I 24 MSA_Out_40_NI MSA_Out_40_I GROUND MSA_Out_08_NI MSA_Out_08_I 25 MSA_Out_39_NI MSA_Out_39_I GROUND MSA_Out_07_NI MSA_Out_07_I 26 MSA_Out_38_NI MSA_Out_38_I GROUND MSA_Out_06_NI MSA_Out_06_I 27 MSA_Out_37_NI MSA_Out_37_I -2.0 V MSA_Out_05_NI MSA_Out_05_I 28 MSA_Out_36_NI MSA_Out_36_I GROUND MSA_Out_04_NI MSA_Out_04_I 29 MSA_Out_35_NI MSA_Out_35_I GROUND MSA_Out_03_NI MSA_Out_03_I 30 MSA_Out_34_NI MSA_Out_34_I GROUND MSA_Out_02_NI MSA_Out_02_I 31 MSA_Out_33_NI MSA_Out_33_I -4.5 V MSA_Out_01_NI MSA_Out_01_I 32 MSA_Out_32_NI MSA_Out_32_I GROUND MSA_Out_00_NI MSA_Out_00_I --- ------------- ------------ ------- ------------- ------------ Pin A B C D E Num Row Row Row Row Row ========================== P5 Front Panel Connector ========================== Pin Number Signal Name ------ ----------- 1 P5_Glb_00_Ninv 2 P5_Glb_00_Inv 3 P5_Glb_01_Ninv 4 P5_Glb_01_Inv 5 P5_Glb_02_Ninv 6 P5_Glb_02_Inv 7 P5_Glb_03_Ninv 8 P5_Glb_03_Inv 9 P5_Glb_04_Ninv 10 P5_Glb_04_Inv 11 P5_Glb_05_Ninv 12 P5_Glb_05_Inv 13 P5_Glb_06_Ninv 14 P5_Glb_06_Inv 15 P5_Glb_07_Ninv 16 P5_Glb_07_Inv 17 P5_Glb_08_Ninv 18 P5_Glb_08_Inv 19 P5_Glb_09_Ninv 20 P5_Glb_09_Inv 21 P5_Glb_10_Ninv 22 P5_Glb_10_Inv 23 P5_Glb_11_Ninv 24 P5_Glb_11_Inv 25 P5_Glb_12_Ninv 26 P5_Glb_12_Inv 27 P5_Glb_13_Ninv 28 P5_Glb_13_Inv 29 P5_Glb_14_Ninv 30 P5_Glb_14_Inv 31 P5_Glb_15_Ninv 32 P5_Glb_15_Inv 33 P5_Glb_16_Ninv 13. Notes about FPGA IOB usage/configuration -------------------------------------------- In the XC4k series FPGAs, any IOB which is configured as an INPUT (or INOUT) must be either always driven from an external source, or must be internally configured with a pullup resistor. Specific examples are: VMEIF FPGA Chip_Status*(n) and Chip_Configed*(n): on the Foundation Module, these signals are only driven for n = 1, 4, 13, 16. ALL of these signals have internal pullup resistors BSF FPGA P5_Global_IO(16:0) and Board_Global_IO(16:0): these signals are INOUT, and their usage is not currently understood well enough to rule out use of pullup resistors. Some HSRO signals may require pullup resistors, as the details of HSRO are understood better. Before and during configuration, all I/O's NOT used for configuration are configured as inputs with weak pull-up resistors. The GTS signal is NOT operational at this time. The I/O's which ARE used for configuration must be carefully allocated to minimize interference between the "normal" and "configuration" uses of these pins. Each of these pins is discussed below for each of the 3 "types" of FPGA's (VMEIF, MSA, and BSF): CCLK: outputs configuration clock in all Master modes and Asynch. Periph. Mode, not available as user I/O. VMEIF: drives XC17256L CLK pin. BSF/MSA: open, not used during configuration DONE: I/O, optional internal pullup. As output, HIGH indicates completion of configuration, as input, LOW delays global logic initialization. Not available as user I/O. VMEIF: drives XC17256L CE pin, internal pullup enabled. BSF/MSA: drives Chip_Configed(n) to VMEIF, internal pullup enabled (note VMEIF also has internal pullup enabled on the receiving end of this line). PROGRAM*: active low input, rising edge initiates program cycle, weak pullup ALWAYS present. Not available as user I/O. VMEIF: driven by VME ACFAIL*. BSF/MSA: driven by Config_Chip*(n) from VMEIF. RCLK+RDY/BUSY*: output, in Peripheral mode indicates when it is appropriate to write another byte (RDY/BUSY*). RCLK function not used in modes of interest to us. Optional pullup/pulldown resistors. VMEIF: open. BSF/MSA: drives Chip_Status*(n) to VMEIF (note VMEIF has internal pullup enabled on the receiving end of this line). M0,M1,M2: inputs, indicate configuration mode to use, optional pullup/pulldown resistors. VMEIF: all tied low, not used after configuration BSF/MSA: M0, M2 tied high, M1 tied low, not used after configuration. TDO: output, JTAG Test Data Output, optional pullup/pulldown resistor. VMEIF: JTAG not used, this pin is open and unused after configuration. BSF/MSA: driven to TDI input of "next" FPGA in JTAG Scan Chain both during and after configuration. TDI: input, JTAG Test Data Input. VMEIF: JTAG not used, this pin is user I/O (VME A23) after configuration. BSF/MSA: driven by TDO output of "previous" FPGA in JTAG Scan Chain both during and after configuration. TCK: input, JTAG Test Clock. VMEIF: JTAG not used, this pin is user I/O (VME LWORD*) after configuration. BSF/MSA: driven by TCK output of 8990 both during and after configuration. TMS: input, JTAG Test Mode Select. VMEIF: JTAG not used, this pin is user I/O (VME D5) after configuration. BSF/MSA: driven by TMS output of 8990 both during and after configuration. HDC: output, high during configuration. VMEIF: not used during configuration, user I/O (Config_Chip*(17)) after configuration. The high level before and during configuration is harmless on this line. BSF/MSA: not used during configuration, user I/O (HSRO Token Out* to "next" FPGA in HSRO Chain) after configuration. The high level before and during configuration is used to force the INIT* pin (to which HSRO_Token_In* is assigned) on the "next" FPGA in the HSRO Chain high as it should be. LDC*: output, low during configuration. VMEIF: not used during configuration, open and unused after configuration. BSF: not used during configuration, user I/O (Board_Global_IO(3)) after configuration. No MSA FPGA should attempt to drive Board_Global_IO(3) high until the BSF FPGA is configured--this can be accomplished using MSA_FPGA_OE*. MSA: not used during configuration, open and unused after configuration. ERR+INIT*: I/O, as active-low input can hold FPGA in WAIT state before configuration, as active-low open-drain output indicates configuration error (we do not have access to this signal via VME). External 1k-10k pullup resistor recommended (but not present on FM since line held high by external source). Note open-drain output low state (indicating configuration error) will NOT conflict with the externally supplied logic high on INIT*. VMEIF: drives XC17256L OE pin (note: XC17256L must be configured with "low reset option" which is NOT the default), not used after configuration. Note '94 data book does not show pullup resistor on INIT* in Master Serial Mode, '96 book does. Again, we do not have this resistor. BSF/MSA: driven by HSRO_Token_In* from "previous" FPGA in HSRO chain. This signal will either be driven high or weakly pulled high by the driving end, depending on whether (and how) the previous FPGA has been configured (see HDC* above). PGCK1-4: input, Primary Global Clock 1-4. VMEIF: PGCK1 only used as global clock, others used as user I/O. BSF: all 4 used for P1_TS inputs, which may or may not be routed on global clock nets. MSA: all 4 used for HQ_TS inputs, which may or may not be routed on global clock nets. SGCK1-4: input, Secondary Global Clock 1-4. VMEIF: used as user I/O only. SGCK4 (doubling as DOUT, which cycles high/low during configuration) not used. BSF: all 4 used for P1_TS inputs, which may or may not be routed on global clock nets. Note potential conflict during config with SGCK4 (DOUT), there is only a small resistor between DOUT and P1_TS bipolar driver. MSA: All 4 used as user I/O. SGCK4 (DOUT) drives HSRO_Data(0), no other FPGA should attempt to drive this signal during configuration (achieved by disabling all FPGA outputs during configuration). CS0*: input, active-low Chip Select 0 (used in Asynch. Periph. Mode). VMEIF: not used during configuration, user I/O (Chip_Status*(15)) after configuration. BSF/MSA: driven by Chip_Select*(n) during and after configuration. CS1: input, active-high Chip Select 1 (used in Asynch Periph. Mode). VMEIF: not used during configuration, open and unused after configuration. BSF: driven by BSF_FPGA_OE* during and after configuration, used as GTS after configuration, must be driven high during configuration. MSA: driven by MSA_FPGA_OE* during and after configuration, used as GTS after configuration, must be driven high during configuration. WS*: input, active-low Write Strobe (used in Asynch Periph. Mode). VMEIF: not used during configuration, open and unused after configuration. BSF/MSA: driven by Write_Strobe* during and after configuration. RS: input, active-high Read Strobe (used in Asynch Periph. Mode), should not be driven high while WS* is driven low. VMEIF: not used during configuration, user I/O (Chip_Select*(18)) after configuration. BSF/MSA: not used during configuration, user I/O (HSRO_Data(10) after configuration. Will be weakly pulled high by the driving end. A0-A17: input, not used in the configuration modes of interest to us. VMEIF/BSF/MSA: User I/O after configuration. D0-D7: input, data in Asynch. Periph. Mode. VMEIF: not used during configuration, user I/O after configuration. BSF/MSA: driven by OCB_Data(7:0) during and after config. =.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.=.= The original version of this document follows: "THE" Card -------------------------------------------------- Rev. 27-JUN-1995 Can one build the new Frameworks from just one type of card? Different programming would be used for the logic on different instances of this card to implement the required various functions. Another more probable idea is to have multiple types of cards differing only in the traces in the FPGA section, providing different internal interconnection structures. The peripheral ring of the different flavors of "THE" card would remain constant (except perhaps for the addition or deletion of the fiber interface to the SAR). General Description ------------------- This card will have the following 6 major sections: 1. Interface to a control-download monitor interface. This is most likely either CBus or else VME (D8, D16, A16, A24). 2. A board "support function" block. This would contain such things as a load PROM's for the programmable logic, receiving and fanout of a set of master clock signals, and LEMO connectors to monitor important signals. 3. Input signal receiver section. 128 differential ECL signals are received from the J2 and J3 backplane connectors. These are 5 row connectors where the center row is used for power and ground and the outer two rows on each side are used for differential signals. In addition to this, up to 16 differential ECL global signals are received on the 5th front panel 34 pin connector. All received signals are provided with termination resistors and may have diode protection and spreader resistors as well. termination resistors. 4. Output signal driver section. This consists of 64 differential ECL drivers and the associated 4 connectors on the front panel (34 pin connectors). There may be one or two more special "global" output signals that exit the card via the 5th front panel 34 pin connector. 5. High Speed Optical event data output driver. This can send out about 400 bytes per event in the time available (assumed to be 4 microseconds). 6. Programmable Logic section. This consists of a number of field programmable logic I.C.'s and their associated wiring. Front and rear panel description -------------------------------- "THE" card is a 9U x 400 mm board with J1, J2, J3 connectors i.e. 400 mm x 400 mm or 160000 sq mm of board area. J1 supports either VME (D8, D16, A16, A24) or else CBus. J1 also brings a small amount of +5 Volt power on card. VSB and VME D32, A32 are not supported. All of J2 and J3 are user defined. Both J2 and J3 are 5 layer DIN connectors. J2 and J3 are used for power, ground, and Input signals. The center layer on each of these connectors is used for power - ground and the other 4 layers on each connector are used to receive a total of 128 differential user signals. The front panel has 5 34 pin flat cable connectors. These take a total of 320 mm of vertical front panel space. In the remaining 60 mm of front panel one could fit perhaps 4 LEMO connectors for scope monitoring of important signals (8 mm per LEMO) and perhaps 4 LED's at 2.54 mm per LED. This leaves 10 mm at the top of the printed circuit board and 10 mm at the bottom of the PCB that are free of front panel components. ***NEED ROOM FOR FIBER CONNECTORS---THESE SHOULD BE ACESSABLE (E.G. ON FRONT PANEL)*** How big is the laser module? Board Area Estimates -------------------- Estimate the board area required to drive the 64 differential signals off card. This will require 11 of the 100324 differential drivers. These are in 28 pin PCC packages which require 160 sq mm each. For 11 chips this requires 1,760 sq mm. Let's double this to have room for bypass caps and traces which gives ---> 3,600 sq mm for the differential line drivers. Now to this add the space required for the protection diodes and the pull down resistors. Estimate this at 0.1" vertical x 0.4" depth per signal (the depth is for 2 diode strips and 2 pull down strips) which is 26 sq mm per signal or a total of 1,700 sq mm for diode protection and pull down resistors. Note that the protection diodes are really only needed when we talk to "the world" and thus may be more sensibly included in patch panels rather than on the card. This gives a total area of ---> 5,300 sq mm to driver 64 signals off card. Estimate the board area required to receive 144 differential signals (128 logic term inputs and 16 master clock and global logic inputs). This will require 26 of the 100325 differential receivers. These are in 28 pin PCC packages which require 160 sq mm each. For 26 chips this requires 4,160 sq mm. Let's double this to have room for bypass caps and traces which gives 8,500 sq mm for the differential receivers. Now to this add the space required for the diode protection and the input terminator. Estimate this at 0.1" vertical x 0.4" depth per signal (the depth is for 2 diode strips and 2 terminator strips) which is 26 sq mm per signal or a total of 3,800 sq mm for diode protection and terminators. Note that no spreader resistors are included here. Note also that the protection diodes may be included in patch panels. Note also that both 100325 and also 10H125 receivers claim that the outputs go LOW when the inputs are left floating, i.e. the spreader resistors are not needed to force a TTL low out of these parts when the inputs are left unconnected. This gives a total area of ---> 12,300 sq mm to receive the 80 differential signals. Estimate the board area required for the J1, J2, and J3 connectors. This will require a 0.6" vertical strip along the entire height at the back of the card. This considers the cards mounted vertically as in a normal 9U VME card file. Thus 16 mm x 400 mm ---> 6,400 sq mm for J1, J2, J3 connectors. Estimate the board area required for the front panel 34 pin connectors, LEMO connectors and LED's. This is about 15mm x 400 mm or about ---> 6,000 sq mm for the front panel components. Estimate the board area required for the CBus or else the VME bus I/O area. I estimate this at 10,000 sq mm. This is taken from looking at Run 1 cards. Let's add double this to include space for "service functions" like configuration PROMs and master clock fanout. This gives ---> 20,000 sq mm for control bus interface and service functions. Estimate the board area required for the high speed optical driver output. This is a pure estimate based on the size of a HP chip, one programmable logic chip and a laser module. 4,000 sq mm for the high speed optical driver. Estimate the board area required around the top and bottom perimeter of the board. Use a 10 mm perimeter. 10 mm x 800 mm ---> 8,000 sq mm for perimeter space. 5,300 sq mm for drivers 12,300 sq mm for receivers 6,400 sq mm for J1, J2, J3 connectors 6,000 sq mm for front panel connectors, LEMO's and LED's 20,000 sq mm for control bus interface and service functions 4,000 sq mm for high speed optical link driver + 8,000 sq mm for top and bottom perimeter keep out space ------------------- 62,000 sq mm The total area of the board is 160,000 sq mm so this leaves about ---> 98,000 sq mm for programmable logic, routing, and bypass capacitors. So, how much programmable logic can we fit into this 98,000 sq mm? Let's pick for this example the XC4020. Pick this because it has > 192 I/O pins, i.e. greater than 3 x 64 I/O pins, i.e. if this card is 64 bits wide then having greater than 192 I/O pins lets you bring in 2 x 64 and output 64. So a XC4020 requires 2,750 sq mm. Now to leave room for routing and bypass caps lets say that a XC4020 will require 6,000 sq mm. We have 98,000 sq mm of board space for this purpose so we have room for ---> 16 of the XC4020's in their 299 pin pin grid array packages. Down Load, Monitor Interface VME, CBus and Service Functions ^ | V 128 +------------------------+ 64 Input |\ | PROGRAMMABLE LOGIC | |\ Output Signals >---| >--------| aprox 16 chips with |---------| >---> Signals and |/ | 224 I/O's and 20k | |/ and Receivers | "gates" each. | Drivers +------------------------+ | | V High Speed Optical Output Data Driver for "Event" Data Cost Estimate for "THE" Card ---------------------------- Semiconductors FPGA's qty 17 @ 150$ = 2550$ Converts TTL,ECL qty 36 @ 3$ = 108$ VME Interface qty 1 @ 25$ = 25$ "Support section" qty 1 @ $ = 50$ (PROMs, timing fanout, ...) ------- 2733$ Connectors 96 pin DIN qty 1 @ 6$ = 6$ 160 pin DIN qty 2 @ 30$ = 60$ 34 pin 0.1 x 0.1 qty 5 @ 4$ = 20$ LEMO qty 4 @ 5$ = 20$ ------- 106$ Fiber Interface qty 1 @ 700$ = 700$ ------- 700$ Circuit Board qty 1 @ 800$ = 800$ 400mm x 400mm, ------- 6 trace layers, 800$ 2 plane layers, fine geometry Misc LED's, Bypass Caps qty 1 @ 25$ = 25$ ------- 25$ Mechanical qty 1 @ 50$ = 50$ Front Support Bar, ------- machining, anodizing, 50$ rear stiffener, etc. Assembly qty 1 @ $ = 200$ Components on one ------- side only, Surface 200$ mount and through hole --------- Total cost WITH fiber interface 4614$ Total cost WITHOUT fiber interface 3914$ Estimate of the Power Supplies and Current Required by THE Card For a working estimate let's make the following assumptions about THE card. The FPGA's will be available in 3.3 Volt family. The differential ECL drivers and receivers will run off of -4.5 volts and -2.0 volts. VME interface will run on +5 volts and will not require interface logic to connect to the 3.3 volt FPGA's. The estimate of -4.5 and -2.0 power can be fairly accurate: Integrated Circuit Qty +5 each -4.5 each total +5 total -4.5 ---------- --- ------- --------- -------- ---------- 100324 11 25 ma 45 ma 275 ma 495 ma 100325 26 45 ma 27 ma 1170 ma 702 ma --------- ---------- Total current 1445 ma 1197 ma from each supply There should be about 128 pull down resistors of 56 ohms each working across Vbb (1.320 Volts) to -2.0 Volts will require 12 ma each. Thus a total of 1.536 Amps of Vtt will be required. The rest of the estimates will be less accurate. VME Slave Interface (two F245's, an ALS521, two F244, two mid size PAL's) 1 Amp of +5V Service Functions (Oscilator, fanout, FPGA load PROM's) 2 Amps of +5V Optical Link (just a guess) 2 Amps of +5V FPGA's (16 of these at 1 Amp each) 16 Amps of 3.3V Summary of the Current Requirements for THE Card Supply Current Voltage Required --------- ---------- +5.0 V 6.5 Amps +3.3 V 16 Amps -2.0 V 1.6 Amps -4.5 V 1.2 Amps Estimate of the Bulk Power Supply ByPass Capacitors That We would Like to Have on THE Card There are two separate reasons why we would like a large amount of Bulk bypass capacitance on THE card and thus there are two ways to estimate the amount of Bulk power supply bypass capacitors that we would like to have. The first way is to say that each card should have enough Bulk power supply capacitors to run itself for one cycle (16 mill sec). To calculate this just find the effective load resistance that each cards presents to the various supplies and then find the "C" that gives an "RC" of 16 mill seconds. Estimated Effective Required "C" Supply Current Load to give a 16 mill Voltage Required Resistance sec "RC" Time Const --------- ----------- ------------ --------------------- +5.0 V 6.5 Amps 0.77 Ohms 21 k mFd +3.3 V 16 Amps 0.21 Ohms 76 k mFd -2.0 V 1.6 Amps 1.25 Ohms 13 k mFd -4.5 V 1.2 Amps 3.75 Ohms 4.3 k mFd The second reason for having Bulk power supply bypass capacitors is to protect the cards against the power supplies doing something random. Lets pick one over the power supply switching frequency as the time constant required to "filter out" random glitches from the power supplies. The switching frequency is 20 kHz so this gives 50 usec time constant. The "R" in the time constant comes from the resistance in the cables that connect the backplane to the power supplies. We can get these resistance numbers from the file that describes the DC power wiring and power bars. Then we want ALL of the cards in a backplane (working in parallel) to have enough Bulk bypass capacitance so that when put together with the "R" of the power supply cables the "RC" time constant is greater than 50 usec. Total Resistance in the DC Capacitance One Power Cables that Connect Required to Fifteenth Power Backplane to this Supply. give a time of this Supply Supply Cable + Return Cable const of 50 usec. Capacitance -------- ----------------------------- ------------------- ------------- +5V 2.061 mill Ohms 24 k mFd 1600 mFd +3.3V 0.806 mill Ohms 62 k mFd 4100 mFd -2V 6.651 mill Ohms 7.5 k mFd 500 mFd -4.5V 8.364 mill Ohms 6.0 k mFd 400 mFd In this table the "one fifteenth" number just shows how much Bulk bypass capacitance needs to be on each card so that a mostly full crate of cards working in parallel has enough capacitance to give a 50 usec time constant. So how close can one come to meeting these two requirements? The tallest component that we can put on a VME board is 0.540". It looks like aluminum electrolytic capacitors of 1/2" diameter and 1 1/2" length are about 5000 mFd. Tantalum capacitors of about the same size are 500 mFd. So for all of the power supplies we can meet the 50 usec RC power supply filter time constant by using one large aluminum electrolytic capacitor per supply. For the -4.5V supply we can meet the 16 mill sec hold up time constant with this same capacitor. For the +5V and the -2V supplies two of these large aluminum electrolytic capacitors would get us at least 1/2 of the 16 mill sec hold up time constant. For the +3.3V supply 4 of these large aluminum electrolytic capacitors gets us about 1/3 of the desired 16 mill sec hold up time constant. Thus it looks like 9 large aluminum capacitors are needed to get close to the requirements that we would like to meet. If there is space for more capacitors they would be useful on the +3.3V supply and to a lesser extent on the +5 volt supply. Some of these capacitors may fit between the VME backplane connectors or possibly in the array of FPGA's. There is (just barely) enough room between each pair of VME backplane connectors to squeeze 3 of these capacitors (for a total of 6 caps) with no cost in usable routing area. Old junk stuff -------------- Estimate the board area required to bring 128 differential signals on or off card. One Motorola "D" suffix SO-8 or SOIC-8 contains two drivers or receivers; thus 64 packages are required. Each package is 5 mm x 6.2 mm i.e. 31 sq mm. Thus the packages will require 2,000 sq mm. Double this to get a realistic estimate of the total board area required once you count the bypass caps and trace routing; ---> 4,000 sq mm for drivers and receivers.