Receiver Section in the HSRO -------------------------------- Original Rev. 5-JUNE-1996 Most Recent Rev. 14-AUG-1998 The receiver section of the HSRO Link on THE card is used to receive command information from the DAQ system (via the VRB). This receiver section consists of two subsections: the Data Receiver and the Clock Receiver. Each of these subsections produces two signals that go to the Board Support Functions FPGA on THE Card: an Information signal and a Link Status signal. Thus the 4 signals that are routed to the BSF FPGA from the HSRO Receiver are: 1. HSRO Command Data 2. HSRO Command Data Link Status 3. HSRO Command Clock 4. HSRO Command Clock Link Status Both the Data Receiver and the Clock Receiver are mounted on the front panel of THE Card. The Data Receiver is mounted above the Clock Receiver. Each of these receivers consists of an HP HFBR-2416T PIN diode - transconductance amplifier, and a Micro Linear ML6622 "Quantizer" IC. The two receivers share a National 100390 PECL-TTL translator. The HFBR-2416T and the analog half of the ML6622, in each receiver, operate from filtered Vcc and Gnd supplies. Each receiver has its own VccA and GndA filters that are separate from the filters for the other receiver. The digital section of both ML6622's together with the PECL section of the shared National 100390 operate from a filtered Vcc. This supply is called VccECL. The digital section of the ML6622's and the PECL section of the 100390 operate from the normal GND plane. The TTL section of the Nation 100390 operates from the normal Vcc +5V plane and the normal GND Plane. Near the TTL outputs of the 100390 there are series terminator resistors in the 4 signal lines that run to the Board Support FPGA. These are needed because of the fairly high frequency signals on these lines (53 MHz), because of the fairly long run from the 100390 over to the Board Support FPGA, and because the 100390's TTL output drivers run from +5V and the Board Support FPGA runs from +3V. Layout: The HFBR-2416T's are mounted at the front edge of the card and are spaced 0.1" apart. In the Mentor orientation the ML6622's are mounted above the HFBR2416T's. The ML6622's have their pin #1 in the top right hand corner. This orientation of the ML6622 puts all of its low level signal input pins and other analog pins near the HP optical receivers, and all its output and other digital pins facing toward the "Mentor top" of the board. Between the HFBR2416T's and the ML6622's there is a row of "1206 size" passive components. This row of components includes: 1. The two 0.01 uFd caps at the signal input to the ML6622 2. The 0.1 uFd cap that is connected between the ML6622 CAP terminal and the GndA for the ML6622. 3. The 2200 pF cap that is connected between the ML6622 CTimer terminal and the GndA for the ML6622. 4. The 10 Ohm resistor that is between this receiver's VccA and pin #6 of its HFBR-2416T. If there is additional space between the HFBR-2416T and the ML6622 then this may be a good place to put the 0.1 uFd cap that runs between VccA and GndA of each receiver. I think that all passive components, expect for the Tantalum caps and the inductors, are 1206 components. Surrounding the ML6622 can be the 0.1 uFd capacitor for it that runs between VccECL and the GND plane. This is also a good place for the 1k Ohm resistor that runs between pins #1-#2 and pin #3. The National 100390 is mounted with its pin #1 oriented towards "Mentor top". This faces its inputs towards the ML6622's. Surrounding the 100390 can be the various tantalum capacitors and then further towards the "Mentor top" may be a good place to locate the filter inductors. Transmitter Section in the HSRO ----------------------------------- Original Rev. 5-JUN-1996 Most Recent Rev. 11-AUG-1998 Questions: Are we using the Finisar pcb board or the Utes version of the Finisar board ? What is the pinout of the Utes board ? Did Utes use the same AMP connector as Finisar used ? Did Utes bring out all the G-Link transmitter input signals or just the signals that Marvin needs for his address-data format readout ? In our HSRO how do we want to drive the Finisar pcb, i.e. how do we want to drive the HP G-Link chip: from TTL to ECL converters, from D-Latched TTL to ECL converters, from transparent latched TTL to ECL converters ?? A known workable solution is the following: 1. Use the Finisar pcb except have its connector mounted on the same side of its PCB as its Laser module and its G-Link chip. Perhaps we can accomplish this by purchasing special Finisar pcb's or by purchasing the pcb assembly from Finisar without the connector installed. The Finisar pcb is their part number FTC-1101. I call it a pcb because to Finisar the word module means just the Laser module itself. 2. Mount the Finisar pcb to THE Card with the Finisar components between the Finisar pcb and THE Card. This orients the Finisar connector pinout in the following way: Finisar pin #1 is in "Mentor upper right" Finisar pin #30 is in "Mentor upper left" Finisar pin #31 is in "Mentor lower right" Finisar pin #60 is in "Mentor lower left" 3. For the way that we want to use the HSRO we need to connect to the following Finisar connector pins, i.e. HP G-Link chip signals: DI0 9 Input ECL \ DI1 10 Input ECL \ DI2 41 Input ECL \ DI3 11 Input ECL | DI4 42 Input ECL | DI5 12 Input ECL | DI6 43 Input ECL | DI7 13 Input ECL | ECL data to the DI8 44 Input ECL | G-Link Chip DI9 14 Input ECL | DI10 45 Input ECL | DI11 16 Input ECL | DI12 46 Input ECL | DI13 17 Input ECL | DI14 47 Input ECL | DI15 18 Input ECL | DI16 48 Input ECL | DI17 19 Input ECL / DI18 49 Input ECL / DI19 20 Input ECL / FLAG 39 Input ECL Flag Bit \ DAV* 6 Input ECL Data Available \ CAV* 36 Input ECL Control Word Available \ STRBIN 37 Input ECL Clock input AC coupled | STRBIN* 38 Input ECL Clock input AC coupled | LOOPEN 23 Input ECL Loop Back Enable | Control TO FLAGSEL 4 Input ECL Flag Bit Select | and a little M20SEL 33 Input ECL 16 vs 20 bit Word Selec | FROM the DIV0 54 Input ECL VCO Divider Select | G-Link Chip DIV1 22 Input ECL VCO Divider Select | RST* 53 Input ECL Reset | ED 8 Input ECL Enable Data / FF 7 Input ECL Fill Frame Select / LOCK 32 Output ECL PLL Locked Indicator / CS* 55 Input TTL to Finisar \ READY 26 Output TTL from Finisar \ SI 56 Input TTL to Finisar | Control TO-FROM SO 57 Output TTL from Finisar | the Finisar Laser SCLK 58 Input TTL to Finisar / OFC_STATUS 52 Output from Finisar / RX_OPT_PWR 24 analog Finisar N.C. required \ NC3 27 Finisar N.C. required | Finisar stuff that RX_SYS1 25 Finisar N.C. required | we know requires no RX_SYS2 28 Finisar N.C. required / connection from us NC1-2 30,51 No connection Vcc1-7 5,15,21,31,40,50,59 ECL - VCC i.e. GND Vee1-2 34,35 ECL - VEE i.e. -5V DVcc 29 Digital +5V for the optics DGnd1-2 1,60 Digital GND for the optics Vtt1-2 2,3 -2V for the ECL Term Layout of the connector on THE card to accept an Finisar pcb mounted with its components next to THE Card and the Finisar connector on the component side of the Finisar pcb. Only the G-Link data and control signals and all the power and ground connections are shown, i.e. none of the Finisar connections are shown. D F V L V V V L V V c O c c c A t t c O D c D D D D D c D c G t t D + P I E I I I I I E D D D D D D A E S - - G 5 E V C 1 1 1 1 1 C I I I I I I E F V C E 2 2 N V N 1 L 9 7 5 3 1 L 9 7 5 3 1 0 D F * L L V V D 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 D V D R V D D D D D D D D D V F S S C V V M L V G c I S c I I I I I I I I I c L T T A e e 2 O c N c V T c 1 1 1 1 1 8 6 4 2 c A R R V e e 0 C c D E 0 * E 8 6 4 2 0 E G B B * - - S K E C C C I I 5 5 E C L L L N N V V L L * Can we get tantalum and ceramic by pass caps near pin #29 of this connector. This is the single +5V connection and it may be making a lot of noise as the Laser modulates. It would also be a good idea to bypass near pin #34,#35 the ECL Vee and near pins #2,#3 the ECL Vtt. How will we use the HDMP-1012 G-Link Transmitter --------------------------------------------------- 1. It does not look like we need to do anything with the (6 or is it 9) control lines to the Laser module on the Finisar PCB. Just bringing them out to vias is fine. 2. I think that there are THREE possible ways to use the G-Link to transmit to transmit both our 16 bit data and our control information. A. Always operate in 20 bit mode. On every frame this gives us 16 data bits and 4 control bits. B. Operate in 16 bit mode and use the "FLAG" bit as a single piece of control information that is sent every frame. C. Operate in 16 bit mode and sometimes send 16 bits of data and sometimes send 16 bits of control. To send one or the other we pull on either DAV* for data or else on CAV* for control information. At the receiver end they get either at data strobe or a control information strobe. In option "A" we would just pull on the DAV* line each time that we had data + control information to send. All other control inputs would be static during normal operation. However, since the number of bits sent depends on whether 16 or 20 bit mode is selected (i.e. there are not 4 additional padding bits in the 16 bit mode), this option requires a faster bit rate than if only 16 data bits are sent. Option "B" sounds stupid. I think that it would be good to make THE Card be able to do either option "A" or "C". This gives us the best chance of being able to use some one elses VRB input board. 11-AUG-1998 On reflection, this doesn't seem so stupid and is the method of choice. In option "C" we would pull on the DAV* line each time that we wanted to send data and we would pull on the CAV* line each time that we wanted to send control information. In either case we present our information to the G-Link transmitter on its Data Input pins 0:15. All other control inputs would be static during normal operation. 3. The table below lists the 13 control inputs to the G-Link chip on the Finisar pcb and the one control output from the G-Link chip. The "Y" indicates that YES we need to talk to this control input. The "F" indicates that we need to talk FAST, i.e. at frame speed. The "R" indicates that we only need to talk slowly, i.e. REGISTER programming via TCC speed. The "J" indicates that we only need to be able to talk very slowly, i.e. at JUMPER changing speed (but using a register would be fine). The "S" indicates that this is a STRAGE ECL input, i.e. AC coupled. How Fast must Signal we be to Direction change this Signal Pin # and type Signal Name Use? Control Input -------- ----- ---------- ---------------------- ---- ------------- FLAG 39 Input ECL Flag Bit Y J DAV* 6 Input ECL Data Available Y F CAV* 36 Input ECL Control Word Available Y F STRBIN 37 Input ECL Clock input AC coupled Y FS STRBIN* 38 Input ECL Clock input AC coupled Y FS LOOPEN 23 Input ECL Loop Back Enable Y J FLAGSEL 4 Input ECL Flag Bit Select Y J M20SEL 33 Input ECL 16 vs 20 bit Word Select Y J DIV0 54 Input ECL VCO Divider Select Y J DIV1 22 Input ECL VCO Divider Select Y J RST* 53 Input ECL Reset Y R ED 8 Input ECL Enable Data Y R FF 7 Input ECL Fill Frame Select Y J LOCK 32 Output ECL PLL Locked Indicator The STRBIN and STRBIN* are not really control inputs. They are the Frame rate clock inputs. This is the 53.104 signal that we get as Timing Signal #0 on THE Card. It looks like the G-Link chip wants this as an AC coupled differential ECL sigal. We will have to use pull downs at the ECL driver chips outputs to get a couple of ma of current in these emitters and then the HP book says to use 0.1 uFd series caps and then the HDMP-1012 chips has internal 50 Ohm to Gnd terminators. For all of the other ECL inputs the HDMP-1012 has internal 16k Ohm resistors to -2V. Does the Finisar pcb provide 50 Ohm resistors to -2V or are we expected to do this on our card ? Answer, I think that we need to do this and then the run to the Finisar is taken to be a stub. LOCK 32 Output ECL PLL Locked Indicator Do we care about being able to read this in a register ? Do we have a spare ECL --> TTL converter ? Additional Support Documentation ------------------------------------ Rev. 17-MAR-1997 Logic Analyzer Adapter Card for the Finisar Connector on THE Card --------------------------------------------------------------------- L O O P E n n n n n n n n n n n n n n n N c c c c c c c c c c c c c c c X X X X X X X X X X X X X X X X F S L T S M A R T 2 D D G F B R 0 D D D D I I R D S L I B C S 1 1 1 1 V V S E F A E A N I A E 9 8 7 6 1 0 T D F V L G * N V L X X X X X X X X X X X X X X X X D D D D D D 1 1 1 1 1 1 D D D D D D D D D D 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X X Gnd Gnd X X Gnd Gnd X X Gnd Gnd X X Gnd Gnd X Finisar Connector on THE Card ---------------------------------- +-----------+ +-----------+ +-----------+ +--| P1 |---------| P2 |---------| P3 |--+ | +-----------+ +-----------+ +-----------+ | | | ~ ~ | | | | | | | | | 30 +------------------+ 1 | | | Finisar Conn. | | | 60 +------------------+ 31 | | | +-------------------------------------------------------------+ Front of THE Card The above sketch shows the arrangement of the connector for the Finisar Module on THE Card. As shown the physical pin numbers match the pin number functions in the Finisar documentation and the pin numbers in the schematic sheet for this connector. Note that this (Finisar) pin numbering scheme does not match the small moulded in triangle symbol in the actual AMP connector. The Finisar Mezzanine Card ------------------------------ +-----------------------------------------+ | (1) _____ (30) | | 61 +----------+ +-------------+ 90 | | | | | | 91 +----------------------------+ 120 | | (31) (60) | | 64 41 | | +----------+ | | 65 | | 40 | | | HP | | | | G-Link | | | 80 | | 25 | | +----------+ | | Jumper 1 24 | | | | LED XXXXXXXXXXX | | | Component Side | 17 1 | Up View | | | | +-----------------------------------------+ As supplied the Finisar mezzanine module has the connector mounted on the "Solder" side of the board. This connector must be removed and a new connector installed on the normal component side of the Finisar card. The component side of the Finisar card has the G-Link IC and the Laser module connector on it. The pin numbers 61:120 refer to the pin numbers in silkscreen on the component side of the Finisar mezzanine board. The numbers in parenthesis are the corresponding pin numbers as used in all the rest of the Finisar documentation. Note that when you put the connector on the component side of the Finisar board and then turn it over that it will fit down over the connector on THE Card. The pin number 1:17 on the Laser module connector match the pinout of the Finisar Laser module itself. The two Finisar boards that we received on 9-SEPT-1997 appear to have been manufactured by: KELTOOL 561 Shoreview Pard Road St Paul, MN 55126 612-483-2703 800-328-1323 The Finisar circuit board provides on board 51 Ohm pull down to VTT on the following signals: D0:D19 STRBIN FLAG STRBIN* DAV* CAV* The following signals run right into the HP G-Link chip and do not have pull down resistors on the Finisar board: DIV0 FLAGSEL DIV1 M20SEL RST* LOOPEN ED FF The Finisar circuit board uses two GND's. These are DGnd and Logic Gnd. On the Finisar circuit board I believe that these are separate isolated sections of a common plane layer. DGnd and Logic Gnd are not electrically connected on the Finisar circuit board. DGnd goes only to the Laser module itself and the Laser power supply by pass capacitors. The Laser module mounting holes are also connected to DGnd. Logic Gnd is the ECL Vcc and is mostly involved with the HP G-Link chip. It is connected directly with the following pins on the G-Link chip: HGnd pins: 7, 13 Gnd pins: 23, 24, 43, 44, 52, 63, 64, 72, 79 ECLGnd pins: 33, 66, 77 Logic Gnd also connects to the by pass capacitors involved with the Vee and Vtt nets. The outer mounting holes, the board mounting holes are not connected to either Gnd system. Pins 74 MDFSEL is connected to Logic Gnd. 5-SEP-1998 Versions of the HP G-Link Transmitter Chip HDMP-1002 Vee range -4.5V : -5.5V Typ 340 ma min 1.53 Watts 68 lead ceramic quad flatpack max 1.87 Watts 110 to 1400 MBaud, ECL I/O, BiPolar HDMP-1012 Vee range -4.5V : -5.5V Typ 403 ma so for 4.5 1.73 Watts 80 lead aluminum M-Quad package max 2.22 Watts 150 to 1500 MBaud, ECL I/O, BiPolar HDMP-1022 Vcc +5.0V Typ 385 ma Max 470 ma typ 1.93 Watts 80 lead aluminum M-Quad package max 2.35 Watts 150 to 1500 MBaud, TTL I/O, BiPolar HDMP-1032 Vcc in range +3.3V @ ??? ma typ . Watts