Description of the Timing Origination Module "TOM" -------------------------------------------------------- Original Rev. 23-JAN-1996 Latest Rev. 6-NOV-1996 Setup Section Rev. 1-FEB-1999 The purpose of the Timing Origination Module is to allow normal 6U x 160 mm VME cards to be used in the Run II Framework crates. These crates operate in the A24 D16 mode. TOM also drives the 16 Timing Signals in each crate. This board is intended to operate normally in slot #1 with a vertical Interconnect installed in that slot. The Timing Origination Module will perform the following functions: 1. Drive differential ECL timing signals onto P1. 2. Provide monitor output copies of the timing signals. 3. Provide outputs to repeat the timing signal cable. 4. Provide the physical and electrical support to plug in a normal 6U VME card (i.e. 3 row DIN connectors) into the Framework P1 backplane. 5. Map the 3 row P1 VME to the 5 row P1 backplane. 6. Terminate the P1 VME signals. 7. Provide power and ground to the 3 row P1 and P2 VME connectors. 8. Pass through the VME P2 USER SIGNALS to the P2 backplane. 9. Provide an activity indicator to show when there is VME activity in the crate. 10. Provide monitor test points for the power supply voltages coming from the Framework backplane. 12 Provide LED's to indicate the status of the 4 power supplies. 12. Provide a push button to generate a VME ACFAIL* signal. 13. Provide a "proto-type" area where special use circuity can be implemented. All details about the components and connections on this card along with many explainitory notes are presented in the two files: Tom_Key_In_Comp_File.txt and Ton_Key_In_Nets_File.txt ########################################################################### Layers: It requires at least 4 layers to route out of the 5 row DIN connectors. These traces must cross over a pair of ECL traces so this brings the total to at least 6. But it requires 5 trace layers to get the TTL VME traces through the VME Terminator. So that brings the card up to 7 trace layers. There are a number of planes: GND, Vcc, Vee, and Vtt. At this time we do not need a Vdd plane nor do the +12V and -12V supplies need to be routed on planes. So it is only 4 required planes but we are going to double up the GND plane to keep a balanced setup between trace layers and plane layers. So we have at least 7 trace layers and 5 planes, i.e. a 12 layer card. The layer ordering is: Physical Layer ----- Component Side 1 ---------------- Signal Layer #1 and SMD Pads 2 VEE =============== 3 ---------------- Signal Layer #2 4 GND =============== 5 ---------------- Signal Layer #3 \ Seconday 6 VCC =============== | Differential 7 ---------------- Signal Layer #4 / ECL Pair 8 GND =============== 9 ---------------- Signal Layer #5 \ Differential 10 ---------------- Signal Layer #6 / ECL Pair 11 VTT =============== 12 ---------------- Signal Layer #7 Solder Side This puts the Primary Differential ECL between the least noisy pair of planes. It puts the Vcc next to Gnd and it puts a quiet plane (Vee) next to the surface where all of the components are mounted. A Secondary Differential ECL Pair is available. Where this Secondary Differential ECL Pair is used the VCC plane is removed. In the areas where there are lots of TTL traces (e.g. between J1 and J4) we need to keep all of the planes well "AC connected". This implies lots of bypass capacitors in these areas even though there may not be any noisy loads on a given plane in this area. Routing TTL VME Traces between connectors J1 and J4: Dressing the VME traces out of J1, through the VME Terminator and into J4 is going to be the tightest routing. To accomplish this VME routing the layers in the following way: So there are 5 layers on which to route these TTL VME traces. The arrangement selected is to put the J1 row "C" traces on Signal Layer #1 (because this puts the fewest traces on the surface with the SMD pads) and then just to put the rest of the J1 row traces in order on the TTL signal layers. So: J1 Row Signal Layer -------- -------------- "A" 2 "B" 3 "C" 1 "D" 4 "E" 7 Use 10 or 12 mil traces for the TTL VME traces. The connections to the VME Terminator resistor networks are arranged in the following way: R50 pin #2 : #9 J1-A11 : J1-A20 R55 pin #2 : #9 J1-A20 : J1-A29 R51 and R56 same thing for the J1 "B" row R52 and R57 same thing for the J1 "C" row R53 and R58 same thing for the J1 "D" row R54 and R59 same thing for the J1 "E" row Traces between J2 and J5: The two outer rows on the 3 row VME P2 connector (i.e. J5) are the "User Defined" pins. The TOM module will route: P2 3 Row P2 5 Row ---------- ---------- J5 row A <--> J2 row A on Mentor Signal Layer #3 J5 row C <--> J2 row B on Mentor Signal Layer #4 The Vertical Interconnect Module uses ECL signals coming into its P2 row "C". So lets place the J5 row "C" to J2 row "B" traces on Signal Layer #4 (i.e. between Vcc and Gnd) and place the J5 row "A" to J2 row "A" traces on Signal Layer #3 (i.e. between Gnc and Vcc, a the preferred channel for TTL traces) . Power Traces: Some of the power supply voltages transported on the TOM card are not carried on planes. The voltages that are transported via traces are the following: +12V, -12V, +5 StdBy, and VDD. These 4 voltages are transported on wide traces that are on the following Mentor Signal Layers: +12V Mentor Signal Layer #4 -12V Mentor Signal Layer #2 +5 StdBy Mentor Signal Layer #3 VDD Mentor Signal Layer #2 These 4 supplies all have one tantalum bypass capacitor on the TOM module. In addition the VDD has a large aluminum electrolytic capacitor, as do the other principal power supply voltages. So to summarize the usage of the Signal Layers: Actual Circuit Board Mentor Conn Conn Diff ECL Physical Mentor Signal J1 to J2 to Timing Layer Plane # Layer # J4 J5 Signals -------- --------- ---------- ----- ----- -------- Component Side 1 ----- Signal Layer #1 J1-C - 2 VEE Plane 3 ==== 3 ----- Signal Layer #2 J1-A - 4 GND Plane 2 ==== 5 ----- Signal Layer #3 J1-B J2-A \ Non-Inv 6 VCC Plane 1 ==== | 2nd pair 7 ----- Signal Layer #4 J1-D J2-B / Inv 8 GND Plane 2 ==== 9 ----- Signal Layer #5 - Non-Inv 10 ----- Signal Layer #6 - Inv 11 VTT Plane 4 ==== 12 ----- Signal Layer #7 J1-E - Solder Side In areas where the Secondary Differential ECL Pair is used the VCC plane should be relieved. There are 12 copper layers, 7 trace layers and 5 plane layers. There are 11 dielectric cores. As setup on MENTOR it looks this way: Physical Order Logical Logical Layer Number Layer 1 Layer 2 # Comment # ----------- ------ -------- -------- -------------------- Physical_1 1 Signal_1 Pad_1 Component Side Physical_2 - 2 - Power_1 VEE Power Physical_3 3 Signal_2 Physical_4 - 4 - Power_2 GROUND Physical_5 5 Signal_3 Physical_6 - 6 - Power_3 VCC Power Physical_7 7 Signal_4 Physical_8 - 8 - Power_4 GROUND Physical_9 9 Signal_5 Diff ECL Non Physical_10 10 Signal_6 Diff ECL Inv Physical_11 - 11 - Power_5 VTT Power Physical_12 12 Signal_7 Pad_2 Solder Side Notes: The MENTOR Order Number is exactly the way that the actual printed circuit board should look. The "tom_pcb" geometry has the Plane Nets defined in the proper order for this card. That is: VEE, GROUND, VCC, GROUND, VTT. ########################################################################### VME Terminator -------------- ALL VME Terminations are 330 Ohm to +5 Volts and 470 Ohm to Gnd. The Thevenin equivalent is 194 Ohm to 2.94 Volts. Thus each signal must drag 2x 5 Volts / 330 Ohms = 30 ma to Gnd to enter the voltage low state. These terminations are on all lines EXCEPT: BG0IN* : BG3IN* BG0OUT* : BG3OUT* IACKIN*, IACKOUT* Thus terminate the following 72 lines: DATA_00 : DATA_15 16 ADRS_01 : ADRS_23 23 AM0 : AM5 6 AS*, DS0* : DS1* 3 LWORD*, WRITE* 2 DTACK*, BERR* 2 BBSY*, BCLR*, 2 BR0* : BR3* 4 IACK*, IRQ1* : IRQ7* 8 SERCLK, SERDATA* 2 ACFAIL*, SYSCLK, SYSFAIL*, SYSREST* 4 Everyone uses 10 pin SIP 330/470 Ohm resistor networks. They use 9 of them. One could also use individual SIP's if the parts were easier to obtain. Can one use 1206 Chip Array Surface Mount resistors for the VME termination ? Well the power in the 330 Ohms resistor is: 5V**2 / 330 Ohms = 0.075 Watts and the rating of the 1206 resistor ARRAY is: 0.125 Watts per resistor for an 8 terminal 4 resistor array. 0.063 Watts per resistor for a 10 terminal 8 resistor (2 commons) array. The rating of a CTS 767 resistor network is 0.15 Watts per resistor and 2.0 Watts per package. The 767 is available in 330/470 dual terminator configuration. The normal SIP part to use is: Bourns 4310R-104-331/471 In this device the 330 Ohm resistor is connected to pin #10 and the 470 Ohm resistor is connected to pin #1. Diode Clamps on the following VME Signals ----------------------------------------- The VERO (and one of the Schroff) VME terminators use diode clamps to prevent signals swinging below ground. They put these clamps on the following signals: B1 BBSY* A12 DS1* B2 BCLR* A13 DS0* A10 SYSCLK A16 DTACK* C11 BERR* A18 AS* In our application I can not see a overwhelming demand for this (especially on the BBSY*, BCLR*, and SYSCLK) lines but if these two rational companies thought that it was a good idea then let's do it on our terminators. It costs very little. It looks like: o +5 Volts | Z Z 220 Ohm Z | +--------+--------+--------+--.....---+--------+---------+ | | | | | | | V - V V V V - - - - - - - - | | | | | | | o o o o o o o GND GND Signal Signal Signal Signal GND bypass bypass Diode Cap Cap to Gnd to Gnd to Gnd ########################################################################### The J2 Connector ---------------- The 5 row J2 Connector on TOM handles the signals for the outer rows of the normal VME 3 row "P2" connector and it also supplies the I/O connections to the Proto-Type area on TOM. The center row of TOM's 5 row J2 connector has the normal power and ground wiring that is used on all of our Run II 5 row equipment. PROVISIONS for connecting to the center row of the 3 row VME "P2" connector J5. ??? TOM J2 LAYOUT ---------------------------------------------------------------- Link to the Classic Proto-Type Area VME P2 Outer Rows I/O Via Connections ---------------------- --------------------- Pin Row Row Row Row Row Number "A" "B" "C" "D" "E" ------ --------- --------- ------- --------- --------- 1 to J5-A1 to J5-C1 Gnd PT-01-Inv PT-01-Non 2 to J5-A2 to J5-C2 +3V PT-02-Inv PT-02-Non 3 to J5-A3 to J5-C3 Gnd PT-03-Inv PT-03-Non 4 to J5-A4 to J5-C4 +3V PT-04-Inv PT-04-Non 5 to J5-A5 to J5-C5 -2V PT-05-Inv PT-05-Non 6 to J5-A6 to J5-C6 Gnd PT-06-Inv PT-06-Non 7 to J5-A7 to J5-C7 +3V PT-07-Inv PT-07-Non 8 to J5-A8 to J5-C8 Gnd PT-08-Inv PT-08-Non 9 to J5-A9 to J5-C9 +5V PT-09-Inv PT-09-Non 10 to J5-A10 to J5-C10 Gnd PT-10-Inv PT-10-Non 11 to J5-A11 to J5-C11 +3V PT-11-Inv PT-11-Non 12 to J5-A12 to J5-C12 Gnd PT-12-Inv PT-12-Non 13 to J5-A13 to J5-C13 +3V PT-13-Inv PT-13-Non 14 to J5-A14 to J5-C14 Gnd PT-14-Inv PT-14-Non 15 to J5-A15 to J5-C15 -2V PT-15-Inv PT-15-Non 16 to J5-A16 to J5-C16 Gnd PT-16-Inv PT-16-Non 17 to J5-A17 to J5-C17 +3V PT-17-Inv PT-17-Non 18 to J5-A18 to J5-C18 Gnd PT-18-Inv PT-18-Non 19 to J5-A19 to J5-C19 +5V PT-19-Inv PT-19-Non 20 to J5-A20 to J5-C20 +3V PT-20-Inv PT-20-Non 21 to J5-A21 to J5-C21 Gnd PT-21-Inv PT-21-Non 22 to J5-A22 to J5-C22 +3V PT-22-Inv PT-22-Non 23 to J5-A23 to J5-C23 Gnd PT-23-Inv PT-23-Non 24 to J5-A24 to J5-C24 -2V PT-24-Inv PT-24-Non 25 to J5-A25 to J5-C25 Gnd PT-25-Inv PT-25-Non 26 to J5-A26 to J5-C26 +3V PT-26-Inv PT-26-Non 27 to J5-A27 to J5-C27 Gnd PT-27-Inv PT-27-Non 28 to J5-A28 to J5-C28 +5V PT-28-Inv PT-28-Non 29 to J5-A29 to J5-C29 +3V PT-29-Inv PT-29-Non 30 to J5-A30 to J5-C30 Gnd PT-30-Inv PT-30-Non 31 to J5-A31 to J5-C31 +3V PT-31-Inv PT-31-Non 32 to J5-A32 to J5-C32 Gnd PT-32-Inv PT-32-Non ########################################################################### The J3 Connector ---------------- The Timing Signals are received on the J3 5 row backplane connector. They are received on rows "A" and "B" with row "B" receiving the non-inverted half of a differential signal and row "A" receiving the inverted half of the signal. All unused pins in the "A" and "B" rows of J3 are connected to the ground plane. The "C" row of J3 contains the normal power and ground connections that are used on all of our 5 row Run II equipment. The Ground, +5V, and -4.5V connections on TOM's J3 row "C" are connected to the appropriate power planes. The +3V pins on J3 row "C" are NOT connected to the TOM's VDD Bus. All pins in TOM's J3 row "D" are connected to the ground plane. All pins in TOM's J3 row "E" are left completely unconnected. The layout of the TOM's J3 5 row connector is the following: TOM's J3 LAYOUT ---------------------------------------------------------------- Pin Row Row Row Row Row Number "A" "B" "C" "D" "E" ------ --------- --------- ------- ------- ------- 1 Gnd Gnd Gnd Gnd N.C. 2 TS_00_INV TS_00_NON +3V Gnd N.C. 3 Gnd Gnd Gnd Gnd N.C. 4 TS_01_INV TS_01_NON +3V Gnd N.C. 5 Gnd Gnd -4.5V Gnd N.C. 6 TS_02_INV TS_02_NON Gnd Gnd N.C. 7 Gnd Gnd +3V Gnd N.C. 8 TS_03_INV TS_03_NON Gnd Gnd N.C. 9 Gnd Gnd +5V Gnd N.C. 10 TS_04_INV TS_04_NON Gnd Gnd N.C. 11 Gnd Gnd +3V Gnd N.C. 12 TS_05_INV TS_05_NON Gnd Gnd N.C. 13 Gnd Gnd +3V Gnd N.C. 14 TS_06_INV TS_06_NON Gnd Gnd N.C. 15 Gnd Gnd -4.5V Gnd N.C. 16 TS_07_INV TS_07_NON Gnd Gnd N.C. 17 Gnd Gnd +3V Gnd N.C. 18 TS_08_INV TS_08_NON Gnd Gnd N.C. 19 Gnd Gnd +5V Gnd N.C. 20 TS_09_INV TS_09_NON +3V Gnd N.C. 21 Gnd Gnd Gnd Gnd N.C. 22 TS_10_INV TS_10_NON +3V Gnd N.C. 23 Gnd Gnd Gnd Gnd N.C. 24 TS_11_INV TS_11_NON -4.5V Gnd N.C. 25 Gnd Gnd Gnd Gnd N.C. 26 TS_12_INV TS_12_NON +3V Gnd N.C. 27 Gnd Gnd Gnd Gnd N.C. 28 TS_13_INV TS_13_NON +5V Gnd N.C. 29 Gnd Gnd +3V Gnd N.C. 30 TS_14_INV TS_14_NON Gnd Gnd N.C. 31 Gnd Gnd +3V Gnd N.C. 32 TS_15_INV TS_15_NON Gnd Gnd N.C. ########################################################################### Layout of the Timing Signal Distribution System: ------------------------------------------------ The following is a list of which section of which integrated circuit handles each of the Timing Signals: Front Panel Backplane Signal Receiver Buffer Driver ------ -------- ----------- --------- TS_00 U1-fD U5-fD U20-Q4 TS_01 U1-fC U5-fC U20-Q3 TS_02 U1-fB U5-fB U20-Q2 TS_03 U1-fA U5-fA U20-Q1 TS_04 U2-fD U6-fD U22-Q4 TS_05 U2-fC U6-fC U22-Q3 TS_06 U2-fB U6-fB U22-Q2 TS_07 U2-fA U6-fA U22-Q1 TS_08 U3-fD U7-fD U21-Q4 TS_09 U3-fC U7-fC U21-Q3 TS_10 U3-fB U7-fB U21-Q2 TS_11 U3-fA U7-fA U21-Q1 TS_12 U4-fD U8-fD U23-Q4 TS_13 U4-fC U8-fC U23-Q3 TS_14 U4-fB U8-fB U23-Q2 TS_15 U4-fA U8-fA U23-Q1 -------- ----------- --------- 100314 100314 100316 Quint Quint Quad Receiver Receiver Driver fA fA Q1 fB fB Q2 fC fC Q3 fD fD Q4 fE fE ########################################################################### Timing Signal Outputs to the Front Panel The Front Panel copy of the timing signals is available in two versions. On the Front Panel itself there is a 34 pin header that has a single ended version of all 16 timing signals. This is for use with a scope to check the timing signal waveforms. These are single ended ECL levels with a 100 Ohm series terminator resistor. One side of this header is all Gnd and the other side is the Timing Signals. The pin out is the following: Front Panel Connector J7 Pin Out -------------------------------------------- Pin Pair Number Signal --------------- ------------------------ 1 - 2 Timing_Signal_14 - Gnd \ 3 - 4 Timing_Signal_15 - Gnd \ . . . . | . . . . | Runs Backwards . . . . | 29 - 30 Timing_Signal_1 - Gnd / 31 - 32 Timing_Signal_0 - Gnd / 33 - 34 VME_AS* - VME_DTACK* On the body of the TOM Card there is another 34 pin header that provides a differential ECL copy of all 16 timing signals. This includes pull down resistors to VTT. The driver for this differential copy also drives the single ended copy to the Front Panel. If you need the highest quality differential copy available then it may be necessary to cut the 100 Ohm series resistors. Differential ECL Copy of the Timing Signals Output Connector J6 Pin Out -------------------------------------------------- Pin Pair Number Signal --------------- ------------------------------- 1 - 2 Non-Inv Timing_Signal_0 Inv 3 - 4 Non-Inv Timing_Signal_1 Inv . . . . . . . . . . . . 29 - 30 Non-Inv Timing_Signal_14 Inv 31 - 32 Non-Inv Timing_Signal_15 Inv 33 - 34 Gnd - Gnd ########################################################################### Voltage Monitor Test Points and LED's On the Front Panel there are 4 voltage monitor test points and a Gnd test point. The Gnd test point is separated from the 4 voltage test points so that one can plug in both of the meter test leads with out bending them. Each of the 4 voltages has its own LED to give a visual indication that all is OK with that power supply. These test points are feed through pico fuses. ########################################################################### Front Panel Layout 34 pin header withOUT ejection ears 5 test points Gnd separated from the 4 voltage points LED's, 4 assemblies of 3 LED's each Push Button Switches from VME Reset and for AC Fail ########################################################################### Front Panel VME RESET and VME ACFAIL PushButtons The Front Panel has separate pushbuttons for both VME RESET and VME ACFAIL. These to buttons are mounted apart from each other to help reduce confusion about which one to push. They are separated by the LED display. The pushbuttons are mounted behind the front panel so that they can not be accidentally pressed. Each pushbutton has a link so that either or both of the pushbuttons may be disabled. The SPDT pushbuttons operate flip-flops so that clean edges are generated. 74F38 driver chip is located between connectors J1 and J4 to keep the VME bus runs short. The two unused sections of the 74F38 are brought out to via's for prototype use. ########################################################################### VME AS* and DTACK* Indicators and Test Points We want some indication of activity in each crate. Running an LED from the VME AS* and DTACK* signals will give us this activity indicator. Close to the J1 to J4 VME connection there is a buffer to listen to the VME AS* and DTACK* signals with out placing too much extra load on them. The buffered copy of these signals drives a one shot stretcher that drives their Led's. A buffered (un-stretched) copy of each of these signals drives a pin on the Front Panel connector, J7, through a 110 Ohm resistor. This would allow one to trigger a scope when a VME cycle starts in the crate. The buffered AS* signal is connected to J7 pin 33 and the DTACK* signal is connected to J7 pin 34. ########################################################################### Proto-Type Area The Proto-Type Area will not be a classic array of holes. Rather it will be a set of dedicate layouts to support various types of IC packages. A number of via's will be provided for connecting to the inner power and ground planes. Some of the layouts will also include bypass capacitors and terminating - pull down resistors. The various layouts will include: 1003xx ECL a 28 pin layout to accept any 1003xx type. 100398 ECL fully wired with power and ground connections and with termination and pull down resistors. 74ALS04 TTL in an SOIC package to buffer the VME AS* and the VME DTACK signals. Sections of this chip that are not used for these VME buffers are brought out to via's. TTL and ECL in a 0.3 or 0.4 inch through hole DIP package. All sections of this chip are brought out to via's. LED's LED's and drivers for them. I/O Pins The I/O pins for the proto-type area will come from rows "D" and "E" of the J2 connector. Via's Power and Ground Via's. Via's to supply ECL voltage HI and LOW Extra 20 pin x 0.3" through hole layout areas for resistors. Rock Layout pads for a 50 MHz rock. Instructions for configuring the 100398: The 100398 as a Differential ECL to TTL Receiver with no latching and the TTL outputs always enabled: Latch Enable TTL LOW Direction Control TTL LOW Output Enable TTL HI The 100398 as a TTL to Differential ECL Driver with no latching and the ECL outputs always enabled: Latch Enable TTL LOW Direction Control TTL HI Output Enable TTL HI ########################################################################### ########################################################################### TOM Parts Ordering Information LED, 3 LED's in one package, Dialight 564-2210-111, Newark 96F2274, pg 221 Switch, miniature pushbutton SPDT, C&K EP12SD1AVBE, Newark 44F1749, pg 396 Oscillator, 50 MHz Crystal Osc, Dale XO-43B-50.0, Newark 44F4221, pg 370 Test Jacks, RED, Johnson type 105-1102-001, Newark 81F4446, pg 1008 Test Jacks, BLACK, Johnson type 105-1103-001, Newark 81F4447, pg 1008 Test Jacks, GREEN, Johnson type 105-1104-001, Newark 81F4448, pg 1008 Test Jacks, ORANGE, Johnson type 105-1106-001, Newark 81F4449, pg 1008 Test Jacks, YELLOW, Johnson type 105-1107-001, Newark 81F4450, pg 1008 Header, 34 pin right angle solder tail 4 wall no ejection latch AMP Part Number 103311-7 Newark 90F7748 pg 817 Capacitor, Tantalum 4.7 uFd 25 Volt, KEMET T491C475K025AS Newark 93F2424 pg 334 1 pn-big_pcap 4 Aluminum Electrolytic C93, C94 2200 uFd 16 Volt, C95, C96 CDE # 201I222P016XX SN 74 HC 00 D Texas Instruments SN 74 F 02 D Texas Instruments SN 74 ALS 04 BD Texas Instruments SN 74 HCT 04 D Texas Instruments SN 74 F 38 D Texas Instruments SN 74 LS 123 D Motorola / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | / - \ | Standard Setups on TOM Board -------------------------------- Initial Rev. 27-JAN-1999 Most Recent Rev. 1-FEB-1999 Setup for Crystal Oscillator ---------------------------- This will use a standard 14 pin DIP crystal oscillator in the provided socket to generate a differential ECL output on J2 Pins D32 and E32. Pin D32 is the direct output and E32 in the complement output. To implement this make the following connections: Osc out to U160 T2 Oscillator TTL siganl going to the translator Osc Gnd to G near U160 T2 Twist this with the above wire. R160 2N to J2 E32 Direct ECL Output to J2 pin E32 R160 2I to J2 D32 Complement ECL Output to J2 pin D32 Twist the two above wires together. U160 Latch to G near U160 Tie U160's Latch control input to Ground. U160 Dir to C near U160 Tie U160's Direction control input to Vcc. U160 OE to C near U160 Tie U160's Output Enable control input to Vcc. Install 56 Ohm 6 pin bused SIP resistor networks at R160 and R161. Setup to provide a copies of the VME IRQ4* signal ------------------------------------------------- This setup will provide a TTL copy and a differential ECL copy of the IRQ4* signal on the VME backplane where the TOM card is installed. It also illuminates the lower lefthand LED. J1 E27 to U70 P3 Connect VME IRQ4* to U70 inverter input. U70 P4 to: U70 P5 Connect the IRQ4 signal from the inverter output to the next inverter input. U160 T3 Also connect the IRQ4 signal to the TTL to ECL translator input. LED4 Also connect the IRQ4 signal to the LED #4 input. U70 P6 to U70 P9 Connect the output of the second inverter to the input of the third inverter. U70 P8 via 56 Ohm Resistor to J2 E1 Connect the output of the third inverter via a 56 Ohm Resistor to J2 pin E1. This sends a TTL copy of this crates VME IRQ4 off the TOM. GND to J2 D1 Provide a grounded pin to pair with J2 E1 above. R160 3N to J2 E3 Connect the output of the TTL to ECL translator R160 3I to J2 D3 to backplane pins J2 E3,D3 via twisted pair. This send a copy of this crates VME IRQ4 off the TOM as a differential ECL signal.