12-Dec-2000

In addition to placing components by hand, there are a couple of other
techniques to improve the timing of a design.  The Xilinx software
allows for multi pass place and route (under the design menu option).
This means that the software will repeatedly place and route the
design, starting with a different cost table each time.  The cost
table is related to the initial placement of components and can affect
whether or not the design ultimately meets the timing constraints.
Once a preferred cost table has been identified, it is possible to
specify that cost table if the design is modified and a new exo is
needed.  Having tried the first 10 cost tables, cost table 1 (the
default) still seems to give the best result for the L1 TRM.

If a specific net or bus is particularly slow, adding the pri property
to the net in Mentor may help.  A higher number means a greater
priority which in turn means that Xilinx will make more of an effort
to place these nets on longlines, avoid route-throughs, etc.  On the
L1 TRM, for instance, putting a priority of 94 on a bus improved the
timing for those paths failing the FIFO fall through timing constraint
by about 0.5 ns.  (See also constraint_performance_of_aonm.txt in the
aonm directory on the web.)

The Xilinx software now includes a floorplanner (under the tools
menu).  We really used this yet.  The Xilinx documentation is
available at file:/home/xilinxm2.1/doc/usenglish/index.htm on desmo.
My understanding is that it's possible to run the design as usual,
view the placed and routed design and tweak it to try and improve the
timing, and then run it again to see the effect of your changes.  I
did have a peek at 3.1 of the L1 TRM, specifically the paths which
were failing to meet the timing constraints.  The relevant inputs are
on the upper left and the outputs are on the upper right.  (Putting
the cursor over a block produces an identifying label near the bottom
of the screen.  Pushing the left mouse button will show the nets into
and out of that block.  The row and column number of the CLB are shown
on the bottom right of the screen.)  The 5 vertical, purple rectangles
at the top, middle are the DPRAM as is the light blue rectangle just
to the right of the last purple rectangle.  Two of the vertical olive
green rectangles to the right of that are the read and write counters.
The hot pink blob a bit to the right of the RAM and just a bit left of
the read counter is the output mux.  I haven't looked closely at the
design, but at least the logic that is currently failing the timing
constraints looks more-or-less reasonably placed - it's not scattered
all over the far side of the FPGA relative to the inputs and outputs.

In the past, we have used another Xilinx program, epics (second icon
from the bottom on the right tool bar), to look at the design.  This
program seems to now be called the Xilinx FPGA Editor.  The list on
the right allows you to see and select specific components.  One
benefit of this program is that it shows you the actual routing of the
nets so you can check for excessively long paths or route throughs.  I
didn't see this feature in the 30 seconds I spent playing with the
floor planner.  Other than that, there doesn't seem to be much reason
to use this program - the floorplanner seems more user friendly, even
if all you want to do is look at the design.

When we were using epics, we did the hand placing in the user
constraint file.  In the case of the AONM, we specified regions for
the various components, e.g. 
 
INST "ao_lup/aoit_31_0/aoit_15_0/lup_3_0" LOC = CLB_R15C1:CLB_R16C4 ; 

This allowed us to group the various bits of logic closely together
while still allowing Xilinx some flexibility.  Note that this requires
a new revision but not a new version since the edif net list hasn't
changed.  

One possible way forward in the case of the L1 TRM would be to use the
floorplanner to determine the preferred layout, but then to apply the
placement constraint in the ucf rather than trying to change things
"on the fly" in the floorplanner itself.  Alternatively it should be
possible to reposition components directly in the floorplanner.