***************************** * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * * and * * * * Level 2 Trigger Framework * * * * Level 2 * * Term Receiver Module FPGA * * * ***************************** Original: 2-DEC-1997 Latest: 6-APR-2000 Introduction ------------ The Term Receiver Module FPGA is used in all MSA FPGA locations on the L2 Term Receiver Module cards. Each Term Receiver Module FPGA has the following input and output connections: 1. On-Card Bus (including High-Quality Timing Signals). 2. High-Speed Readout Interface. 3. 4 Subsystem Input Input Terms (these are Main Signal Array (MSA) Input Signals). 4. 1 Subsystem Strobe signal (this is an MSA Input Signal). 5. 4 Isochronous Output Terms (these are MSA Output Signals). The purpose of this FPGA is to receive 4 Input Terms (e.g. L2 Global Answers, L1 Specific Trigger Fired), buffer them in a FIFO, and provide them to the Level 2 Framework in an isochronous fashion. Some state readout (via HSRO and Monitor Readout) and scalers (readout via Monitor Readout) are also provided. Operation--General Comments --------------------------- This FPGA is used for several functions in the Level 2 Trigger Framework: 1. receiving L2 Global Answers from L2 Global 2. receiving L1 Specific Trigger Fired Mask from L1 Framework 3. receiving Auxiliary data from L1 Framework This FPGA was originally a programmable "mode" of the L1 TRM FPGA, but this became unwieldy due to the differences in processing required by the various L1 Modes and the L2 Mode. Therefore this design was split off into a separate (but very similar) FPGA. The Term Receiver Module FPGA is composed of the following elements: 1. On-Card Bus Interface 2. High-Speed Readout Interface 3. 32 Stage FIFO for 4 Input Terms, consisting of: A. 32 x 4 FIFO B. Programmable FIFO Error Detection logic 4. FIFO Bypass Data Path (D-Latch Mode) 5. Two Test Data Registers 6. Output Term Source Selection 7. Output Term Latches and Drivers 8. Output Term State Recording logic 9. Output Term Scaler logic Each element is described below. 1. On-Card Bus Interface This is the standard On-Card Bus Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. 2. High-Speed Readout Interface This is the standard High-Speed Readout Interface from the MSU FPGA Common Block Library. Its operation is described elsewhere and will not be repeated here. It is not actually used in L2 applications but is left from the L1 TRM FPGA. 3. 32 Stage FIFO for 4 Input Terms (plus Gap) The heart of this FPGA is a 32 stage FIFO, consisting of: A. 32 x 4 FIFO B. Programmable FIFO Error Detection logic 3.A 32 x 4 FIFO The incoming Input Terms are stored in a 32 stage by 4 bit wide FIFO. The depth of this FIFO is set by the maximum L2 Buffer Depth of 16 events awaiting L2 Decisions. This FIFO is built using 4 32x1 dual-port RAM's (from the Xilinx component library), with additional control logic (write address counter, read address counter, empty/full condition detection, etc.) as needed. Data is written into the FIFO on the rising edge of the Input Strobe (which accompanies the incoming Input Terms on the P2/P3 backplane connectors). Writing data into the FIFO increments the Write Address by 1, in preparation for the next write (i.e. this new incremented address indicates which RAM location will be written to on the NEXT Input Strobe rising edge). Data is read from the FIFO and latched (in the Output Term Latch, described below) on the rising edge of the TRM Clock. The Read Clock is a HQ Timing Signal. Reading data from the FIFO increments the Read Address by 1, in preparation for the next read (i.e. this new incremented address indicates which RAM location's data will be latched on the NEXT TRM Clock rising edge), providing for the most rapid clock-to-output data path, since it is not necessary to wait for the counter to increment and the RAM to be addressed, but only for the D-latch to update. Note that the Read Clock must be qualified by a Read Enable (also an HQ Timing Signal). This is because the Read Clock is a BX-rate clock, but the Read Enable is only active once per L2 Cycle. The Read and Write Addresses can both be forced to zero by the normal reset mechanism (Timing Signal or TCC Forced). No phase relationship is assumed between the Input Strobe and the TRM Clock. 3.B Programmable FIFO Error Detection logic The FIFO must be capable of detecting two different error conditions in all applications: 1. FIFO Full: if, following a Write, the Write Address is equal to the Read Address, the FIFO is Full and cannot accept another Input. A Write request under these conditions is a "FIFO Full" error. 2. FIFO Empty: if, following a Read, the Read Address is equal to the Write Address, the FIFO is Empty and cannot provide another Output. A Read request under these conditions is a "FIFO Empty" error. Note that correctly processing these errors requires "knowing" whether the last action was a Write or a Read. This is done by watching the Write Address and Read Address directions, see Xilinx App. Note XAPP 051. The Gap error detection logic in the L1 TRM FPGA is omitted in the L2 TRM FPGA. All of these checks can be ignored, via writes to a control register. The FIFO Empty/Full checks must be performed in all applications, and should not be turned off. Any error that occurs is latched into a status register. This register can either be cleared via a TCC write, or automatically cleared when the FIFO counters are reset by a TCC write or Timing Signal Reset. If any error occurs, this FPGA pulls the Chip Status signal to the VME Interface FPGA, which will result in the VME Interface FPGA requesting an interrupt via the VME bus (if interrupts are enabled). This is how TCC is informed of a FIFO error. Note that the Chip Status signal is also used to indicate FIFO Not Empty to the L2 Helper. The Chip CSR controls whether the Chip Status Signal indicated FIFO Error or FIFO Not Empty. Several states and scalers are recorded for monitoring readout to help characterize the system operation and diagnose errors. At the system level, once an error is detected, TCC must become involved to diagnose the error and process it. The L2 TRM FPGA has a "Maginot Line" input which works exactly like the L1 TRM FPGA "Maginot Line" input, at this time the L2 Helper FPGA simply holds it low. This "Maginot Line" loop is not part of the TRM FPGA functionality, but rather part of the system-level services provided to the FPGA. 4. FIFO Bypass Data Path (D-Latch Mode) Many L1 TRM applications (Individual/Global/Front-End Busy Disables) do not require the above-described FIFO. For these applications, a FIFO Bypass mode, in which the Input Terms directly become the Output Terms (which are latched by the TRM Clock P1 Timing Signal as described below). This latching is required because the downstream Framework logic expects its inputs to change only at discrete, specified "phases" in the tick. This mode is not used in L2 applications, but remains in the L2 TRM FPGA. 5. Two Test Data Registers The TRM FPGA has two separate Test Data Registers, programmable via TCC. Each of these registers contains a 4-bit pattern to which the 4 Output Terms can be driven, again under TCC control. These data registers are called the A and B Test Data Registers, and are used both for system testing and also for forcing the output to a known state during (for example) system startup or a FIFO synch error. The details of Output Term source selection are provided in the following section. 6. Output Term Source Selection The TRM Output Term source selection logic is made up of a pair of multiplexers. The first mux is under TCC control via VME register access, and the second is controlled by the Maginot Line P1 Timing Signal. They are arranged as shown below: Maginot Line P1 TS -----------. | Output Mux Control Reg | | | .-------. | FIFO Bypass -/--| | | 4 | 4-bit | | | | .-------. FIFO --------/--| 3:1 |-/---| | 4 | | 4 | 4-bit | | mux | | | TDR A -------/--| | | 2:1 |-/-- Output Terms 4 `-------' | | 4 (to Output Term | mux | Latches and TDR B -------/----------------| | Drivers) `-------' If the Maginot Line P1 Timing Signal (see above sections for details) is LOW, then TCC can select (at VME register access speed) either the FIFO, FIFO Bypass, or Test Data Register A Output Terms. If the Maginot Line is HIGH, then the Output Terms come from Test Data Register B, regardless of the "upstream" mux programming. During normal physics running, TCC would select either the FIFO or FIFO Bypass Output Terms (depending on the particular TRM application), and program Test Data Register B with all zeros. The Maginot Line would typically be LOW (allowing the selected Output Terms to be driven off-chip), but would go HIGH in the event of a FIFO synch error, causing the all-zero Output Terms from TDR B to be driven off-chip. During system testing, TCC would select Test Data Register A, and control the Maginot Line (via a helper channel) to alternate between driving TDR A and TDR B off-chip. This would allow "single-chance" system testing, by sending a long string of, e.g. TDR A, with a single tick of TDR B interposed. By asserting the Capture Monitor Data P1 Timing Signal at a controlled time following the "TDR B" tick, the results of the TDR B Output Terms can be captured and analyzed. During testing, the Output Terms must change at the same "phase" of the tick as they would during normal running. Rather than trying to precisely control the timing of the Maginot Line, the Output Terms (regardless of source) are all latched as described in the following section. 7. Output Term Latches and Drivers Regardless of the source of the Output Terms, they are all latched (on the rising edge of the TRM Clock P1 Timing Signal) before being driven off-chip. The reasons for latching the FIFO and FIFO Bypass mode Output Terms are described above. The reason for latching the Output Terms when they come from Test Data Registers is more subtle. During system testing, it is desirable for the Output Terms to change at the same "phase" of the tick as they do during normal running. If the Output Terms coming from Test Data Registers were not latched, then the Maginot Line P1 Timing Signal would need to switch at a very precise time to emulate the real system timing. Latching the Output Terms in all cases eliminates this system-level concern. Note that the Output Term Latches only are updated when the Read Enable P1 Timing Signal is active. This is unlike the L1 TRM FPGA logic, which has no Read Enable signal. 8. Output Term State Recording logic The 4 Output Terms (regardless of source) are available for readout via both the HSRO readout mechanism and the Monitor Readout mechanism. The data capture and readout are performed in the standard fashion, described elsewhere. 9. Output Term Scaler logic Additionally, each Output Term (again, regardless of source) is fed to its own 32-bit scaler, which is incremented on every tick during which the Output Term is HIGH. Again, if Test Data Mode is selected, the Test Data, and not the FIFO output, act as the scaler gates. These scalers can be reset via a HQ Timing Signal. The 32-bit values from these scalers are available via Monitor Readout, again the capture and readout are performed in the standard fashion. Programming Interface --------------------- The Per-Bunch Scaler FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R/W Chip Control Status Register (LSW) 1 R/W Chip Control Status Register (MSW) 2 R/W Scaler Timing Signal Reset Enable Register 3 R/W Scaler Force Reset Register 8 R/W FIFO Control Status Register 9 R FIFO Error Reporting Register 10 R FIFO Counter Status Register 12 R/W Test Data Register A 13 R/W Test Data Register B 16 R/W Output Term Source Selection Register 24 R HSRO State 25 R/W HSRO Terminal Count 26 R HSRO Current Count 32 R/W Tick History Shift Register Control Reg 36 R Monitor Readout copy of HSRO States 40 R Output Term 0 Scaler Monitor Register (LSW) 41 R Output Term 0 Scaler Monitor Register (MSW) 42 R Output Term 1 Scaler Monitor Register (LSW) 43 R Output Term 1 Scaler Monitor Register (MSW) 44 R Output Term 2 Scaler Monitor Register (LSW) 45 R Output Term 2 Scaler Monitor Register (MSW) 46 R Output Term 3 Scaler Monitor Register (LSW) 47 R Output Term 3 Scaler Monitor Register (MSW) The bit allocation in each of these registers is: Chip Control Status Register LSW (Register Address 0) Bit Access Contents --- ------ -------- 0 R/W Chip Interrupt Enable ('1': interrupts enabled) 1 R/W Internal Interrupt Request ('1': on-chip logic is requesting an interrupt, regardless of the Chip Interrupt Enable, this is the logical OR of all enabled sources of Internal Interrupt Request) 2 R Chip Status Signal (Interrupt Request Status) (logical AND of Chip Interrupt Enable and Chip Interrupt Request--this is the logical INVERSE of the Chip_Status*(x) signal from this chip to the VME Interface FPGA) 3 R/W Enable Latched_FIFO_Error to generate Internal Interrupt Request 4 R Latched_FIFO_Error generating Internal Interrupt Request (AND of Latched_FIFO_Error and the above control bit) 5 R/W Enable FIFO_Not_Empty to generate Internal Interrupt Request (NOTE: FIFO_Not_Empty should *not* be used to generate VME Interrupts because it is not latched. This is used only in L2 applications, where the "Interrupt Request" goes out via P5 not via VME. To accomplish this, disable VME Interrupt Generation from this card in the VME FPGA Board CSR) 6 R FIFO_Not_Empty generating Internal Interrupt Request (AND of FIFO_Not_Empty and the above control bit) 7:15 --- not allocated The Chip Status Register MSW is currently unused. Scaler Timing Signal Reset Enable Register Bit Access Contents --- ------ -------- 0 R/W Enable Timing Signal Reset for Output Term 0 Scaler 1 R/W Enable Timing Signal Reset for Output Term 1 Scaler 2 R/W Enable Timing Signal Reset for Output Term 2 Scaler 3 R/W Enable Timing Signal Reset for Output Term 3 Scaler 4 R/W Enable Timing Signal Reset for FIFO Address Counters 15:5 R/W Unallocated Scaler Force Reset Register Bit Access Contents --- ------ -------- 0 R/W Force Reset for Output Term 0 Scaler 1 R/W Force Reset for Output Term 1 Scaler 2 R/W Force Reset for Output Term 2 Scaler 3 R/W Force Reset for Output Term 3 Scaler 4 R/W Force Reset for FIFO Address Counters 15:5 R/W Unallocated FIFO Control Status Register Bit Access Contents --- ------ -------- 0 R/W Enable "FIFO Full" Error Checking 1 R/W Enable "FIFO Empty" Error Checking 7:2 R/W Unallocated 8 R/W Enable Automatic Error Clearing 9 R/W Manually Clear Errors (Only meaningful when Automatic Error Clearing is disabled. TCC must pulse this bit high and then back low again) 15:10 R/W Unallocated FIFO Error Reporting Register Bit Access Contents --- ------ -------- 0 R FIFO Full Error (Latched) 1 R FIFO Empty Error (Latched) 7:2 R Unallocated 8 R FIFO Error Flag (logical OR of bits 1:0) 15:9 R Unallocated FIFO Counter Status Register Bit Access Contents --- ------ -------- 4:0 R FIFO DPRAM Write Address (see note below) 7:5 R Unallocated 12:8 R FIFO DPRAM Read Address (see note below) 15:13 R Unallocated FIFO DPRAM Write/Read Addresses do NOT progress in standard binary sequence. They progress in a modified Grey code as follows: 0 0x00 00000 (reset state) 1 0x01 00001 3 0x03 00011 7 0x07 00111 6 0x06 00110 5 0x05 00101 2 0x02 00010 4 0x04 00100 8 0x08 01000 9 0x09 01001 11 0x0b 01011 15 0x0f 01111 14 0x0e 01110 13 0x0d 01101 10 0x0a 01010 12 0x0c 01100 24 0x18 11000 25 0x19 11001 27 0x1b 11011 31 0x1f 11111 30 0x1e 11110 29 0x1d 11101 26 0x1a 11010 28 0x1c 11100 16 0x10 10000 17 0x11 10001 19 0x13 10011 23 0x17 10111 22 0x16 10110 21 0x15 10101 18 0x12 10010 20 0x11 10100 0 0x00 00000 (sequence begins again) Test Data Register A/B Bit Access Contents --- ------ -------- 3:0 R/W Output Term 3:0 15:4 R/W Unallocated Output Source Selection Register Bit Access Contents --- ------ -------- 1:0 R/W Output Source Select ('00': FIFO Bypass '01': FIFO '10': Test Data Register A '11': Undefined) 15:2 R/W Unallocated HSRO State Bit Access Contents --- ------ -------- 0 R HSRO_DCE_IN* 1 R HSRO_DCE_OUT* 2 R Enable_HSRO_Data 15:3 R not allocated HSRO Terminal Count Bit Access Contents --- ------ -------- 3:0 R/W Number of Words for High-Speed Readout (MUST be greater than 0 if chip HSRO is enabled) 14:4 R/W not allocated 15 R/W Enable HSRO from this Chip (0: DCE_In* passes directly through to DCE_Out* 1: DCE_Out* is generated by the terminal count comparator) Tick History Shift Register Control Reg Bit Access Contents --- ------ -------- 2:0 R/W Depth in stage 1 of BXHSR 15:3 R/W unallocated Output Term Scaler Monitor Registers Bit Access Contents --- ------ -------- 15:0 R Scaler MS Word / LS Word as appropriate Output Term State Monitor Register Bit Access Contents --- ------ -------- 0 R Output Term 0 State: NT NT Previous L2 Cycle 1 R Output Term 1 State: NT NT Previous L2 Cycle 2 R Output Term 2 State: NT NT Previous L2 Cycle 3 R Output Term 3 State: NT NT Previous L2 Cycle 4 R Output Term 0 State: Next to Previous L2 Cycle 5 R Output Term 1 State: Next to Previous L2 Cycle 6 R Output Term 2 State: Next to Previous L2 Cycle 7 R Output Term 3 State: Next to Previous L2 Cycle 8 R Output Term 0 State: Previous L2 Cycle 9 R Output Term 1 State: Previous L2 Cycle 10 R Output Term 2 State: Previous L2 Cycle 11 R Output Term 3 State: Previous L2 Cycle 12 R Output Term 0 State: Current L2 Cycle 13 R Output Term 1 State: Current L2 Cycle 14 R Output Term 2 State: Current L2 Cycle 15 R Output Term 3 State: Current L2 Cycle