*****************************
                     *                           *
                     *   D-Zero Run II Upgrade   *
                     *                           *
                     * Level 1 Trigger Framework *
                     *                           *
                     *            and            *
                     *                           *
                     * Level 2 Trigger Framework *
                     *                           *
                     *Static HSRO Event Data FPGA*
                     *                           *
                     *****************************



						Original:  4-MAY-2000
						 Current: 31-JUL-2000

Introduction
------------

The Static HSRO Event Data (SHED) FPGA provides an easy way to include
up to eight, 16-bit fixed (or very slowly changing) words into the
HSRO data block.  For example, this is how the luminosity interval
will be inserted into the data block.  It may also be useful during
initial HSRO testing.

This FPGA lives on the Global Disable TRM in M123 Top, Slot 20.  At
the moment only MSA FPGA's 1,2,5, and 6 are used on this card so there
are plenty of free FPGA's, and its HSRO is not heavily used.  FPGA 9
will be configured with the SHED FPGA.

The SHED FPGA has the following input and output connections:

	1. On-Card Bus (including High-Quality Timing Signals)


Functionality
-------------

The SHED FPGA is composed of the following elements:

	1. On-Card Bus

	2. Block of Registers

	3. High-Speed Readout Interface

Each element is described below:

1. On-Card Bus Interface

	This is the standard On-Card Bus Interface from the MSU FPGA
	Common Block Library.  Its operation is described elsewhere
	and will not be repeated here.

2. Block of Registers
	
	This is a set of eight, 16-bit registers that can be written
	and read by TCC.  TCC can choose to include from 0 to 8 of
	these registers in the HSRO data block, but it is always the
	first x registers which are readout, e.g. if only 4 registers
	are readout, it will be registers 3:0.

	The data from these registers is captured in the usual fashion
	(with the rising edge of the Tick Clock when Capture HSRO Data
	is asserted) but doesn't go through a beam crossing history
	shift register.

3. High-Speed Readout Interface

	This is the standard High-Speed Readout (HSRO) Interface from
	the MSU FPGA Common Block Library.  Its operation is described
	elsewhere and will not be repeated here.


Programming Interface
---------------------

The SHED FPGA has the following VME-visible registers:

    Reg             Register
    Addr    Access  Contents
    ----    ------  --------
       0     R/W    Chip Control Status Register (LSW)
       1     R/W    Chip Control Status Register (MSW)

    15:8     R/W    Data Registers 7:0

      24      R     HSRO State
      25     R/W    HSRO Terminal Count
      26      R     HSRO Current Count


The bit allocation in each of these registers is:

Chip Control Status Register LSW (Register Address 0)

    Bit    Access   Contents
    ---    ------   --------
     0      R/W     Chip Interrupt Enable
                        ('1': interrupts enabled)

     1      R/W     Chip Interrupt Request
                        ('1': request interrupt)

     2      R       Chip Status Signal (Interrupt Request Status)
                        (logical AND of Chip Interrupt Enable and
                         Chip Interrupt Request--this is the logical
                         INVERSE of the Chip_Status*(x) signal from
                         this chip to the VME Interface FPGA)

  3:15      ---     not allocated

The Chip Status Register MSW is currently unused.

HSRO State

    Bit     Access  Contents
    ---     ------  --------
     0        R     HSRO_DCE_IN*

     1        R     HSRO_DCE_OUT*

     2        R     Enable HSRO_Data

   15:3       R     not allocated

HSRO Terminal Count

    Bit     Access  Contents
    ---     ------  --------
    3:0      R/W    Number of Words for High-Speed Readout
                    (MUST be greater than 0 if chip HSRO is enabled)

   14:4      R/W    not allocated

     15      R/W    Enable HSRO from this Chip
                    (0: DCE_In* passes directly through to DCE_Out*
                     1: DCE_Out* is generated by the terminal count
                        comparator)