*****************************
                     *                           *
                     *   D-Zero Run II Upgrade   *
                     *                           *
                     * Level 1 Trigger Framework *
                     *                           *
                     *        Test Source        *
                     *                           *
                     *      FPGA Description     *
                     *                           *
                     *****************************

                                                Original:  7-DEC-1995
                                                  Latest:  7-DEC-1998 

Introduction
------------
    
The Source FPGA is for use in testing the inputs to a TRM.  The Source
FPGA provides 18 output signals: 16 data signals, 1 gap signal, and a
strobe.  The data signals and the gap come as a block of 17 signals
from one of two source registers; the source register is selected by a
High Quality Timing Signal.  All 17 outputs from the register are
captured for monitor readout.  The strobe is simply a copy of a second
High Quality Timing Signal.

At the moment, this design is implemented for MSA FPGA #4 of an FM.

Programming Interface
---------------------

The Source FPGA has the following VME-visible registers:

    Reg            Register
    Addr  Access   Contents
    ----  ------   --------
       0   R/W     Chip Control Status Register (LSW)
       1   R/W     Chip Control Status Register (MSW)

     5:4   R/W	   Register A Data
     7:6   R/W	   Register B Data

       8   R/W     Tick History Shift Register Control Reg     

    10:9    R      Monitor Readout copy of States Next+1 Tick     
    10:9    R      Monitor Readout copy of States Next Tick     
    10:9    R      Monitor Readout copy of States Triggered Tick     
    10:9    R      Monitor Readout copy of States Previous Tick     

The bit allocation in each of these registers is:

Chip Control Status Register LSW (Register Address 0)

    Bit    Access   Contents
    ---    ------   --------
     0      R/W     Chip Interrupt Enable
                        ('1': interrupts enabled)

     1      R/W     Chip Interrupt Request
                        ('1': request interrupt)

     2      R       Chip Status Signal (Interrupt Request Status)
                        (logical AND of Chip Interrupt Enable and
                         Chip Interrupt Request--this is the logical
                         INVERSE of the Chip_Status*(x) signal from

  15:3      ---     not allocated

The Chip Status Register MSW is currently unused.

Register A Data

    Bit    Access   Contents
    ---    ------   --------
   16:0      R/W     Register A Data

   31:17     R/W     not allocated

Register B Data

    Bit    Access   Contents
    ---    ------   --------
   16:0      R/W     Register B Data

   31:17     R/W     not allocated


Tick History Shift Register Control Reg

    Bit     Access  Contents
    ---     ------  --------
    2:0       R/W   Depth in stage 1 of BXHSR

   15:3       R/W   unallocated

Monitor Readout copy of States

    Bit     Access  Contents
    ---     ------  --------
    16:0       R    Output Data for Specified Tick
	
    31:17	    unallocated