***************************** * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * * Term Receiver Module * * * ***************************** Original: 31-MAY-1995 Latest: 26-MAR-1998 Introduction ------------ The Term Receiver Module (TRM) is used in the Level 1 Trigger Framework. It has the following functions: 1) Receive a subset of the And-Or Input Terms (AOIT's) from Level 1 Trigger subsystems (e.g. L1 Calorimeter Trigger) 2) De-skew these AOIT's and present them isochronously to the rest of the Level 1 Trigger Framework 3) Store these de-skewed AOIT's in a Beam Crossing History Shift Register for subsequent Data Block and Monitoring readout 4) Scale the de-skewed AOIT's for Monitoring readout 5) Inject "test data" (rather than the actual AOIT's from the L1 Trigger Subsystems) into the L1 Trigger Framework. There are 11 TRM's in the L1 Trigger Framework. Four are used to service the 256 And-Or Input Terms, 2 for the 128 Geographic Section Front-End Busies, 4 for the 256 Per-Specific Trigger Disables (2 of these Disables exist for each of the 128 Specific Triggers), and 1 for Global Disables. Each TRM has the following connections to the experiment: (1) Real-time inputs Main Signal Array Inputs: - 64 Subsystem And-Or Input Terms, divided into 4 groups of 16 - 4 Gap Markers (one per group of 16 AOIT's) - 4 Strobe signals (one per group of 16 AOIT's) - 56 spare signals, routed as described below P1 Timing Signals: - BX Clock - Capture Monitor Data signal - Capture HSRO Data signal (2) Real-time output Main Signal Array Outputs: - 64 Framework (Isochronous) And-Or Input Terms (3) Programming information - 64 Test And-Or Input Terms - Test vs. Subsystem And-Or Term Mode flag (4) Data Block readout information - 64 And-Or Input Terms from the Triggered Beam Crossing - 64 And-Or Input Terms from the previous-to-Triggered BX - 64 And-Or Input Terms from the next-after-Triggered BX (5) Monitoring readout information - 64 And-Or Input Term Scalers - all Data Block readout information Operation --------- The primary functions of the TRM are receiving and de-skewing the And-Or Input Terms from the Level 1 Trigger Subsystems. Recall that the various L1 Trigger subsystems have differing latencies. The TRM uses FIFO's to synchronize the And-Or Input Terms. Use of FIFO's (rather than a simple pipeline), with input clocks provided by L1 Trigger Subsystems, frees us of the need to predetermine the latency of each L1 Trigger Subsystem or constantly adjust Framework timing to compensate for changes in L1 Trigger Subsystem timing. For input purposes, the TRM is divided into 4 independent 16-bit-wide FIFO's, each with its own And-Or Term Input Clock and Write Counter. On the output side, all 4 FIFO's are addressed in parallel to provide an isochronous set of And-Or Input Terms to the subsequent L1 Trigger Framework logic. The FIFO's work as follows: - on every Subsystem And-Or Input Term Strobe rising edge: - store the associated 16 And-Or Input Terms in the 16-bit FIFO - increment the Write counter for the 16-bit FIFO - verify that the FIFO has not overflowed (if it has, flag an error) - on every Framework And-Or Input Term Clock rising edge outside the Sync Gap (as seen at the L1 Framework time skew): - verify that there is at least one entry available (i.e. the Read counter > Write counter) in each of the 4 FIFO's (if not, flag an error) - latch the oldest entries (i.e. those pointed to by the Read counter) in all 4 FIFO's and drive them off-card - increment the Read counter (which is common to all 4 FIFO's - on the First "Beam Crossing" of the Sync Gap (as seen at the L1 Trigger Subsystem time skew): - verify that all 8 Write counters and the Read counter are equal (if not, flag an error and reset all 8 Write counters and the Read counter to 0) - (optionally) always reset all 8 Write counters and the Read counter to 0 The FIFO length is driven by the maximum L1 Trigger Subsystem latency, which has an upper bound of 25, 132 ns clock ticks. The FIFO's may be circular in nature, wrapping between gap resets. Additionally, the TRM must record the Framework AOIT's for Data Block readout. These AOIT's must be stored in a Beam Crossing History Shift Register (separate from the FIFO described above) to account for the latency of the L1 Trigger Framework, and L1 Accept distribution network. This Beam Crossing History Shift Register is on the order of 3-4 stages long. The number of stages is fixed in the FPGA configuration and is not programmable via TCC. The AOIT information in the Data Block is also available for Monitoring readout via the VME bus. The TRM also scales the And-Or Input Term rate. These scalers, like the state recording, are on the Framework side of the FIFO. These scalers are 32 bits and the values are available for Monitoring readout via the VME interface. These scalers in the Monitor Data will be isochronous with the AOIT state information in the Monitor Data. This requires either the output of the scalers, or (more cleverly) the clock to the scalers, to be recorded in a Beam Crossing History Shift Register. The TRM has a 64 bit wide Test Data Register, to store Test AOIT's which can be sent to the rest of the L1 Trigger Framework in place of the Subsystem AOIT's. This Test Data Register is programmable via TCC. TCC is also able to select between Test Data and Subsystem Data. The captured data is read out via the VME bus at normal VME speed via normal VME cycles. This reading will necessarily span multiple Beam Crossings, so new Monitor data must not be captured during this readout. The scalers on this card must be resettable. The reset mechanism is yet to be defined. It will probably be one of: - a parallel timing signal (would reset all Channels simultaneously) - a VME write to some particular register (could either reset all Channels simultaneously or could have individual per-Channel resets) Implementation -------------- The TRM will be implemented on THE card. This card is clearly bound by output connector pin count rather than input pins or logic capacity. All 16 FPGA's on this card will be configured identically. Thus each FPGA will service 64/16 = 4 And-Or Input Terms. Note that this means that the logical 16-bit FIFO's described above are actually implemented using 4, 4-bit FIFO's split between 4 FPGA's. The FPGA's are described below: FPGA's ------ Each AONM FPGA has the following inputs and outputs: 1) Fast inputs - 4 Subsystem And-Or Input Terms - Subsystem And-Or Input Term Strobe - Framework And-Or Input Term Clock - Gap Marker - Capture Data Block Data signal - Capture Monitor Data signal - Beam Crossing Marker 2) Fast outputs - 4 Framework And-Or Input Terms 3) On-card bus interface ------------------------------------------------- Recall which FPGA Site Handles which And-Or Terms ------------------------------------------------- Remember that a TRM card (like a TDM card) has a "transposed" mapping of which FPGA site handles which signals. "Normal" TRM And-Or Card Card Term FPGA Site FPGA Site ------ --------- --------- 0:3 1 -> 1 4:7 2 -> 5 8:11 3 -> 9 12:15 4 -> 13 16:19 5 -> 2 20:23 6 -> 6 24:27 7 -> 10 28:31 8 -> 14 32:35 9 -> 3 36:39 10 -> 7 40:43 11 -> 11 44:47 12 -> 15 48:51 13 -> 4 52:55 14 -> 8 56:59 15 -> 12 60:63 16 -> 16 ------------- SPARE SIGNALS ------------- There are 56 unrouted MSA_IN signals on the TRM, 14 associated with each of the four groups of input terms. Unused ------ 16 of the spare signals, 4 from each input group, are terminated at vias near the resistor packs at the top of the board. MSA_IN ------ 44,45,46,47 60,61,62,63 108,109,110,111 124,125,126,127 Per Column ---------- 8 signals, 2 from each input group, are routed to one of four columns of FPGAs. Each pair from an input group is routed to a unique column. Column FPGA MSA_IN ------ ---- ------ 1 1,5,9,13 34,35 2 2,6,10,14 50,51 3 3,7,11,15 98,99 4 4,8,12,16 114,115 Per FPGA -------- 16 signals, 4 from each input group, are routed to individual FPGAs. The 4 signals associated with a group are routed the the FPGAs in the same column that the per column spares for that group are routed to. FPGA | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ------|----------------------------------------------------------------- MSA_IN| 40 56 104 120 41 57 105 121 42 58 106 122 43 59 107 123 Global ------ 16 signals, 4 from each input group, are routed to every FPGA. MSA_IN ------ 36,37,38,39 52,53,54,55 100,101,102,103 116,117,118,119 Unused FPGA Pins Routed to Vias ------------------------------- There are 90 unused I/O pins on each MSA FPGA. 19 pins of each MSA FPGA are routed to vias for future access. The pins are located on the top side on the FPGAs. FPGA Pin #s ----------- 4 9 11 13 16 18 21 24 26 32 35 38 41 43 46 48 50 53 56 GLOBAL I/O ---------- The Global I/O signals are routed to the BSF FPGA and terminate after in vias for future routing. -------------------------------------------- TERM/GAP/STROBE/SPARE -> MSA_IN/OUT Mapping -------------------------------------------- TERM MSA_IN MSA_OUT ---- ------ ------- TERM 0:15 MSA_IN_0:15 MSA_OUT_0:15 GAP MSA_IN_32 (for terms 0:15) STROBE MSA_IN_33 (for terms 0:15) SPARE 0:13 MSA_IN_34:47 TERM 16:31 MSA_IN_16:31 MSA_OUT_16:31 GAP MSA_IN_48 (for terms 16:31) STROBE MSA_IN_49 (for terms 16:31) SPARE 14:27 MSA_IN_50:63 TERM 32:47 MSA_IN_64:79 MSA_OUT_32:47 GAP MSA_IN_96 (for terms 32:47) STROBE MSA_IN_97 (for terms 32:47) SPARE 28:41 MSA_IN_98:111 TERM 48:63 MSA_IN_80:95 MSA_OUT_48:63 GAP MSA_IN_112 (for terms 48:63) STROBE MSA_IN_113 (for terms 48:63) SPARE 42:55 MSA_IN_114:127 ------------------------- CONNECTOR PIN ASSIGNMENTS ------------------------- The TRM has 8 connectors: P1: 160-pin E-style DIN connector for VME and P1 Timing Signals P2: 160-pin E-style DIN connector for Trigger Framework P2 input bus P3: 160-pin E-style DIN connector for Trigger Framework P3 input bus P4: 160-pin E-style DIN connector for card output P5: 34-pin front-panel connector for "global" signals P6-P7: Low-Speed Optical Link from VRB P8: High-Speed Optical Link to VRB ---------------------------------------------------------------------- P1: 160-pin C-style DIN connector for VME P1 bus -------------------------------------------------------------------- (see P1 Backplane description) ---------------------------------------------------------------------- P2: 160-pin E-style DIN connector for Trigger Framework P2 input bus -------------------------------------------------------------------- (note: 0 <= n <= 3) Pin # Signal Description Dir Identifier ----- ------------------ --- ---------- A1 Subsystem And-Or Input Term 64*n + 0 COM INPUT MSA_In_000 B1 Subsystem And-Or Input Term 64*n + 0 DIR INPUT MSA_In_000 A2 Subsystem And-Or Input Term 64*n + 1 COM INPUT MSA_In_001 B2 Subsystem And-Or Input Term 64*n + 1 DIR INPUT MSA_In_001 A3 Subsystem And-Or Input Term 64*n + 2 COM INPUT MSA_In_002 B3 Subsystem And-Or Input Term 64*n + 2 DIR INPUT MSA_In_002 A4 Subsystem And-Or Input Term 64*n + 3 COM INPUT MSA_In_003 B4 Subsystem And-Or Input Term 64*n + 3 DIR INPUT MSA_In_003 A5 Subsystem And-Or Input Term 64*n + 4 COM INPUT MSA_In_004 B5 Subsystem And-Or Input Term 64*n + 4 DIR INPUT MSA_In_004 A6 Subsystem And-Or Input Term 64*n + 5 COM INPUT MSA_In_005 B6 Subsystem And-Or Input Term 64*n + 5 DIR INPUT MSA_In_005 A7 Subsystem And-Or Input Term 64*n + 6 COM INPUT MSA_In_006 B7 Subsystem And-Or Input Term 64*n + 6 DIR INPUT MSA_In_006 A8 Subsystem And-Or Input Term 64*n + 7 COM INPUT MSA_In_007 B8 Subsystem And-Or Input Term 64*n + 7 DIR INPUT MSA_In_007 A9 Subsystem And-Or Input Term 64*n + 8 COM INPUT MSA_In_008 B9 Subsystem And-Or Input Term 64*n + 8 DIR INPUT MSA_In_008 A10 Subsystem And-Or Input Term 64*n + 9 COM INPUT MSA_In_009 B10 Subsystem And-Or Input Term 64*n + 9 DIR INPUT MSA_In_009 A11 Subsystem And-Or Input Term 64*n + 10 COM INPUT MSA_In_010 B11 Subsystem And-Or Input Term 64*n + 10 DIR INPUT MSA_In_010 A12 Subsystem And-Or Input Term 64*n + 11 COM INPUT MSA_In_011 B12 Subsystem And-Or Input Term 64*n + 11 DIR INPUT MSA_In_011 A13 Subsystem And-Or Input Term 64*n + 12 COM INPUT MSA_In_012 B13 Subsystem And-Or Input Term 64*n + 12 DIR INPUT MSA_In_012 A14 Subsystem And-Or Input Term 64*n + 13 COM INPUT MSA_In_013 B14 Subsystem And-Or Input Term 64*n + 13 DIR INPUT MSA_In_013 A15 Subsystem And-Or Input Term 64*n + 14 COM INPUT MSA_In_014 B15 Subsystem And-Or Input Term 64*n + 14 DIR INPUT MSA_In_014 A16 Subsystem And-Or Input Term 64*n + 15 COM INPUT MSA_In_015 B16 Subsystem And-Or Input Term 64*n + 15 DIR INPUT MSA_In_015 A17 Subsystem And-Or Input Term 64*n + 16 COM INPUT MSA_In_016 B17 Subsystem And-Or Input Term 64*n + 16 DIR INPUT MSA_In_016 A18 Subsystem And-Or Input Term 64*n + 17 COM INPUT MSA_In_017 B18 Subsystem And-Or Input Term 64*n + 17 DIR INPUT MSA_In_017 A19 Subsystem And-Or Input Term 64*n + 18 COM INPUT MSA_In_018 B19 Subsystem And-Or Input Term 64*n + 18 DIR INPUT MSA_In_018 A20 Subsystem And-Or Input Term 64*n + 19 COM INPUT MSA_In_019 B20 Subsystem And-Or Input Term 64*n + 19 DIR INPUT MSA_In_019 A21 Subsystem And-Or Input Term 64*n + 20 COM INPUT MSA_In_020 B21 Subsystem And-Or Input Term 64*n + 20 DIR INPUT MSA_In_020 A22 Subsystem And-Or Input Term 64*n + 21 COM INPUT MSA_In_021 B22 Subsystem And-Or Input Term 64*n + 21 DIR INPUT MSA_In_021 A23 Subsystem And-Or Input Term 64*n + 22 COM INPUT MSA_In_022 B23 Subsystem And-Or Input Term 64*n + 22 DIR INPUT MSA_In_022 A24 Subsystem And-Or Input Term 64*n + 23 COM INPUT MSA_In_023 B24 Subsystem And-Or Input Term 64*n + 23 DIR INPUT MSA_In_023 A25 Subsystem And-Or Input Term 64*n + 24 COM INPUT MSA_In_024 B25 Subsystem And-Or Input Term 64*n + 24 DIR INPUT MSA_In_024 A26 Subsystem And-Or Input Term 64*n + 25 COM INPUT MSA_In_025 B26 Subsystem And-Or Input Term 64*n + 25 DIR INPUT MSA_In_025 A27 Subsystem And-Or Input Term 64*n + 26 COM INPUT MSA_In_026 B27 Subsystem And-Or Input Term 64*n + 26 DIR INPUT MSA_In_026 A28 Subsystem And-Or Input Term 64*n + 27 COM INPUT MSA_In_027 B28 Subsystem And-Or Input Term 64*n + 27 DIR INPUT MSA_In_027 A29 Subsystem And-Or Input Term 64*n + 28 COM INPUT MSA_In_028 B29 Subsystem And-Or Input Term 64*n + 28 DIR INPUT MSA_In_028 A30 Subsystem And-Or Input Term 64*n + 29 COM INPUT MSA_In_029 B30 Subsystem And-Or Input Term 64*n + 29 DIR INPUT MSA_In_029 A31 Subsystem And-Or Input Term 64*n + 30 COM INPUT MSA_In_030 B31 Subsystem And-Or Input Term 64*n + 30 DIR INPUT MSA_In_030 A32 Subsystem And-Or Input Term 64*n + 31 COM INPUT MSA_In_031 B32 Subsystem And-Or Input Term 64*n + 31 DIR INPUT MSA_In_031 C1 GROUND C2 +3.3V UPPER C3 GROUND C4 +3.3V UPPER C5 -2.0V UPPER C6 GROUND C7 +3.3V UPPER C8 GROUND C9 +5.0V UPPER C10 GROUND C11 +3.3V UPPER C12 GROUND C13 +3.3V UPPER C14 GROUND C15 -2.0V UPPER C16 GROUND C17 +3.3V UPPER C18 GROUND C19 +5.0V UPPER C20 +3.3V UPPER C21 GROUND C22 +3.3V UPPER C23 GROUND C24 -2.0V UPPER C25 GROUND C26 +3.3V UPPER C27 GROUND C28 +5.0V UPPER C29 +3.3V UPPER C30 GROUND C31 +3.3V UPPER C32 GROUND D1 Subsystem Gap COM INPUT MSA_In_032 E1 Subsystem Gap DIR INPUT MSA_In_032 D2 Subsystem Strobe to AOITs 64*n + (0:15) COM INPUT MSA_In_033 E2 Subsystem Strobe to AOITs 64*n + (0:15) DIR INPUT MSA_In_033 D3 Spare: Column 1, Per-Column Spare 0 COM INPUT MSA_In_034 E3 Spare: Column 1, Per-Column Spare 0 DIR INPUT MSA_In_034 D4 Spare: Column 1, Per-Column Spare 1 COM INPUT MSA_In_035 E4 Spare: Column 1, Per-Column Spare 1 DIR INPUT MSA_In_035 D5 Spare: Global 0 COM INPUT MSA_In_036 E5 Spare: Global 0 DIR INPUT MSA_In_036 D6 Spare: Global 1 COM INPUT MSA_In_037 E6 Spare: Global 1 DIR INPUT MSA_In_037 D7 Spare: Global 2 COM INPUT MSA_In_038 E7 Spare: Global 2 DIR INPUT MSA_In_038 D8 Spare: Global 3 COM INPUT MSA_In_039 E8 Spare: Global 3 DIR INPUT MSA_In_039 D9 Spare: MSA FPGA 1 Per-FPGA Spare COM INPUT MSA_In_040 E9 Spare: MSA FPGA 1 Per-FPGA Spare DIR INPUT MSA_In_040 D10 Spare: MSA FPGA 5 Per-FPGA Spare COM INPUT MSA_In_041 E10 Spare: MSA FPGA 5 Per-FPGA Spare DIR INPUT MSA_In_041 D11 Spare: MSA FPGA 9 Per-FPGA Spare COM INPUT MSA_In_042 E11 Spare: MSA FPGA 9 Per-FPGA Spare DIR INPUT MSA_In_042 D12 Spare: MSA FPGA 13 Per-FPGA Spare COM INPUT MSA_In_043 E12 Spare: MSA FPGA 13 Per-FPGA Spare DIR INPUT MSA_In_043 D13 Spare: Unrouted 0 COM INPUT MSA_In_044 E13 Spare: Unrouted 0 DIR INPUT MSA_In_044 D14 Spare: Unrouted 1 COM INPUT MSA_In_045 E14 Spare: Unrouted 1 DIR INPUT MSA_In_045 D15 Spare: Unrouted 2 COM INPUT MSA_In_046 E15 Spare: Unrouted 2 DIR INPUT MSA_In_046 D16 Spare: Unrouted 3 COM INPUT MSA_In_047 E16 Spare: Unrouted 3 DIR INPUT MSA_In_047 D17 Subsystem Gap COM INPUT MSA_In_048 E17 Subsystem Gap DIR INPUT MSA_In_048 D18 Subsystem Strobe to AOITS 64*n + (16:31) COM INPUT MSA_In_049 E18 Subsystem Strobe to AOITS 64*n + (16:31) DIR INPUT MSA_In_049 D19 Spare: Column 2, Per-Column Spare 0 COM INPUT MSA_In_050 E19 Spare: Column 2, Per-Column Spare 0 DIR INPUT MSA_In_050 D20 Spare: Column 2, Per-Column Spare 1 COM INPUT MSA_In_051 E20 Spare: Column 2, Per-Column Spare 1 DIR INPUT MSA_In_051 D21 Spare: Global 4 COM INPUT MSA_In_052 E21 Spare: Global 4 DIR INPUT MSA_In_052 D22 Spare: Global 5 COM INPUT MSA_In_053 E22 Spare: Global 5 DIR INPUT MSA_In_053 D23 Spare: Global 6 COM INPUT MSA_In_054 E23 Spare: Global 6 DIR INPUT MSA_In_054 D24 Spare: Global 7 COM INPUT MSA_In_055 E24 Spare: Global 7 DIR INPUT MSA_In_055 D25 Spare: MSA FPGA 2 Per-FPGA Spare COM INPUT MSA_In_056 E25 Spare: MSA FPGA 2 Per-FPGA Spare DIR INPUT MSA_In_056 D26 Spare: MSA FPGA 6 Per-FPGA Spare COM INPUT MSA_In_057 E26 Spare: MSA FPGA 6 Per-FPGA Spare DIR INPUT MSA_In_057 D27 Spare: MSA FPGA 10 Per-FPGA Spare COM INPUT MSA_In_058 E27 Spare: MSA FPGA 10 Per-FPGA Spare DIR INPUT MSA_In_058 D28 Spare: MSA FPGA 14 Per-FPGA Spare COM INPUT MSA_In_059 E28 Spare: MSA FPGA 14 Per-FPGA Spare DIR INPUT MSA_In_059 D29 Spare: Unrouted 4 COM INPUT MSA_In_060 E29 Spare: Unrouted 4 DIR INPUT MSA_In_060 D30 Spare: Unrouted 5 COM INPUT MSA_In_061 E30 Spare: Unrouted 5 DIR INPUT MSA_In_061 D31 Spare: Unrouted 6 COM INPUT MSA_In_062 E31 Spare: Unrouted 6 DIR INPUT MSA_In_062 D32 Spare: Unrouted 7 COM INPUT MSA_In_063 E32 Spare: Unrouted 7 DIR INPUT MSA_In_063 ---------------------------------------------------------------------- P3: 160-pin E-style DIN connector for Trigger Framework P3 input bus ---------------------------------------------------------------------- (note: 0 <= n <= 3) Pin # Signal Description Dir Identifier ----- ------------------ --- ---------- A1 Subsystem And-Or Input Term 64*n + 32 COM INPUT MSA_In_064 B1 Subsystem And-Or Input Term 64*n + 32 DIR INPUT MSA_In_064 A2 Subsystem And-Or Input Term 64*n + 33 COM INPUT MSA_In_065 B2 Subsystem And-Or Input Term 64*n + 33 COM INPUT MSA_In_065 B3 Subsystem And-Or Input Term 64*n + 34 COM INPUT MSA_In_066 B3 Subsystem And-Or Input Term 64*n + 34 DIR INPUT MSA_In_066 A4 Subsystem And-Or Input Term 64*n + 35 COM INPUT MSA_In_067 B4 Subsystem And-Or Input Term 64*n + 35 DIR INPUT MSA_In_067 A5 Subsystem And-Or Input Term 64*n + 36 COM INPUT MSA_In_068 B5 Subsystem And-Or Input Term 64*n + 36 DIR INPUT MSA_In_068 A6 Subsystem And-Or Input Term 64*n + 37 COM INPUT MSA_In_069 B6 Subsystem And-Or Input Term 64*n + 37 DIR INPUT MSA_In_069 A7 Subsystem And-Or Input Term 64*n + 38 COM INPUT MSA_In_070 B7 Subsystem And-Or Input Term 64*n + 38 DIR INPUT MSA_In_070 A8 Subsystem And-Or Input Term 64*n + 39 COM INPUT MSA_In_071 B8 Subsystem And-Or Input Term 64*n + 39 DIR INPUT MSA_In_071 A9 Subsystem And-Or Input Term 64*n + 40 COM INPUT MSA_In_072 B9 Subsystem And-Or Input Term 64*n + 40 DIR INPUT MSA_In_072 A10 Subsystem And-Or Input Term 64*n + 41 COM INPUT MSA_In_073 B10 Subsystem And-Or Input Term 64*n + 41 DIR INPUT MSA_In_073 A11 Subsystem And-Or Input Term 64*n + 42 COM INPUT MSA_In_074 B11 Subsystem And-Or Input Term 64*n + 42 DIR INPUT MSA_In_074 A12 Subsystem And-Or Input Term 64*n + 43 COM INPUT MSA_In_075 B12 Subsystem And-Or Input Term 64*n + 43 DIR INPUT MSA_In_075 A13 Subsystem And-Or Input Term 64*n + 44 COM INPUT MSA_In_076 B13 Subsystem And-Or Input Term 64*n + 44 DIR INPUT MSA_In_076 A14 Subsystem And-Or Input Term 64*n + 45 COM INPUT MSA_In_077 B14 Subsystem And-Or Input Term 64*n + 45 DIR INPUT MSA_In_077 A15 Subsystem And-Or Input Term 64*n + 46 COM INPUT MSA_In_078 B15 Subsystem And-Or Input Term 64*n + 46 DIR INPUT MSA_In_078 A16 Subsystem And-Or Input Term 64*n + 47 COM INPUT MSA_In_079 B16 Subsystem And-Or Input Term 64*n + 47 DIR INPUT MSA_In_079 A17 Subsystem And-Or Input Term 64*n + 48 COM INPUT MSA_In_080 B17 Subsystem And-Or Input Term 64*n + 48 DIR INPUT MSA_In_080 A18 Subsystem And-Or Input Term 64*n + 49 COM INPUT MSA_In_081 B18 Subsystem And-Or Input Term 64*n + 49 DIR INPUT MSA_In_081 A19 Subsystem And-Or Input Term 64*n + 50 COM INPUT MSA_In_082 B19 Subsystem And-Or Input Term 64*n + 50 DIR INPUT MSA_In_082 A20 Subsystem And-Or Input Term 64*n + 51 COM INPUT MSA_In_083 B20 Subsystem And-Or Input Term 64*n + 51 DIR INPUT MSA_In_083 A21 Subsystem And-Or Input Term 64*n + 52 COM INPUT MSA_In_084 B21 Subsystem And-Or Input Term 64*n + 52 DIR INPUT MSA_In_084 A22 Subsystem And-Or Input Term 64*n + 53 COM INPUT MSA_In_085 B22 Subsystem And-Or Input Term 64*n + 53 DIR INPUT MSA_In_085 A23 Subsystem And-Or Input Term 64*n + 54 COM INPUT MSA_In_086 B23 Subsystem And-Or Input Term 64*n + 54 DIR INPUT MSA_In_086 A24 Subsystem And-Or Input Term 64*n + 55 COM INPUT MSA_In_087 B24 Subsystem And-Or Input Term 64*n + 55 DIR INPUT MSA_In_087 A25 Subsystem And-Or Input Term 64*n + 56 COM INPUT MSA_In_088 B25 Subsystem And-Or Input Term 64*n + 56 DIR INPUT MSA_In_088 A26 Subsystem And-Or Input Term 64*n + 57 COM INPUT MSA_In_089 B26 Subsystem And-Or Input Term 64*n + 57 DIR INPUT MSA_In_089 A27 Subsystem And-Or Input Term 64*n + 58 COM INPUT MSA_In_090 B27 Subsystem And-Or Input Term 64*n + 58 DIR INPUT MSA_In_090 A28 Subsystem And-Or Input Term 64*n + 59 COM INPUT MSA_In_091 B28 Subsystem And-Or Input Term 64*n + 59 DIR INPUT MSA_In_091 A29 Subsystem And-Or Input Term 64*n + 60 COM INPUT MSA_In_092 B29 Subsystem And-Or Input Term 64*n + 60 DIR INPUT MSA_In_092 A30 Subsystem And-Or Input Term 64*n + 61 COM INPUT MSA_In_093 B30 Subsystem And-Or Input Term 64*n + 61 DIR INPUT MSA_In_093 A31 Subsystem And-Or Input Term 64*n + 62 COM INPUT MSA_In_094 B31 Subsystem And-Or Input Term 64*n + 62 DIR INPUT MSA_In_094 A32 Subsystem And-Or Input Term 64*n + 63 COM INPUT MSA_In_095 B32 Subsystem And-Or Input Term 64*n + 63 DIR INPUT MSA_In_095 C1 GROUND C2 +3.3V LOWER C3 GROUND C4 +3.3V LOWER C5 -4.5V LOWER C6 GROUND C7 +3.3V LOWER C8 GROUND C9 +5.0V LOWER C10 GROUND C11 +3.3V LOWER C12 GROUND C13 +3.3V LOWER C14 GROUND C15 -4.5V LOWER C16 GROUND C17 +3.3V LOWER C18 GROUND C19 +5.0V LOWER C20 +3.3V LOWER C21 GROUND C22 +3.3V LOWER C23 GROUND C24 -4.5V LOWER C25 GROUND C26 +3.3V LOWER C27 GROUND C28 +5.0V LOWER C29 +3.3V LOWER C30 GROUND C31 +3.3V LOWER C32 GROUND D1 Subsystem Gap COM INPUT MSA_In_096 E1 Subsystem Gap DIR INPUT MSA_In_096 D2 Subsystem Strobe to AOITs 64*n + (32:47) COM INPUT MSA_In_097 E2 Subsystem Strobe to AOITs 64*n + (32:47) DIR INPUT MSA_In_097 D3 Spare: Column 3, Per-Column Spare 0 COM INPUT MSA_In_098 E3 Spare: Column 3, Per-Column Spare 0 DIR INPUT MSA_In_098 D4 Spare: Column 3, Per-Column Spare 1 COM INPUT MSA_In_099 E4 Spare: Column 3, Per-Column Spare 1 DIR INPUT MSA_In_099 D5 Spare: Global 8 COM INPUT MSA_In_100 E5 Spare: Global 8 DIR INPUT MSA_In_100 D6 Spare: Global 9 COM INPUT MSA_In_101 E6 Spare: Global 9 DIR INPUT MSA_In_101 D7 Spare: Global 10 COM INPUT MSA_In_102 E7 Spare: Global 10 DIR INPUT MSA_In_102 D8 Spare: Global 11 COM INPUT MSA_In_103 E8 Spare: Global 11 DIR INPUT MSA_In_103 D9 Spare: MSA FPGA 3 Per-FPGA Spare COM INPUT MSA_In_104 E9 Spare: MSA FPGA 3 Per-FPGA Spare DIR INPUT MSA_In_104 D10 Spare: MSA FPGA 7 Per-FPGA Spare COM INPUT MSA_In_105 E10 Spare: MSA FPGA 7 Per-FPGA Spare DIR INPUT MSA_In_105 D11 Spare: MSA FPGA 11 Per-FPGA Spare COM INPUT MSA_In_106 E11 Spare: MSA FPGA 11 Per-FPGA Spare DIR INPUT MSA_In_106 D12 Spare: MSA FPGA 15 Per-FPGA Spare COM INPUT MSA_In_107 E12 Spare: MSA FPGA 15 Per-FPGA Spare DIR INPUT MSA_In_107 D13 Spare: Unrouted 8 COM INPUT MSA_In_108 E13 Spare: Unrouted 8 DIR INPUT MSA_In_108 D14 Spare: Unrouted 9 COM INPUT MSA_In_109 E14 Spare: Unrouted 9 DIR INPUT MSA_In_109 D15 Spare: Unrouted 10 COM INPUT MSA_In_110 E15 Spare: Unrouted 10 DIR INPUT MSA_In_110 D16 Spare: Unrouted 11 COM INPUT MSA_In_111 E16 Spare: Unrouted 11 DIR INPUT MSA_In_111 D17 Subsystem Gap COM INPUT MSA_In_112 E17 Subsystem Gap DIR INPUT MSA_In_112 D18 Subsystem Strobe to AOITs 64*n + (48:63) COM INPUT MSA_In_113 E18 Subsystem Strobe to AOITs 64*n + (48:63) DIR INPUT MSA_In_113 D19 Spare: Column 4, Per-Column Spare 0 COM INPUT MSA_In_114 E19 Spare: Column 4, Per-Column Spare 0 DIR INPUT MSA_In_114 D20 Spare: Column 4, Per-Column Spare 1 COM INPUT MSA_In_115 E20 Spare: Column 4, Per-Column Spare 1 DIR INPUT MSA_In_115 D21 Spare: Global 12 COM INPUT MSA_In_116 E21 Spare: Global 12 DIR INPUT MSA_In_116 D22 Spare: Global 13 COM INPUT MSA_In_117 E22 Spare: Global 13 DIR INPUT MSA_In_117 D23 Spare: Global 14 COM INPUT MSA_In_118 E23 Spare: Global 14 DIR INPUT MSA_In_118 D24 Spare: Global 15 COM INPUT MSA_In_119 E24 Spare: Global 15 DIR INPUT MSA_In_119 D25 Spare: MSA FPGA 4 Per-FPGA Spare COM INPUT MSA_In_120 E25 Spare: MSA FPGA 4 Per-FPGA Spare DIR INPUT MSA_In_120 D26 Spare: MSA FPGA 8 Per-FPGA Spare COM INPUT MSA_In_121 E26 Spare: MSA FPGA 8 Per-FPGA Spare DIR INPUT MSA_In_121 D27 Spare: MSA FPGA 12 Per-FPGA Spare COM INPUT MSA_In_122 E27 Spare: MSA FPGA 12 Per-FPGA Spare DIR INPUT MSA_In_122 D28 Spare: MSA FPGA 16 Per-FPGA Spare COM INPUT MSA_In_123 E28 Spare: MSA FPGA 16 Per-FPGA Spare DIR INPUT MSA_In_123 D29 Spare: Unrouted 12 COM INPUT MSA_In_124 E29 Spare: Unrouted 12 DIR INPUT MSA_In_124 D30 Spare: Unrouted 13 COM INPUT MSA_In_125 E30 Spare: Unrouted 13 DIR INPUT MSA_In_125 D31 Spare: Unrouted 14 COM INPUT MSA_In_126 E31 Spare: Unrouted 14 DIR INPUT MSA_In_126 D32 Spare: Unrouted 15 COM INPUT MSA_In_127 E32 Spare: Unrouted 15 DIR INPUT MSA_In_127 ---------------------------------------------------------------------- P4: 160-pin front-panel connector for card outputs ---------------------------------------------------------------------- (note: 0 <= n <= 3) Pin # Signal Description Dir Identifier ----- ------------------ --- ---------- A1 Isochronous And-Or Input Term 64*n + 63 DIR OUTPUT MSA_Out_63 B1 Isochronous And-Or Input Term 64*n + 63 COM OUTPUT MSA_Out_63 A2 Isochronous And-Or Input Term 64*n + 62 DIR OUTPUT MSA_Out_62 B2 Isochronous And-Or Input Term 64*n + 62 COM OUTPUT MSA_Out_62 A3 Isochronous And-Or Input Term 64*n + 61 DIR OUTPUT MSA_Out_61 B3 Isochronous And-Or Input Term 64*n + 61 COM OUTPUT MSA_Out_61 A4 Isochronous And-Or Input Term 64*n + 60 DIR OUTPUT MSA_Out_60 B4 Isochronous And-Or Input Term 64*n + 60 COM OUTPUT MSA_Out_60 A5 Isochronous And-Or Input Term 64*n + 59 DIR OUTPUT MSA_Out_59 B5 Isochronous And-Or Input Term 64*n + 59 COM OUTPUT MSA_Out_59 A6 Isochronous And-Or Input Term 64*n + 58 DIR OUTPUT MSA_Out_58 B6 Isochronous And-Or Input Term 64*n + 58 COM OUTPUT MSA_Out_58 A7 Isochronous And-Or Input Term 64*n + 57 DIR OUTPUT MSA_Out_57 B7 Isochronous And-Or Input Term 64*n + 57 COM OUTPUT MSA_Out_57 A8 Isochronous And-Or Input Term 64*n + 56 DIR OUTPUT MSA_Out_56 B8 Isochronous And-Or Input Term 64*n + 56 COM OUTPUT MSA_Out_56 A9 Isochronous And-Or Input Term 64*n + 55 DIR OUTPUT MSA_Out_55 B9 Isochronous And-Or Input Term 64*n + 55 COM OUTPUT MSA_Out_55 A10 Isochronous And-Or Input Term 64*n + 54 DIR OUTPUT MSA_Out_54 B10 Isochronous And-Or Input Term 64*n + 54 COM OUTPUT MSA_Out_54 A11 Isochronous And-Or Input Term 64*n + 53 DIR OUTPUT MSA_Out_53 B11 Isochronous And-Or Input Term 64*n + 53 COM OUTPUT MSA_Out_53 A12 Isochronous And-Or Input Term 64*n + 52 DIR OUTPUT MSA_Out_52 B12 Isochronous And-Or Input Term 64*n + 52 COM OUTPUT MSA_Out_52 A13 Isochronous And-Or Input Term 64*n + 51 DIR OUTPUT MSA_Out_51 B13 Isochronous And-Or Input Term 64*n + 51 COM OUTPUT MSA_Out_51 A14 Isochronous And-Or Input Term 64*n + 50 DIR OUTPUT MSA_Out_50 B14 Isochronous And-Or Input Term 64*n + 50 COM OUTPUT MSA_Out_50 A15 Isochronous And-Or Input Term 64*n + 49 DIR OUTPUT MSA_Out_49 B15 Isochronous And-Or Input Term 64*n + 49 COM OUTPUT MSA_Out_49 A16 Isochronous And-Or Input Term 64*n + 48 DIR OUTPUT MSA_Out_48 B16 Isochronous And-Or Input Term 64*n + 48 COM OUTPUT MSA_Out_48 A17 Isochronous And-Or Input Term 64*n + 47 DIR OUTPUT MSA_Out_47 B17 Isochronous And-Or Input Term 64*n + 47 COM OUTPUT MSA_Out_47 A18 Isochronous And-Or Input Term 64*n + 46 DIR OUTPUT MSA_Out_46 B18 Isochronous And-Or Input Term 64*n + 46 COM OUTPUT MSA_Out_46 A19 Isochronous And-Or Input Term 64*n + 45 DIR OUTPUT MSA_Out_45 B19 Isochronous And-Or Input Term 64*n + 45 COM OUTPUT MSA_Out_45 A20 Isochronous And-Or Input Term 64*n + 44 DIR OUTPUT MSA_Out_44 B20 Isochronous And-Or Input Term 64*n + 44 COM OUTPUT MSA_Out_44 A21 Isochronous And-Or Input Term 64*n + 43 DIR OUTPUT MSA_Out_43 B21 Isochronous And-Or Input Term 64*n + 43 COM OUTPUT MSA_Out_43 A22 Isochronous And-Or Input Term 64*n + 42 DIR OUTPUT MSA_Out_42 B22 Isochronous And-Or Input Term 64*n + 42 COM OUTPUT MSA_Out_42 A23 Isochronous And-Or Input Term 64*n + 41 DIR OUTPUT MSA_Out_41 B23 Isochronous And-Or Input Term 64*n + 41 COM OUTPUT MSA_Out_41 A24 Isochronous And-Or Input Term 64*n + 40 DIR OUTPUT MSA_Out_40 B24 Isochronous And-Or Input Term 64*n + 40 COM OUTPUT MSA_Out_40 A25 Isochronous And-Or Input Term 64*n + 39 DIR OUTPUT MSA_Out_39 B25 Isochronous And-Or Input Term 64*n + 39 COM OUTPUT MSA_Out_39 A26 Isochronous And-Or Input Term 64*n + 38 DIR OUTPUT MSA_Out_38 B26 Isochronous And-Or Input Term 64*n + 38 COM OUTPUT MSA_Out_38 A27 Isochronous And-Or Input Term 64*n + 37 DIR OUTPUT MSA_Out_37 B27 Isochronous And-Or Input Term 64*n + 37 COM OUTPUT MSA_Out_37 A28 Isochronous And-Or Input Term 64*n + 36 DIR OUTPUT MSA_Out_36 B28 Isochronous And-Or Input Term 64*n + 36 COM OUTPUT MSA_Out_36 A29 Isochronous And-Or Input Term 64*n + 35 DIR OUTPUT MSA_Out_35 B29 Isochronous And-Or Input Term 64*n + 35 COM OUTPUT MSA_Out_35 A30 Isochronous And-Or Input Term 64*n + 34 DIR OUTPUT MSA_Out_34 B30 Isochronous And-Or Input Term 64*n + 34 COM OUTPUT MSA_Out_34 A31 Isochronous And-Or Input Term 64*n + 33 DIR OUTPUT MSA_Out_33 B31 Isochronous And-Or Input Term 64*n + 33 COM OUTPUT MSA_Out_33 A32 Isochronous And-Or Input Term 64*n + 32 DIR OUTPUT MSA_Out_32 B32 Isochronous And-Or Input Term 64*n + 32 COM OUTPUT MSA_Out_32 C1 GROUND C2 +5.0 V C3 GROUND C4 GROUND C5 GROUND C6 +3.3 V C7 GROUND C8 GROUND C9 GROUND C10 -2.0 V C11 GROUND C12 GROUND C13 GROUND C14 -4.5 V C15 GROUND C16 GROUND C17 GROUND C18 GROUND C19 +5.0 V C20 GROUND C21 GROUND C22 GROUND C23 +3.3 V C24 GROUND C25 GROUND C26 GROUND C27 -2.0 V C28 GROUND C29 GROUND C30 GROUND C31 -4.5 V C32 GROUND D1 Isochronous And-Or Input Term 64*n + 31 DIR OUTPUT MSA_Out_31 E1 Isochronous And-Or Input Term 64*n + 31 COM OUTPUT MSA_Out_31 D2 Isochronous And-Or Input Term 64*n + 30 DIR OUTPUT MSA_Out_30 E2 Isochronous And-Or Input Term 64*n + 30 COM OUTPUT MSA_Out_30 D3 Isochronous And-Or Input Term 64*n + 29 DIR OUTPUT MSA_Out_29 E3 Isochronous And-Or Input Term 64*n + 29 COM OUTPUT MSA_Out_29 D4 Isochronous And-Or Input Term 64*n + 28 DIR OUTPUT MSA_Out_28 E4 Isochronous And-Or Input Term 64*n + 28 COM OUTPUT MSA_Out_28 D5 Isochronous And-Or Input Term 64*n + 27 DIR OUTPUT MSA_Out_27 E5 Isochronous And-Or Input Term 64*n + 27 COM OUTPUT MSA_Out_27 D6 Isochronous And-Or Input Term 64*n + 26 DIR OUTPUT MSA_Out_26 E6 Isochronous And-Or Input Term 64*n + 26 COM OUTPUT MSA_Out_26 D7 Isochronous And-Or Input Term 64*n + 25 DIR OUTPUT MSA_Out_25 E7 Isochronous And-Or Input Term 64*n + 25 COM OUTPUT MSA_Out_25 D8 Isochronous And-Or Input Term 64*n + 24 DIR OUTPUT MSA_Out_24 E8 Isochronous And-Or Input Term 64*n + 24 COM OUTPUT MSA_Out_24 D9 Isochronous And-Or Input Term 64*n + 23 DIR OUTPUT MSA_Out_23 E9 Isochronous And-Or Input Term 64*n + 23 COM OUTPUT MSA_Out_23 D10 Isochronous And-Or Input Term 64*n + 22 DIR OUTPUT MSA_Out_22 E10 Isochronous And-Or Input Term 64*n + 22 COM OUTPUT MSA_Out_22 D11 Isochronous And-Or Input Term 64*n + 21 DIR OUTPUT MSA_Out_21 E11 Isochronous And-Or Input Term 64*n + 21 COM OUTPUT MSA_Out_21 D12 Isochronous And-Or Input Term 64*n + 20 DIR OUTPUT MSA_Out_20 E12 Isochronous And-Or Input Term 64*n + 20 COM OUTPUT MSA_Out_20 D13 Isochronous And-Or Input Term 64*n + 19 DIR OUTPUT MSA_Out_19 E13 Isochronous And-Or Input Term 64*n + 19 COM OUTPUT MSA_Out_19 D14 Isochronous And-Or Input Term 64*n + 18 DIR OUTPUT MSA_Out_18 E14 Isochronous And-Or Input Term 64*n + 18 COM OUTPUT MSA_Out_18 D15 Isochronous And-Or Input Term 64*n + 17 DIR OUTPUT MSA_Out_17 E15 Isochronous And-Or Input Term 64*n + 17 COM OUTPUT MSA_Out_17 D16 Isochronous And-Or Input Term 64*n + 16 DIR OUTPUT MSA_Out_16 E16 Isochronous And-Or Input Term 64*n + 16 COM OUTPUT MSA_Out_16 D17 Isochronous And-Or Input Term 64*n + 15 DIR OUTPUT MSA_Out_15 E17 Isochronous And-Or Input Term 64*n + 15 COM OUTPUT MSA_Out_15 D18 Isochronous And-Or Input Term 64*n + 14 DIR OUTPUT MSA_Out_14 E18 Isochronous And-Or Input Term 64*n + 14 COM OUTPUT MSA_Out_14 D19 Isochronous And-Or Input Term 64*n + 13 DIR OUTPUT MSA_Out_13 E19 Isochronous And-Or Input Term 64*n + 13 COM OUTPUT MSA_Out_13 D20 Isochronous And-Or Input Term 64*n + 12 DIR OUTPUT MSA_Out_12 E20 Isochronous And-Or Input Term 64*n + 12 COM OUTPUT MSA_Out_12 D21 Isochronous And-Or Input Term 64*n + 11 DIR OUTPUT MSA_Out_11 E21 Isochronous And-Or Input Term 64*n + 11 COM OUTPUT MSA_Out_11 D22 Isochronous And-Or Input Term 64*n + 10 DIR OUTPUT MSA_Out_10 E22 Isochronous And-Or Input Term 64*n + 10 COM OUTPUT MSA_Out_10 D23 Isochronous And-Or Input Term 64*n + 9 DIR OUTPUT MSA_Out_09 E23 Isochronous And-Or Input Term 64*n + 9 COM OUTPUT MSA_Out_09 D24 Isochronous And-Or Input Term 64*n + 8 DIR OUTPUT MSA_Out_08 E24 Isochronous And-Or Input Term 64*n + 8 COM OUTPUT MSA_Out_08 D25 Isochronous And-Or Input Term 64*n + 7 DIR OUTPUT MSA_Out_07 E25 Isochronous And-Or Input Term 64*n + 7 COM OUTPUT MSA_Out_07 D26 Isochronous And-Or Input Term 64*n + 6 DIR OUTPUT MSA_Out_06 E26 Isochronous And-Or Input Term 64*n + 6 COM OUTPUT MSA_Out_06 D27 Isochronous And-Or Input Term 64*n + 5 DIR OUTPUT MSA_Out_05 E27 Isochronous And-Or Input Term 64*n + 5 COM OUTPUT MSA_Out_05 D28 Isochronous And-Or Input Term 64*n + 4 DIR OUTPUT MSA_Out_04 E28 Isochronous And-Or Input Term 64*n + 4 COM OUTPUT MSA_Out_04 D29 Isochronous And-Or Input Term 64*n + 3 DIR OUTPUT MSA_Out_03 E29 Isochronous And-Or Input Term 64*n + 3 COM OUTPUT MSA_Out_03 D30 Isochronous And-Or Input Term 64*n + 2 DIR OUTPUT MSA_Out_02 E30 Isochronous And-Or Input Term 64*n + 2 COM OUTPUT MSA_Out_02 D31 Isochronous And-Or Input Term 64*n + 1 DIR OUTPUT MSA_Out_01 E31 Isochronous And-Or Input Term 64*n + 1 COM OUTPUT MSA_Out_01 D32 Isochronous And-Or Input Term 64*n + 0 DIR OUTPUT MSA_Out_00 E32 Isochronous And-Or Input Term 64*n + 0 COM OUTPUT MSA_Out_00 ---------------------------------------------------------------------- P5: 34-pin front-panel connector for "global" signals ---------------------------------------------------------------------- Pin # Signal Description Dir Identifier ----- ------------------ --- -------- 1 P5 Global I/O Signal 0 COM BIDIR P5_IO_00 2 P5 Global I/O Signal 0 DIR BIDIR P5_IO_00 3 P5 Global I/O Signal 1 COM BIDIR P5_IO_01 4 P5 Global I/O Signal 1 DIR BIDIR P5_IO_01 5 P5 Global I/O Signal 2 COM BIDIR P5_IO_02 6 P5 Global I/O Signal 2 DIR BIDIR P5_IO_02 7 P5 Global I/O Signal 3 COM BIDIR P5_IO_03 8 P5 Global I/O Signal 3 DIR BIDIR P5_IO_03 9 P5 Global I/O Signal 4 COM BIDIR P5_IO_04 10 P5 Global I/O Signal 4 DIR BIDIR P5_IO_04 11 P5 Global I/O Signal 5 COM BIDIR P5_IO_05 12 P5 Global I/O Signal 5 DIR BIDIR P5_IO_05 13 P5 Global I/O Signal 6 COM BIDIR P5_IO_06 14 P5 Global I/O Signal 6 DIR BIDIR P5_IO_06 15 P5 Global I/O Signal 7 COM BIDIR P5_IO_07 16 P5 Global I/O Signal 7 DIR BIDIR P5_IO_07 17 P5 Global I/O Signal 8 COM BIDIR P5_IO_08 18 P5 Global I/O Signal 8 DIR BIDIR P5_IO_08 19 P5 Global I/O Signal 9 COM BIDIR P5_IO_09 20 P5 Global I/O Signal 9 DIR BIDIR P5_IO_09 21 P5 Global I/O Signal 10 COM BIDIR P5_IO_10 22 P5 Global I/O Signal 10 DIR BIDIR P5_IO_10 23 P5 Global I/O Signal 11 COM BIDIR P5_IO_11 24 P5 Global I/O Signal 11 DIR BIDIR P5_IO_11 25 P5 Global I/O Signal 12 COM BIDIR P5_IO_12 26 P5 Global I/O Signal 12 DIR BIDIR P5_IO_12 27 P5 Global I/O Signal 13 COM BIDIR P5_IO_13 28 P5 Global I/O Signal 13 DIR BIDIR P5_IO_13 29 P5 Global I/O Signal 14 COM BIDIR P5_IO_14 30 P5 Global I/O Signal 14 DIR BIDIR P5_IO_14 31 P5 Global I/O Signal 15 COM BIDIR P5_IO_15 32 P5 Global I/O Signal 15 DIR BIDIR P5_IO_15 33 P5 Global I/O Signal 16 COM BIDIR P5_IO_16 34 P5 Global I/O Signal 16 DIR BIDIR P5_IO_16