***************************** * * * D-Zero Run II Upgrade * * * * Level 1 Trigger Framework * * * * and * * * * Level 2 Trigger Framework * * * * TRM Connectivity Test * * * * FPGA Description * * * ***************************** Original: 15-JUNE-1998 Latest: 15-JUNE-1998 Introduction ------------ The Connectivity Test will be used during two different phases in the life of the system (including L1 and L2 Framework): - as part of initial card commissioning, - as an exerciser, diagnostics, and repair tool to support the running system. The goal is to cover all possible types of connections, including - cables - connectors - on board traces - part placement - soldering For this test, a special TRM FPGA configuration and a special BSF FPGA configuration are needed. In these special configurations, all FPGA inputs are readable from VME registers, and all outputs are controllable from VME registers, with no connection inside the FPGA between inputs and outputs. Whenever possible, "physically close" groups of signals should be handled by neighboring bits within a common register; ideally 16 connections at a time. The VME Interface FPGA will not (cannot) be programmed differently during the connectivity tests. Note that for the connectivity test a special On-Card Bus (OCB) is needed. The standard OCB includes a BSCAN component to enable JTAG; for these tests the JTAG lines will be controlled by registers and consequently this component must be removed from the OCB. TRM FPGA --------- The TRM Connectivity Test FPGA has the following inputs and outputs: o Input Terms o Subsystem Gap o Subsystem Strobe o Spare Inputs o HSRO Data o HSRO Data Valid o HSRO DCE In o High-Quality Timing Signals o Capture High-Speed Data o Capture Monitor Data o JTAG Test Data In o Output Terms o HSRO DCE Out o Chip Status o JTAG Test Data Out Programming Interface --------------------- The TRM Connectivity Test FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R Subsystem Inputs 4 R Global Spare Inputs 5 R Individual Spare Inputs 8 R Bussed Control Lines 16 R HSRO Data 17 R HSRO DCE In 24 R High-Quality Timing Signals 32 R JTAG Test Data In 48 R/W Output Terms 56 R/W HSRO DCE Out 57 R/W JTAG Test Data Out 64 R/W Chip Status The bit allocation in each of these registers is given below. Subsystem Inputs Bit Access Contents --- ------ -------- 3:0 R Input Terms 4 R Subsystem Gap 5 R Subsystem Strobe 15:6 not allocated Individual Spare Inputs Bit Access Contents --- ------ -------- 0 R Per FPGA Spare 2:1 R Per Column Spare (1:0) 15:3 not allocated Bussed Control Lines Bit Access Contents --- ------ -------- 0 R HSRO Data Valid 1 R Capture High-Speed Data 2 R Capture Monitor Data 15:3 not allocated HSRO DCE In Bit Access Contents --- ------ -------- 0 R HSRO DCE In 15:1 not allocated High-Quality Timing Signals Bit Access Contents --- ------ -------- 4:0 R HQ Timing Signal 4:0 15:5 not allocated JTAG Test Data In Bit Access Contents --- ------ -------- 0 R JTAG Test Data In 15:1 not allocated Output Terms Bit Access Contents --- ------ -------- 3:0 R/W Output Terms 15:4 not allocated HSRO DCE Out Bit Access Contents --- ------ -------- 0 R/W HSRO DCE Out 15:1 not allocated Chip Status Bit Access Contents --- ------ -------- 0 R/W Chip Status 15:1 not allocated JTAG Test Data Out Bit Access Contents --- ------ -------- 0 R/W JTAG Test Data Out 15:1 not allocated BSF FPGA -------- The BSF FPGA for the TRM Connectivity Test has the following inputs and outputs: o P1 Timing Signals (including the 53 MHz clock as P1 TS #0) o P5 Global I/O o HSRO DCE In o JTAG Test Data In o High-Quality Timing Signals o Capture High-Speed Data o Capture Monitor Data o HSRO Data o HSRO Data Valid o HSRO DCE Out o Chip Status o JTAG Test Data Out Programming Information ----------------------- The TRM Connectivity Test BSF FPGA has the following VME-visible registers: Reg Register Addr Access Contents ---- ------ -------- 0 R P1 Timing Signals 8 R/W Bussed Control Lines 16 R/W HSRO Data 17 R HSRO DCE In 24 R/W High-Quality Timing Signals 32 R JTAG Test Data In 48 R P5 Global I/O (15:0) 49 R P5 Global I/O (16) 56 R/W HSRO DCE Out 57 R/W JTAG Test Data Out 64 R/W Chip Status The bit allocation in each of these registers is given below. Bussed Control Lines Bit Access Contents --- ------ -------- 0 R/W HSRO Data Valid 1 R/W Capture High-Speed Data 2 R/W Capture Monitor Data 15:3 not allocated HSRO DCE In Bit Access Contents --- ------ -------- 0 R HSRO DCE In 15:1 not allocated High-Quality Timing Signals Bit Access Contents --- ------ -------- 3:0 R/W HQ Timing Signals 3:0 to MSA FPGAs 4:1 7:4 R/W HQ Timing Signals 3:0 to MSA FPGAs 8:5 11:8 R/W HQ Timing Signals 3:0 to MSA FPGAs 12:6 15:12 R/W HQ Timing Signals 3:0 to MSA FPGAs 16:13 JTAG Test Data In Bit Access Contents --- ------ -------- 0 R JTAG Test Data In 15:1 not allocated HSRO DCE Out Bit Access Contents --- ------ -------- 0 R/W HSRO DCE Out 15:1 not allocated Chip Status Bit Access Contents --- ------ -------- 0 R/W Chip Status 15:1 not allocated JTAG Test Data Out Bit Access Contents --- ------ -------- 0 R/W JTAG Test Data Out 15:1 not allocated