To Initialize or ReSync  The TRM Input FIFO
          -----------------------------------------------

                                                        Rev 9-DEC-1997

1. Turn off the "out of sync error detection logic" for Term Input Group
   that needs to be ReSync'd.

2. Force both the Write Address Counter (WAC) and the Read Address
   Counter (RAC) both to Zero.   Hold them both at Zero.   This causes
   the Term Input Information to be repetitively written to RAM
   address Zero .

3. When the Term Input Group contains an asserted Gap Signal then
   allow the WAC to begin incrementing.  The Tick with the Term Input
   Information with the asserted Gap Signal will be stored at RAM
   address Zero, the next Tick's data at RAM address 1, ...

4. After the WAC has been enabled to increment, then the RAC control
   logic waits for the P1 Timing Signal that says that the FIFO read
   channel should now be pulling a Tick's worth of information from
   the RAM that contains an asserted Gap Signal.  At this point allow
   the RAC to begin incrementing.

5. After waiting for a couple of ticks then Enable the Sync Error
   Detection logic for this Term Input Group.



Requirement:

   The maximum length of the FIFO delay is shorter than the time
   between Gaps.   For example a maximum delay of 25 ticks and a
   Gap signal once every 46 or 48 ticks is OK.

   Something like a max delay of 25 and a gap every 10 is a problem.
   You do not know where to line up.


Problems:

   The actual control logic for the RAC is going to be very hard to
   design because it will have to take into consideration the case
   where there is almost no FIFO delay;  i.e. a L1 Trig that gets its
   Term Input Signals to the L1 FW just in time.   The WAC and the RAC
   will both have to begin incrementing at just about the same time.


Signal Names:

   The "OR" line that tells if any Term Input Group has detected an
   Out of Sync Error can be called the Maginot Line.