Orig: 24-NOV-1998 
                                                Rev:  24-NOV-1998 

How can we test the TRM FIFO using an external data source?

For each group of TRM Input Terms, we need a data source which
can provide:

    - 16 Subsystem Input Terms
    -  1 Subsystem Gap
    -  1 Subsystem Strobe

This data source must have 2 Test Data Registers, designated A and B
(analogous to the TDR's on the TRM itself), programmable by TCC.  They
contain:

    - 16 Subsystem Input Terms
    -  1 Subsystem Gap

The data source requires 2 P1 Timing Signals:

    - 1 Subsystem Strobe Source     (Carmen-type, always running)
    - 1 TDR Select A/B*             (Helper-type) (like Mag. Line)

This data source is "plugged in" to the normal TRM inputs using 
appropriate cables.  

The data source then normally strobes pattern "A" into the TRM, but
when the Helper Function FPGA is kicked, the data source strobes
pattern "B" into the TRM, and (with the appropriate delay) asserts
Capture Monitor Data to get the Framework's response to pattern "B".  

The TRM FIFO will need to be initally "synched" and we will likely want
to occasionally re-synch the FIFO during the test, or deliberately 
introduce a FIFO synch error.  In order to do this, the TRM's Framework Gap
HQ Timing Signal must be sourced by a Helper Function, rather than
the Carmen (or Big Ben).  This can be done by programming the HQ_TS mux
on the TRM BSF, and we already have set aside P1_TS(14) for this purpose.
Also note that the Maginot Line HQ_TS on the TRM must be forced LOW, again
this can be done via the TRM BSF's HQ_TS mux.  Currently the Helper FPGA
does not generate P1_TS(14) (although the Helper Toy does), but this is
not a major issue.  

To initially synch the FIFO, TCC would program the data source TDR B
to assert its SS_Gap signal.  TCC would program the Helper FPGA with
a given delay between its Assert Data Source TDR B output and its
Framework Gap output.  This effectively sets the "active depth" of
the TRM's FIFO.  The Capture Monitor Data Helper output would follow
the Framework Gap output by a fixed delay.  TCC can look at the 
Monitor Data to verify FIFO synch.

For some number of successive loops, TCC would program the data source
TDR B with random values, but NOT set the SS_Gap.  The Helper would be
programmed to NOT assert FW Gap either.  

At some point, TCC could re-synch the FIFO using the above procedure, 
but setting a different "active depth."  Or TCC could force a FIFO
synch error by asserting the FW_Gap without the SS_Gap, or vice-versa.

The data source FPGA could be on an FM, since it needs 18 outputs there
are 2 potential sites on each FM, so one FM could drive half of one
TRM.  If we use the same FM's that currently hold the P1_P5 TS copier
FPGA's we don't even add cards to the Test Crate.  Note that then we
would need to modify P1_P5 copier FPGA to also drive HQ_TS to the
data source FPGA's.

Advantages of this scheme are:

    - uses the actual TRM FPGA, input buffers, traces, etc.
    - runs the FIFO at full speed (although clocking the same data
      in repetitively, the address pointers must run correctly, etc)
    - from software, it looks much like the current test

Some disadvantages:

    - all TRM FIFO's run at same active depth
    - all Subsystem Strobes run at same time, in fixed phase 
      relationship with TRM Clock (but could vary with varying cable
      lengths)