TRM MSA FPGA Initialization
	---------------------------
							Orig: 24-FEB-2000
							Rev:  30-MAR-2000


There are several different TRM uses:

      - AOIT TRM's					      (L1_TRM)	  
      - L1 Busy, Individual Disable, and Global Disable TRM's (L1_TRM)	  
      - L2 ST Fired and L2 Aux Data TRM's		      (L2_TRM)
      - L2 Global Answer TRM's				      (L2_TRM)

These types of TRM's must each be set up in a unique fashion.  This file
described the MSA FPGA programming of each type of card.  

(1) AOIT TRM's: L1_TRM FPGA
    
    Addr Data	  Comment
    ---- ----	  -------
     0	 0x0009	  Interrupts Enabled, Latched FIFO Error generates IRQ

		  **** NOTE: probably don't want to enable Interrupts
		  **** until error checking is under control, see
		  **** below

		  **** NOTE: at initialize time, disable interrupts 
		  **** in the VME FPGA of each L1 AOIT TRM.  For each
		  **** AOIT which is used in one or more Specific Triggers,
		  **** enable the corresponding TRM FPGA to generate 
		  **** interrupts via the VME FPGA

     2	 0x0000	  No scalers enabled for Timing Signal Reset

     3	 0x0000	  No scalers held in reset

     8	 0x000f	  Enable all FIFO error checking, but DO NOT enable
		  automatic error clearing (i.e. errors remain stored
		  in Error Reporting Register until TCC manually clears
		  them)
		  
		  **** NOTE: TCC should clear any initial errors in
		  **** the Error Reporting Register at Initialize time
		  **** A way to do this is to write 0x000f, wait for 
		  **** re-synch (21 us or less if everything's OK), 
		  **** then write 0x020f (clearing errors), then
		  **** write 0x000f again.  
	
    12   0x0000   Test Data Reg A
    13	 0x0000   Test Data Reg B

    16	 0x0001	  Select FIFO as output source
    
    25	 0x8002	  Enable HSRO, provide 2 16-bit words (note: only one
		  currently used)

    32	 0x0001   Selects BXHSR Depth                       


(2) L1 Front-End Busy, Individual and Global Disable TRM's: L1_TRM FPGA

    Addr Data	  Comment
    ---- ----	  -------
     0	 0x0000	  Disable Interrupts

     2	 0x0000	  No scalers enabled for Timing Signal Reset

     3	 0x0000	  No scalers held in reset

     8	 0x0000	  Disable all FIFO error checking

    12   0x0000	  Test Data Reg A
    13	 0x0000	  Test Data Reg B

    16	 0x0000	  Select FIFO Bypass output source
    
    25	 0x8002	  Enable HSRO, provide 2 16-bit words (note: only one
		  currently used)

    32	 0x0001   Selects BXHSR Depth  


(3) L1 Aux Data TRM:			      L2_TRM FPGA

    Addr Data	  Comment
    ---- ----	  -------
     0	 0x0021	  Enable  VME Interrupts, but send a copy of FIFO_Not_Empty
		  to the BSF FPGA

     2	 0x0000	  No scalers enabled for Timing Signal Reset

     3	 0x0000	  No scalers held in reset

     8	 0x0003	  Enable FIFO Empty and FIFO Full Error checking.  
		  DO NOT enable automatic error clearing (i.e. errors 
		  remain stored in Error Reporting Register until TCC 
		  manually clears them)
		  
		  **** NOTE: TCC should clear any initial errors in
		  **** the Error Reporting Register at Initialize time
		  **** A way to do this is to write 0x0003, wait for 
		  **** re-synch (21 us or less if everything's OK), 
		  **** then write 0x0203 (clearing errors), then
		  **** write 0x0003 again.  

    12   0x000f	  Test Data Reg A
    13	 0x000f	  Test Data Reg B

    16	 0x0001	  Select FIFO as output source       
    
    25	 0x0000	  Disable HSRO

    32	 0x0001   BXHSR Depth                                 


(4) L1 Specific Trigger Fired (to L2 FW) TRM's:    L2_TRM FPGA

    Addr Data	  Comment
    ---- ----	  -------
     0	 0x0000	  Disable VME Interrupts. 

     2	 0x0000	  No scalers enabled for Timing Signal Reset

     3	 0x0000	  No scalers held in reset

     8	 0x0003	  Enable FIFO Empty and FIFO Full Error checking.  
		  DO NOT enable automatic error clearing (i.e. errors 
		  remain stored in Error Reporting Register until TCC 
		  manually clears them)
		  
		  **** NOTE: TCC should clear any initial errors in
		  **** the Error Reporting Register at Initialize time
		  **** A way to do this is to write 0x0003, wait for 
		  **** re-synch (21 us or less if everything's OK), 
		  **** then write 0x0203 (clearing errors), then
		  **** write 0x0003 again.  		  

    12   0x000f	  Test Data Reg A
    13	 0x000f	  Test Data Reg B

    16	 0x0001	  Select FIFO as output source       
    
    25	 0x0000	  Disable HSRO

    32	 0x0001   BXHSR Depth                             


(4) L2 Global Answer TRM's                     

    Addr Data	  Comment
    ---- ----	  -------
     0	 0x0021	  Enable  VME Interrupts, but send a copy of FIFO_Not_Empty
		  to the BSF FPGA

     2	 0x0000	  No scalers enabled for Timing Signal Reset

     3	 0x0000	  No scalers held in reset

     8	 0x0003	  Enable FIFO Empty and FIFO Full Error checking.  
		  DO NOT enable automatic error clearing (i.e. errors 
		  remain stored in Error Reporting Register until TCC 
		  manually clears them)
		  
		  **** NOTE: TCC should clear any initial errors in
		  **** the Error Reporting Register at Initialize time
		  **** A way to do this is to write 0x0003, wait for 
		  **** re-synch (21 us or less if everything's OK), 
		  **** then write 0x0203 (clearing errors), then
		  **** write 0x0003 again.  

    12   0x000f	  Test Data Reg A
    13	 0x000f	  Test Data Reg B

    16	 0x0001	  Select FIFO as output source     
         0x0002   Select TDR A as output source
		  
		  * NOTE: two different values shown, lower value used
		    only when there is no L2 Global
    
    25	 0x0000	  Disable HSRO
			    
    32	 0x0000   Meaningless in L2 applications